INESC-ID 3 Months Extension Report (2005)

By INESC-ID

May 2005

INESC-ID, BMT, UGR and UMH (WP4)

2

Contributions to this report This report includes written contributions and results of research work of: Prof. Moisés Piedade, Prof. José Gerald, Prof. Leonel Sousa and work developed by the undergraduate student Elísio Varela among other researchers. Also, aiming the architecture implementation of the intracortical prosthesis in VLSI circuits, it includes the written contribution and results of. Prof. Jorge Fernandes and Prof. Marcelino Santos.

3

Contents 1. Introduction .................................................................................................................. 4 2. Integrated Version - Electrodes Stimulator and Control Unit ...................................... 4

2.1 ADC and Backward Communication channel ....................................................... 4 2.2 Ongoing Work ........................................................................................................ 5

3. Integrated Version - Power Recovery .......................................................................... 5 3.1 Main Objectives...................................................................................................... 5 3.2 Milestones............................................................................................................... 5 3.3 Work accomplished ................................................................................................ 5 3.4 Results .................................................................................................................... 5 3.5 Deliverables ............................................................................................................ 8 3.6 Exploitation and dissemination activities ............................................................... 9

4. Design of a Prototype System Based on a FPGA......................................................... 9 4.1 Digital logic blocks................................................................................................. 9

4.1.1 Image capture and resize ................................................................................. 9 4.1.2 Register configuration ................................................................................... 12 4.1.3 Classic model implementation ...................................................................... 14 4.1.4 Serial communication protocol...................................................................... 14 4.1.5 Image display................................................................................................. 16

4.2 Remarks and results.............................................................................................. 18 5. Definition of the Architecture to Implement the Deterministic Model of the Artificial

Retina ......................................................................................................................... 20 6. Conclusions and Future Work .................................................................................... 22 Bibliography ................................................................................................................... 22 Project Published Bibliography in 2005......................................................................... 23

4

1. Introduction This report concerns the work developed in the context of CORTIVIS WP4 and WP2 by INESC-ID in the project 3 months extension (January – March, 2005). It describes the main activities and summarises the most relevant results. In what concerns the WP4, according to the planned, the work was oriented towards an integrated solution for the RF link. In this 3 months extension of the project, the work towards the RF-link integrated version continued. A full system RF-link coupling (including the secondary link inside-to-outside head communication) was simulated in computer. Also, a PCB of the secondary link was produced, although the respective experimental results are still ongoing. In what concerns the Electrode Stimulation & Control Unit (full “system on chip”), the work is described in Chapter 2. In what concerns the Power, the work is described in Chapter 3. In what concerns the WP2, the participation of INESC-ID in the CORTIVIS project, aim at the definition of the architecture to implement the deterministic model of the artificial retina. This work is described in Chapter 5. The major conclusions and future work are presented in Chapter 6.

2. Integrated Version - Electrodes Stimulator and Control Unit

2.1 ADC and Backward Communication channel To sense the signals applied to the electrodes we need to convert the Analog level to a digital form and modulate it. The ADC load to the electrode is critical as it can change the value to be measured. It has been studied a new input stage for a parallel structure which is based on a multi level pseudo differential comparator [1]. This input stage leads to a very low power, area, input capacitance, and able to work with supply voltage. The ADC architecture is based on this new comparator block with a suitable architecture based on the parallel architecture and a new Wallace tree encoder for error correction. The ADC frontend block is presented in Fig. 2.1.

VR n

vOUT n

VR1v IN 1

vIN 2

vOUT 1

V DD

Fig. 2.1: ADC frontend schematic.

5

2.2 Ongoing Work Although the project is ending we consider on continue working on it. Therefore an MSc thesis is still ongoing and we aim to design a prototype in a new technology AMS CMOS 0.35um with lower voltage supply and the circuits revised. This integrated prototype will be 2x2 Array with 1 mm2 just to validate the circuit architecture.

3. Integrated Version - Power Recovery

3.1 Main Objectives Efficiency optimization minimizing the power delivered in the primary side. This is expected to be accomplished taking advantage of the fact that when the secondary side of the transformer has no current, the current in the primary side is reduced. Thus by sensing the current in the primary side of the transformer it is possible to identify if the control circuit in the secondary is open or closed. With this information, it is possible to reduce the power delivered in the primary side to the minimum required for the operation with a given range of loads.

3.2 Milestones Feb 2005 – Study of different transformers (different ratios and wires), evaluating primary current under different secondary loads. May 2005 – Prototype of the discrete secondary rectification and regulation circuit with an on/off control (in the 3,3V regulation) that allows high efficiency and dynamic evaluation of the primary current changes. November 2005 – Primary circuit discrete implementation for optimization of the efficiency (reducing power in the primary when the secondary regulator opens due to excess of voltage after regulation).

3.3 Work accomplished The work is in schedule. The first two milestones were respected.

3.4 Results Figure 3.1 and 3.2 show the primary and battery currents for different loads in the secondary with a transformer with a 1:3 ratio. Figure 3.3 shows the schematic of the rectifier and 3,3V regulator. Figure 3.4 shows the waveforms of the gate control and output voltage during the operation of the implemented discrete circuit.

6

Figure 3.5 shows the current in the source of T1 (figure 3.1) during on and off states if the PMOS transistor in the secondary regulation circuit. This figure shows that different current are involved in the resonant E stage of the primary winding of the transformer and that is going to be used for optimization of the power delivered to the primary. Circuit:

C

R

V1

C1

213pF

C2

1,9nF

L2

198uH

1

2

R2

00 0

1 V

9

0

L1

1mH

1

2

V

R11

0

Vdc

V

L3

19,7uH

1

2

T1

Results:

RL [Ω] VR [mV] V1 [V] I1 [mA] P2 [W] VC [V] η (%)

100 71 15,8 71 1,12 4,84 20,98 120 76 15,8 76 1,20 5,16 18,57 150 79,6 15,8 79,6 1,25 5,44 15,77 220 89,2 16,3 89,2 1,45 6 11,32 270 92 16,1 92 1,47 6,28 9,92 330 95,2 16,1 95,2 1,52 6,6 8,66 390 98 16,1 98 1,57 6,84 7,65

Open secondary 114 16,1 114 1,82 7,1 -

Figure 3.1: Primary currents for different loads in the secondary with a transformer with

a Litz wire and a 1:3 ratio. Circuit:

C

V1

C1

213pF

C2

1,9nF

L2

198uH

1

2

R2

00 0

1

9

V

0

L1

1mH

1

2

V

R1 1

0

R

Vdc

V

L3

19,7uH

1

2

T1

7

Results:

RL [Ω] VR [mV] IR [mA] VC [V]

100 38,5 38,5 4,56 120 37,2 37,2 5,04 150 35,7 35,7 5,52 220 33,5 33,5 6,56 270 32,8 32,8 7,04 330 32,2 32,2 7,52 390 31,9 31,9 7,92

Open secondary 29,9 29,9 11,4

Figure 3.2: Battery currents for different loads in the secondary with a transformer with

a Litz wire and a 1:3 ratio.

4

V1

103

C10.1u

2C233u

10 10 22

2

R1590

2 22

Y2volts

4 3

R230

6 6

5 9

R4390k

99555

5

7 7

2 22

2

2 2

2

1

R8820

7

7

5 55

5

1Y1volts

5

Y3volts

2

7

R65k

2

2

7

6

C32u

6

6

111 11 1

5 55

5

1

111

2

5

R114.7k

5

R1210k

2

2228

9

10

X2IRFD9120

5

55 5

1

11 1

9

99 99

9

22

1

D2+

VCC

VEE

5

17

6

9

X4LM393T

9

9

2 2

77

66

9 9

9

Y4volts

9 99

9

2

9

R53.3k

2

22 210

X1BAT85p

8 2

X3BAT85p

Figure 3.3: Schematic of the rectifier and 3,3V regulator.

8

Figure 3.4: Waveforms of the gate control and output voltage during the operation of the regulation circuit.

Figure 3.5: Current in transistor T1 during on and off states if the PMOS transistor in the secondary regulation circuit.

3.5 Deliverables João Matos Maria, Miguel Almeida, "Transmissão de Energia sem Contactos para Prótese Visual Intracraniana", report for graduation on Engenharia electrotécnica e de Computadores, Instituto Superior Técnico, due in November 2004.

9

3.6 Exploitation and dissemination activities Poster presentation of the cortivis project in the Electronic Systems stand during the JEEC - “Jornadas de Engenharia Electrotécnica e de Computadores”, Instituto Superior Técnico, Universidade Técnica de Lisboa, April 2005.

4. Design of a Prototype System Based on a FPGA

4.1 Digital logic blocks In order to perform a validation of the retina processing module, the architecture was implemented in VHDL and tested on the developed prototype board. Only the Classic Model was implemented but an analysis of the Neural Networks was made towards determining the required hardware resources. The tests were made using only one color channel and an input represented in 8-bit grayscale, however a 12-bit representation was used internally to reduce computational and filter discretization errors. The considered dimension of the electrode array was 32×32. It was also necessary to develop other modules, Figure 4.1 represents the developed logic circuits.

Figure 4.1 - Digital logic block diagram.

Two modules were created for image acquisition, one to capture the input image and resize it and the other to make the power-on configuration of the digital camera internal registers. The resized image is then feed to the visual encoding module. This module produces two outputs, one is the train of action potentials that will be sent to the brain and the other is the firing rate that results from the retina model filtering. The data packing module prepares the spike information to be transmitted over a serial link. At last, the display module produces a screen visual image to allow the validation of the processing module. This module displays the input image, the spike information and the processed image before the spikes are generated. The synthesis results presented in the following subsections where achieved using the XILINX ISE WebPACK 6.2i synthesis tool with a XILINX SPARTAN-3 XC3S400-4 as target device.

4.1.1 Image capture and resize The input image was obtained using a digital camera module from Quasar Electronics [2] that uses Omnivision OV7620 [3] Complementary Metal-Oxide Semiconductor (CMOS) image sensor. All camera functions can be configured using a serial data transmission protocol, Serial Camera Control Bus (SCCB) [4], which is a simplified version of Philips Inter Integrated Circuit (I2C) [5] protocol. This camera is able to

10

capture a window size of 4.84 3.64 mm mm× generating an array of 644×492 with a pixel size of 7.6 7.6 m mµ µ× . The digital video port supports 60 Hz YCrCb 4:2:2 16-bit/8-bit format, Zoomed Video Format (ZV) Port output format, RGB raw data 16-bit/8-bit output format and CCIR601/CCIR656 format, with progressive or interlaced scan. It also has a black and white composite video signal output (VTO) in National Television System Committee (NTSC) format that can be used for test purposes. The sensor has a signal to noise ratio greater then 48 dB and a dynamic range of more than 72 dB. The supply voltage for this sensor is 5 V and it requires less then 120 mW when it is active and only 50 Wµ while in standby. This camera module includes lens with a focal length and an aperture of 6 mm and F1.6, respectively. The current retina model version only uses grayscale data and the camera is programmed to capture frames in Quarter Video Graphics Array (QVGA), at a frame rate of 20 Hz in non-interlaced mode. The camera module supplies three synchronization signals: vertical sync (VSYN), horizontal window reference (HREF) and pixel clock (PCLK). Frame synchronization is done by detecting a high pulse on VSYN and a new line occurs when HREF has a low pulse, Figure 4.2 shows the temporal diagrams for this two signals.

Figure 4.2 - Camera module sync signals. The PCLK is used to identify pixels on a line, the pixels information is updated every falling edge of pixel clock. This implies that pixel information can be read on the rising edge of PCLK. Another signal, odd field flag (FODD), is also required in order to only assert WE when FODD is high. A simple hardware can be used in order to capture the frames using these four synchronization signals. In Figure 4.3, it is shown the implementation used for this module [6]. The hardware costs of this synchronization device are 15 slices (1%) with a maximum operating frequency of 25 MHz . The developed processing module for this prototype was configured to have an input of only one color channel, in this case grayscale, and a frame window of 32×32. In a first approach, the desired window was obtained using only register configuration, but the image frames for this solution where very affected by noise. Another solution was to make an image resize: the visual frames were captured with a 128×128 window size and, using filtering followed by decimation, the image was reduced to 32×32 pixels. The filter main purpose is to avoid the aliasing generated by the decimation process, but it is also used to reduce some of the vertical noise. Three types of filters were considered: bicubic, Gaussian and bilinear. The chosen filter was a Gaussian low pass type with a standard deviation of two, since it provides good results and does not require much logic. The schematic representation can be seen in Figure 4.4, where the symmetry of the Gaussian was used to reduce the necessary logic, it uses less multipliers and less delay lines.

11

Figure 4.3 - Implemented hardware for frame capture. The hardware costs of this filter are 130 slices (3%) and 1 RAM block and the maximum operating frequency is 179 MHz .

x

x

x

x

x

Register

++ + +

Delay line

a1

a2

a3

a4

a0

+ ++

+

Inputpixel

Output pixelDecimaion

a 1x[n

+1]

a 2x[n

+2]

a 3x[n

+3]

a4x[n+4]

a 0x[n

]

a 1x[n

]a 2x

[n]

a 3x[n

-3]

a 4x[n

]

a 2x[n

+3]

a 1x[n

+2]

a 1x[n

+3]

a 0x[n

+1]

a 0x[n

+2]

a 0x[n

+3]

a 2x[n

+1]

a 3x[n

-2]

a 3x[n

-1]

a 4x[n

+2]

a 4x[n

+3]

a 4x[n

+1]

a3x[n+4]

a2x[n+4]

a1x[n+4]

a0x[n+4]p[n]

p[n-1]=

x[n+4]

Y[n]

a 2x[n

-1]

a 1x[n

-1]

a 2x[n

-2]

a 4x[n

-4]

a 4x[n

-2]

a 4x[n

-1]

a 4x[n

-3]

a 3x[n

]

a 3x[n

+1]

a 3x[n

+2]

Figure 4.4 - Spatial low pass Gaussian filter.

12

4.1.2 Register configuration A new hardware module was developed to improve the output image of the digital camera. This independent system was only designed to experiment new register settings, although the VHDL core had to be included in the main design in order to make the register configuration at setup time. To allow a more flexible operation, the VHDL core receives data with the register settings from a PC through the Digilab 2 [7] parallel port. The data is sent by a simple program written in C language. Figure 4.5 shows the connections diagram for this module.

Figure 4.5 - Block diagram for register configuration module. Initially, the camera composite video output, VTO, was used to evaluate the resulting image. However, this more simple solution had to be put aside as it was necessary to adjust the frame rate to achieve better results. The block diagram of the developed system is shown in Figure 4.6.

Figure 4.6 - Register configuration block diagram. The control program supplies the register address and value to the VHDL core and stores the register configuration in a file. A first VHDL block, epp2, only reads the programming data from the parallel port and then stores it in a dual port RAM; this block has a counter that is incremented whenever a new byte is received. The dual port RAM is also connected to a second block, program_regs, responsible for the interface with the camera using the SCCB protocol. The protocol was implemented using a hierarchical three level state machine as shown in Figure 4.7.

13

Figure 4.7 - Block diagram of the program regs. The first layer, camera_config, sends commands to enable a read or a write cycle and supplies the register address and the value, which were stored in the dual port RAM. The cycle is initiated when a button on Digilab 2 is pressed. The next layer consists of two state machines: one to implement the write cycle (write_cycle), and the other the read cycle (read_cycle), only one is active at a time. The third layer does the interface with the camera module. The last layer is responsible for generating all the bit sequences necessary to implement the SCCB protocol. A write and a read cycle are shown in Figure 4.8 and 4.9, respectively.

Figure 4.8 - Write cycle.

Figure 4.9 - Read cycle. After achieving a suitable register configuration, the PC interface is no longer necessary. A modified version of this system was included in the main design, in order to make the power-on configuration. In this solution, the configuration values are stored in a ROM memory block and only write operations are necessary. This register configuration device requires a total of 114 slices (3%), operating at a maximum frequency of 191 MHz .

14

4.1.3 Classic model implementation The employed implementation only processes one of the RGB channels and considers space-time separability. The global FPL architecture for one RGB channel is shown in Figure 4.10.

Figure 4.10 - Early Layers FPL full architecture. Figure 4.11 shows the adopted FPL architecture for the Spike Generation. This model was used in order to test the developed prototype board and also the other developed hardware modules. The complete model, including the CGC block, occupies a total of 365 slices (10%) and 7 RAM blocks (43%), and has a maximum operating frequency of 86 MHz .

Figure 4.11 - Integrate-and-fire adopted architecture. 4.1.4 Serial communication protocol The function of this hardware module is to create the packet structure defined in WP4. Figure 4.12 represents the adopted hardware implementation. The function of each block can be described as follows:

• Dual Port RAM, storage element of the FIFO memory;

• counter_5, bit counter, also generates the number of sent events;

• SUB, generates the number of events waiting to be sent;

• MUX, selects the data to be loaded into the output buffer;

• out_buffer, sends the data to the RF modulator; with a parallel load, it stores the data corresponding to a given chunk of the packet;

15

• State Machine, this Mealy state machine generates all the control signals necessary to perform the packet formatting; it also manages the read pointer of the FIFO memory; the output from the counter_5 and result of SUB are input signals to the state machine.

Figure 4.12 - Data packing block diagram. This module requires 148 slices (4%) and 1 RAM block (6%), operating at maximum frequency of 121 MHz . It was also necessary to develop a hardware module capable of receiving and unpacking the output data of the RF link demodulator. The implementation of this hardware device is shown in Figure 4.13.

Figure 4.13 - Data unpacking block diagram.

16

The function of each block can be described as follows: • in_buffer, shift register that stores incoming data;

• counter_5, bit counter, also generates the number of send events;

• event_data, stores the recovered spike information that will be written in the memory;

• num_events, stores the number of events from the current packet;

• comp1, active when a new packet is detected;

• State Machine, generates all the control signals necessary for the data unpacking; it also controls the write signal and the write pointer of the Dual Port RAM; the output from counter_5, the num_events signal and the result of comp1 are the input signals for this state machine;

• Dual Port RAM, implements a spike buffer,

• Counter, uses the signal data_valid from the State Machine and the output of comp2 to manage the read pointer of the Dual Port RAM.

This unpacking module was implemented on a Xilinx Spartan XC2S200 requiring 72 slices (3%) and 3 RAM blocks; the maximum operating frequency is 57 MHz . 4.1.5 Image display To verify the proper functioning of the artificial retina processing module, an output stimulus display module was included in the design. This module should generate all synchronization signals necessary for the standard VGA monitor. The adopted configuration uses a resolution of 640×480 and a refresh rate of 60 MHz . Figure 4.14 shows the temporal diagram of the VGA signals and Table 4.1 the necessary timings for the signals.

TPW Tbp TfpTdisplay

TS

H/V SYNC

R/G/Bsignals

Figure 4.14 - VGA timing diagram.

The circuit of Figure 4.15 fulfills this task. As the captured image is in grayscale, so is the output. Also, since an array of 32×32 pixels if very small for visual analysis, the output image was enlarged four times by repeating the same pixel of the original image 16 times in the output image resulting in a window of 256×256 pixels. Although this module is relatively simple, namely required additional RAM. The signals generated by this circuit only control the image display. This device requires 37 slices (1%) and uses 2 RAM blocks; the maximum operating frequency is 204 MHz .

17

Table 4.1 - VGA Timings [7].

Symbol Parameter Vertical Sync Horizontal Sync

ST Period 16.7 ms 32 sµ

dispT Display time 15.36 ms 26.5 sµ

pwT Sync pulse width 64 sµ 3.84 sµ

fpT Sync front porch 320 sµ 640 ns

bpT Sync back porch 928 sµ 1.92 sµ In order to validate the actual spike generation it was developed a module that recovers the image using the spike information [6]. This recovery system was implemented by using a low-pass filter with a very low cutoff frequency. To decrease the filter size it was used an Infinite Impulsive Response (IIR) filter, with the following transfer function

1 2 1 22

. ( ) ( ) ( ) ( )

c c c cH ss a s a s a

= =+ + +

(4.1)

where 1c and 2c are gain coefficients. This filter can be implemented using a chain of two low-pass IIR filters, equation. The discrete filter chain requires coefficients with a higher value than the second order filter. Hence, the filter chain makes the implementation less sensible to discretization errors. The adopted design implements the filter chain requiring 98 slices (2%), 2 RAM blocks and 2 multipliers. The maximum operating frequency is 91 MHz .

CounterMOD 800

CLK Q

COUNT/STOP

CounterMOD 521

CLK Q

COUNT/STOP

>=656

<752

<640

<480

>=490

<492

CLK

‘1’

‘1’

HorizontalSync Pulse

VerticalSync Pulse

Blank

Line count

Column count

Bit Vector

Bit

DIV2

Columnaddressing

section

Lineaddressing

section

Figure 4.15 - VGA monitor control circuit [6].

18

4.2 Remarks and results Table 4.2 presents the implementation costs of the developed prototype. This table includes the hardware costs of all the developed digital circuits. Considering the results shown in Table 4.2, this new platform achieves the proposed objectives. It implements the complete system with a high operating frequency and using a small amount of hardware resources. To achieve an independent spatial processing, only the space calculus would be replicated. As the hardware resources for the classic model are only 10% of the total slices, this system allows the implementation of the classic model considering independent spatial processing for the three RGB channels. The power requirements also follow the expected results: using the full implementation of the digital blocks on the FPGA the board requires 450 mW , value that increases to 950 mW when the digital camera is connected. The usage of the VGA output, with a conversion rate of 12.5 MHz for the DACs, requires 1.2 W . Regarding to the previous prototype [6] the relative power consumption is about 50% less (1.8 W ). Figure 4.16 presents a picture of the complete prototype system.

Figure 4.16 - Complete prototype system. In order to test the processing model on the new board, a switch was used to control the information shown in the display device. By using this switch, the output image can be set to display the output of the Early Layers or the recovered image from the spike output. Also, using another switch, it is possible to remove the temporal high-pass filter. Figure 4.17 shows the output images obtained from the prototype. The input image resized is on the upper left corner and the processed image is on the lower right corner.

19

The output image from the Early Layers when the high-pass filter is included was obtained by moving the camera. This resulted, as expected, in an image were only the moving edges are displayed. When the filter is removed, the resulting image only presents the shapes of the objects. In order to test the spike generation the input of the Neuromorphic Pulse Coding was set to be the input resized image. The results followed the expected model behavior. The developed board also operates as expected and the output image is slightly better when compared with the previous developed board. The developed board can also be employed as a development platform for a different system, since it offers a total of 61 I/O pins in which 6 are global clock pins. These connectors also provide a power source to a possible expansion module. The camera connector provides a 5 V supply and the generic connector provides 5 V , 3.3 V and the unregulated input voltage. The video port uses 8-bit per RGB channel, generating a true color video format, and the video DAC has a maximum conversion rate of 20 MHz . This video port makes this board suitable for image processing, although for bigger image frames it might be necessary to introduce a memory expansion module.

Table 4.2 - Complete Artificial Retina system implemented on a Xilinx Spartan XC3S400 FPGA.

Block Slice Occupation

Operating Frequency ( MHz )

RAM Blocks(Total 16)

Multipliers (Total 16)

Image Capture And Resize 3% 178 1 0

Register Configuration

3%

190

0

0

Classic Model* 10% 85** 7 3

Serialization and

Data Packing 4% 121 1 0

Image Display 3% 91 4 2

Data Unpacking*** 3% 57 3 0

Complete System 20% 85 12 5

* includes Image Capture and Resize ** 49 clock cycles are required to process each pixel *** synthesized on a Xilinx Spartan XC2S200 FPGA

20

input image

spatial filtering only

retina model output

recovered from spike information

Figure 4.17 - Photograph of the experimental results obtained with the artificial retina prototype.

5. Definition of the Architecture to Implement the Deterministic Model of the Artificial Retina

The architecture for implementing the bio-inspired processing module of the artificial retina model is composed by two distinct modules: Retina Early Layers and Neuromorphic Pulse Coding. Figure 5.1 represents the block diagram of this bio-inspired processing module.

Figure 5.1 - Classic Bio-Inspired processing module.

The Retina Early Layers is introduced in the previous section for the classic model and the Neuromorphic Pulse Coding generates the action potentials using the instantaneous firing rate. This last block will be described in the present section. It is specified that the Retina Early Layers module should be able to process frames at a maximum rate of 100 Hz and that the maximum spike rate generation for the Neuromorphic Pulse Coding can be up to 1 kHz per cell [8].

21

Figure 5.2 - Retina Early Layers diagram. The spatial calculus is done using one DoG fillter if space-time independency is considered. Nevertheless, the spatial filtering should be done using two Gaussians in order to independently convolve the center and surround, since several authors have suggested that space-time filtering is not completely separable [9, 10]. Thus, this implies the use of a low pass filter after each gaussian. With such architecture it is not only possible to implement space-time dependent models, but also the one with space-time separability, as depicted in Figure 5.2. As different colors are treated differently by the retina, the spatial filter can be expanded into three separated filters, one per each RGB channel. As depicted in Figure 5.2, considering space-time dependency there will be six receptive fields, two per RGB channel. The time filtering is done using a high-pass filter. The Contrast Gain Control (CGC) non-linear function was implemented using a look-up table and the low-pass filter. As the human brain responds to action potentials, the instantaneous firing rate at the output of the Early Layers must be modified to meet this new representation. This task is carried out by the Neuromorfic Pulse Coding block. A first approach to fulfill this goal is to use the standard integrate-and-fire mechanism. To improve this model, some modifications were suggested: (1) a leakage factor in the integrator [11]; (2) a spike height modulation factor [12]. Integrate-and-fire was implemented using a simplification: the spike amplitude remains constant, only the leakage factor was included. This solution decreased the needed hardware as it requires less memory. Figure 5.3 shows the schematic representation of this block.

Figure 5.3 - Integrate-and-fire block diagram. The module can be described by (5.1) and (5.2)

[ , ] [ , ] . [ , - 1] - [ , - 1] - acc accP n F n P n pulse n dγ= +q q q q (5.1)

22

[ , ] ( [ , ] - )accpulse n H P n φ=q q (5.2)

where γ is the feedback loop gain, d is a leakage factor, φ is the firing threshold and q represents the discrete spatial dimensions.

6. Conclusions and Future Work In the 3 month extension period of Cortivis project, the integrated version of the RF-link was continued. Progresses were made in the secondary RF-link (from inside to outside head), in the ADC structure of the Electrodes StimulatorUnit, and in the Power Recovery Unit. In the secondary RF-link (from inside to outside head), a full system was simulated in computer, and a PCB experimental prototype was implemented. Experimental results are sill ongoing. In the Electrodes StimulatorUnit an MSc thesis is ongoing and the design of a prototype in a new technology AMS CMOS 0.35mm with lower voltage supply was continued. In the Power Recovery Unit different transformers (different ratios and wires) were studied, evaluating primary current under different secondary loads. Also, it was designed a prototype of the discrete secondary rectification and regulation circuit with an on/off control (in the 3,3V regulation) that allows high efficiency and dynamic evaluation of the primary current changes. The work towards the goal of implementing a VLSI (0.35 m) chip with both the main and secondary links, as well as the power recovery unit, the electrodes stimulator unit and the control unit goes on after the end of this Cortivis project. It was finished the work regarding the design of a prototype system based on a FPGA. It was designed the digital logic blocks.

Bibliography [1]. Jorge R. Fernandes, Manuel M. Silva, “A Very Low-Power CMOS Parallel

A/D Converter For Embedded Applications”, ISCAS’04, May 2004. [2]. Quasar Electronics Ltd. C3188A - 1/3" Color Camera Module With Digital

Output. http://www.electronic-kits-and-projects.com/kit-files/cameras/d-c3188a.pdf.

[3]. OmniVision Technologies Inc. OV7620 - Single-Chip Cmos Color Digital Camera. http://mxhaard.free.fr/spca50x/Doc/Omnivision/OV7620.pdf.

[4]. OmniVision Technologies Inc. The Serial Camera Control Bus Functional Specifications. http://www.ovt.com/pdfs/ds note.pdf.

[5]. Philips Semiconductors. THE I2C-BUS SPECIFICATION. http://www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf.

[6]. Pedro F. Z. Tomás. Bio-inpired processing module for the development of an artificial retina. Graduation Report, Instituto Superior Técnico, Lisbon, 2003.

23

[7]. Digilent Inc. Digilab 2 Reference Manual. http://www.digilentinc.com/Data/Products/D2/D2-rm.PDF.

[8]. P.F. Tomás. Bio-inspired processing module for the development of an artificial retina. Graduation Report, Instituto Superior Técnico, Lisbon, 2003.

[9]. B.A. Wandell. Foundations of Vision. (Sinauer Associates, Sunderland, Massachusetts, 1995).

[10]. M. Meister and M.J. Berry II. The neural code of the retina. Neuron, 22:253–450, March 1999.

[11]. J. Keat, P. Reinagel, R.C. Reid, and M. Meister. Predicting every spike: A model for the responses of visual neurons. Neuron, 30:803–817, June 2001.

[12]. R. Moreno and N. Parga. Firing rate for a generic integrate-and-fire neuron with exponentially correlated input. Lecture Notes in Computer Science of Springer-Verlag Heidelberg, 2415, 2002.

Project Published Bibliography in 2005 [13]. José Gerald, Gonçalo Tavares, Moisés Piedade, Elísio Varela, “Wireless

transmission of power and data to implants,” Proc. 5th Conference on Telecommunications, Tomar, Portugal, April 2005.

[14]. José Gerald, Gonçalo Tavares, Moisés Piedade, Elísio Varela Ricardo Ribeiro, “RF link for cortical neuroprosthesis,” Proc. ISCAS’05 – 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 2005.

[15]. Leonel Sousa, Pedro Tomás, Francisco Pelayo, Antonio Martinez, Christian A. Morillas, Samuel Romero, New Algorithms, Architectures and Applications for Reconfigurable Computing, chapter 22: "Bioinspired stimulus encoder for cortical visual neuroprostheses", Springer-Verlag, January 2005.

[16]. Sérgio Capela, Sérgio Martins, Leonel Sousa, "Processing Module for the Development of an Artificial Retina", Graduation thesis, Instituto Superior Técnico, Universidade Técnica de Lisboa, July 2005.

[17]. José Germano, Ricardo Baptista, Leonel Sousa, "Configurable Platform for Real Time Video Processing and Vision Systems", accepted for publication on DCIS 2005, November 2005.

[18]. João C. Martins, Leonel A. Sousa, "Performance Comparison of Computational Retina Models" accepted for publication on VIIP 2005, September 2005.