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A GENERAL PURPOSE GRAPHICS PROCESSOR.
Item Type text; Thesis-Reproduction (electronic)
Authors Morreale, Jay Philip.
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University: Microfilms
International 300 N.Zeeb Road Ann Arbor, Ml 48106
MORREALE, JAY PHILIP
A GENERAL PURPOSE GRAPHICS PROCESSOR
THE UNIVERSITY OF ARIZONA
University Microfilms
International 300 N. Zeeb Road, Ann Arbor. MI 48106
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University Microfilms
International
A GENERAL PURPOSE GRAPHICS PROCESSOR
by
Jay Philip Horreale
A Thesis Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL ENGINEERING
In partial Fulfillment of the Requirements For the degree of
MASTERS OF SCIENCE
In the Graduate College
THE UNIVERSITY OF ARIZONA
19 8 4
STATEMENT BY AUTHOR
This thesis has been submitted in partial fulfillment of requirements for an advanced degree at the University of Arizona and is deposited in the University Library to be available to borrowers under rules of the Library.
Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgement of the source is made. Requests for permission for extended quotations from of reproductions of this manuscript in whole or part may be granted by the head of the major department or the Dean of the Graduate College when in his judgement the proposed use of the material is in the interest of
scholarship. In all other instances, however, permission must be obtained from the author.
SIGNED
APPROVAL BY THESIS DIRECTOR
This thesis has been approved on the date shown below:
L.P. Huelsman Professor of Engineering
Da te
ACKNOWLEGMENTS
I would like to thank several people for their help
on this project. First, to Robert W. Freund for his help in
trouble shooting the proto-type boards. Second, to Tom
Meersman for drawing the figures and illustration in this
document. Third, to Dr. Huelsman for his continued support
throughout this project. Last, to my parents Phil and
Virginia Morreale.
Jay P. Morreale 11 March 84
i i i
TABLE OF CONTENTS
LIST OF ILLUSTRATIONS.. v
LIST OF TABLES vii
ABSTRACT ix
1. GRAPHICS CONTROLLER. 1
Raster Scan Graphics 4 GDC and Timing Board 5 Host I/O Write 6 Host I/O Read 10 Slave I/O Read........ 11 Slave I/O Write 12 Display Cycle 14 RWM Cycle 20 Zoom Control 22 Configure Control 24 N0N-S-100 Bus Characteristics 26
2. SLAVE PROCESSOR 27
Initialization 29 S-100 Bus Interface 32 Host Command Port 33 Host Status Port 36 Host Response Port 38 Host Control Port 38 NON-S-lOO Bus Characteristics 40 Slave S-100 Bus Interface........ 40 Slave Status Port.... 41 Slave Command Port. 44 Slave Response Port 45 Slave Processor Memory Interface 46 Slave Memory Read 46 Slave Memory Write 52 Host Processor RAM interface 52 Host Memory Read 53 Host Memory Write 57 N0N-S-100 Bus Characteristics 58
i v
V
TABLE OF CONTENTS--continued
3 . SOFTWARE 59
Host Memory Configuration 61 A Forth Application 63 A Colon Definition 67 A Code Definition 72
APPENDIX A: 8088 FORTH ASSEMBLER 76
APPENDIX Bi FORTH METACOMPILER 90
APPENDIX C: 8088 FORTH 94
APPENDIX D: THE PROTO-TYPE 129
REFERENCES 137
LIST OF ILLUSTRATIONS
Figure Page
1. Slave Processor Block Diagram 2
2. Display Generator Block Diagram 3
3A. Graphics Pocessor S-100 Bus Interface 7
3B. Graphics processor bus interface and buffering... 8
4. Host I/O timing diagram.. 9
5. Graphics Processor Display Timing 13
6. Slave 1/0 Timing,.,,. 15
7A. Graphics Processor Display RAM - Red 16
7B. Graphics Processor Display RAM - Green.. 17
7C. Graphics Processor Display RAM - Blue 18
8. Display Memory Timing Diagram 19
9. Read-Write-Modify Display Cycle Diagram....... 21
10. 2X Zoom Factor Timing Diagram 25
11. 8088 Slave Processor 30
12. Slave Processor I/O Interface 34
13. Host FIFO I/O Timing Diagram 35
14. Slave FIFO I/O Timing Diagram 42
15. Slave Processor Memory Map 47
16. Slave Processor Memory Interface 48
v i
vii
LIST OF ILLUSTRATIONS--continued
Figure Page
17. Slave Processor RAM Timing Diagram 49
18. Host Memory Interface 54
19. Host RAM Timing Diagram 55
20. Host Memory Map 62
21. Host-Slave Coprocessor Flowchart 68
22. Memory Map of a Colon Definition 69
23. Memory Map of a Code Definition 74
24. Slave Processor Layout Diagram 130
25. Slave Processor Photo 131
26. Graphics Controller Layout 132
27. GDC and Timing board Photo 133
28. Graphics Memory Layout 134
29. Display Memory Board Photo 135
30. System Photo 3-36
LIST OF TABLES
Table Page
1. Slave Processor I/O Port configuration 11
2A. Zoom Command Byte 23
2B. Configure command byte 24
3. 8088 Microprocessor Reset States 32
4. Slave Processor Port Assignments 33
5. Host Control Port Bit Functions 40
6. Slave Processor 1/0 Port Assignments 41
7. Status Port Bit Functions 44
8. Slave Processor Address Decoding 51
9. Host Address Selection 56
10. Host/Slave Address Selection 56
v i i i
ABSTRACT
The General Purpose Graphics Processor is a high
resolution raster graphics subsystem in an S-100 bus
microcomputer system. This subsystem consists of three
logical components. First, an 8088 microprocessor and
support circuitry provide additional computational power for
intelligent image processing and generation. This
intelligence is supported by a customized FORTH kernel which
provides graphics software support not available from the
hardware. Second, and NEC 7220 Graphics Display Controller
chip and associated circuitry generates all basic video
timing and some image generation functions. Third, the NEC
7220 GDC reads and writes to three memory planes to create
eight color images. Additional circuitry continuously scans
this display memory and sends it to a color monitor for
viewing. This system, thus, will display color images with
an 640 horizontal by 480 vertical non-interlaced resolution.
ix
CHAPTER ONE
GRAPHICS CONTROLLER
*
The general purpose graphic processor is a S-100 bus
graphics subsystem capable of generating high resolution
color images. This graphics system consists of three boards
(see figures 1 and 2). First, a slave processor card,
containing an 8088 microprocessor, a FIFO bus interface, 8k
bytes of dual port RAM, 16K of EPROM, will serve the host
processor (Z80) as an intellegent interface to the GDC chip.
The host processor, for example, can generate complex images
by passing single byte commands to the slave processor via
the FIFO command-port interface. The 8088 microprocessor, in
turn, interprets these commands and calls the appropriate
routines from EPROM to instruct the GDC to generate the
desired image. These EPROM routines are part of a
customized FORTH kernal which can compile and link new
command routines into the slave processor memory space.
These commands can be used at any time, and with existing
commands in EPROM. Furthermore, the slave processor can be
programmed in high level Forth, and 8088 Forth assembly
language from other languages like basic, host (Z80)
1
TO NEC7220
INTERFACE
S-100 BUS
TRISTATE
SWITCH
16 K I 8
EPROM
B K t B
RAM
HOST
PROCESSOR
INTERFACE 8284 CLOCK CHIP
INTERFACE
8087
CO-PROCCSSOR
8288 BUSS
CONTROUER
Figure 1. Slave Processor Block Diagram.
N)
* HSYNC *• VSYNC
GEN* FROM
SLAVE PROCESSOR
TRISTATE SWITCH DATA CONTROL
NEC
7220
GDC
ZOOM
C0N1G
PORT
ADDRESS CONTROL
S-100 BUS ]
GREEN
BLUE
RED
MEMORY PLANE
I024H » 1024 V
CONTROL
SHIFT
REGISTER
AND
DRIVERS
DlSPLfff TIMING
BREED
BLUE
RED
Figure 2. Display Generator Block Diagram.
Lo
4
assembly language, or from ASCII files and a simple loader
to allow the most flexible interface possible. Second, a
NEC -7220 GDC and timing card generates all RGB video timing,
display zoom timing, display resolution, display memory
refresh, and image generation. The GDC, in particular, is
capable of creating arces, circles, polygons, lines,
graphics characters, and it can even fill polygons. Last,
the third board contains 348k bytes of display RAM, video
shift registers, and some address decoding. The resulting
configuration will, thus, generate an images of 640H by 480V
pixels noninterlaced in eight colors within a larger image
buffer of 1024H by 1024V pixels.
Raster Scan Graphics
Every displayed image is made up of individual dots
and must be redrawn on the screen more than thirty times a
second to prevent the image from flickering. The displayed
image, thus, must be kept within a display memory so the
display can be update at this rate. Each memory element or
bit in display RAM, in turn, corresponds to one dot or pixel
of the image. Multiple memory planes, on the other hand,
can be use to generate color images or images with multiple
shades. Three display memory planes, for example, will
provide eight shades of gray or eight colors. In color
image generation, in particular, each memory plane holds
5
data for a single color - red, green, or blue, The red,
green, and blue memory planes are designed so that each
plane will sequentially send pixel information to the
corresponding red, green, and blue inputs of a color
monitor. Other signals, horizontal sync, vertical sync, and
blanking are used to tell the monitor when to begin and end
each horizontal line, when to begin a new vertical line, and
when not do any thing - retrace, respectively[1][2].
GDC and Timing Board •
T he heart of the graphics processor is the NEC 7220
graphics display controller (GDC) chip[3]. The GDC
simplifies raster scan graphics systems by generating all
display timing and by controlling the display memory. The
GDC for example, can manipulate up to 256k by 16 bits of
display RAM which will produce a maximum possible picture of
1024 horizontal by 1024 vertical pixels, the GDC, also, can
draw lines, arches, circles, polygons, fill polygons, and
produce a multitude of special graphics characters. One to
sixteen zoom magnifications, panning, two independent
scrollable areas, and programmable raster parameters are
also part of the GDC repertoire of functions. Vhat a
powerful chip! The current graphics processor
implementation, however, does not use all the GDC
capabilities. Although the circuitry is present for four
6
memory planes, for instance, only three memory planes are
implemented. Also, all characters must be displayed as
graphics characters, and direct memory access (DMA) and
light pen interfaces have not been utilized. The current
design, on the other hand, will provide three display
configurations such as 320H by 240V pixels noninterlaced,
640H by 480V interlaced, and 640H by 480V pixels
noninterlaced. Calculations will show that the above active
viewing area,; in particular, does not fill the entire
available display RAM. The remaining display RAM can be used
for fast frame swapping for animations, or for windowing
larger images.
Host I/O Write
The host processor may read and write to the GDC
board through three input-output S-100 bus ports (see
figures 3a, 3b and 4). The host may, for example, write to
the command register of the 7220 GDC chip by executing an
OUT instruction like OUT 31H. This example assumes that the
I/O ports address switch selection is set to I/O base
address 30H. As a result, S-100 bus signal, PSYNC, goes
high at the rising edge of the first clock cycle (BSl), and
the address lines and status lines become stable. The board
select line, BDSEL*, line from the eight bit address
comparator (U2) will go low. Since GEN* is assumed to be
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Figure 4. Host I/O timing diagram.
10
high (allowing host access), and BDSEL* is low, the 74LS138
one of eight decoder (U3) is enabled, and output Y2 will go
low. The output of the NAND gate U6 then goes low. Second,
PUR* goes low at the rising edge of the next clock cycle
(BS2). Now since the output of NAND gate U8 and PVR* are
both low, the output, HWR*, of the OR gate U6 goes low. With
HWR* low, the data on the data bus is sent to the 7220 GDC
chip. HWR* is allowed through the tristate buffer U9 as WR*.
Third PUR* returns high at the rising edge of the next clock
cycle causing UR* (HWR*) to return high. The rising edge of
WR* cases the data to be latched into the 7220 GDC chip.
Last, by the end of the next clock cycle (BS3), the address
and status lines become unstable causing BDSEL* to go high
and deselecting the board[4].
Host I/O Read
The host processor may also read two of the five bus
1/0 ports by executing an input instruction like IN 31H. A
read from port 31H, for example, allows the host access to
picture data, cursor position, or light pen address. This
read operation is the same as the write operation except in
the following ways. ' First, PDBXN is inverted to create
PDBIN* which goes low at the rising edge of clock cycle BS2
instead of PWR*. Since the output of the NAND gate U8 is
low, HRD* goes low which allows data from the 7220 GDC chip
11
out onto the S-100 data bus. HRD* also propagates through
the 74LS244 tristate buffer U9 to become RD*. Second PDBIN
returns high causing the data to be latched into the host
processor t a 280 in this case, and HRD* and RD* also return
high. With HRD* high the tristate buffer U4 tristates
preventing the data from the GDC from going onto the bus
data lines. Last, shorty after PDBIN* goes high the address
and status lines become unstable deselecting the board. This
ends the host read.
Table 1. Slave I/O Port Configuration
PORT
BASE+0 BASE+1 BASE+2 BASE+3 BASE+4 BASE+5 BASE+6 BASE+7
READ
GDC STATUS FIFO DATA
WRITE
FIFO DATA GDC COMMAND ZOOM/CONFIGURE
Slave I/O Read
When the host processor enables the slave processor
through the slave processor control port, the slave
processor has access and control of the 7220 GDC chip and
otheT board timing features just as the host processor did
in the previous examples. GEN*, in particular, is low when
the slave processor is in control. GEN* disables the
12
74LS138 one of eight decoder U3 and half of the 74LS244
tristate buffer U9. In this state the all host processor
accesses would be ignored. The slave processor, however,
has access to the GDC at a n y time. A read operation, for
example, occurs when the slave processor executes an IN 02H
instruction (port addresses are fixed). As a result,
Address latch enable, ALE, Goes high in the first half of
slave clock cycle T1 (see figure 5). The address lines
become stable and are latched. G10R* goes low and is passed
through half of the tristate buffer U9 creating RD*. GIOR*
returns high at the falling edge of clock cycle T4 causing
the data to be latched into the slave processor, an 8088.
Last, RD* goes high and the output of the 7220 GDC tristates
ending the read operation.
Slave I/O Write
The slave processor may also write to the 7220 GDC
chip by executing an output instruction like OUT 41H. The
resulting operation is the same as the above read operation
except for the follow differences. First, GIOW* goes low at
near the falling edge of clock cycle T3 instead of GIOR*.
The data from the slave processor is stable and is passed to
the 7220 GDC through the 72LS245 tristate transceivers U52.
Second, GIOW* returns high causing WR* to go high latching
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14
the data into the 7220 GDC. Last, the data and address
become unstable ending the write operation.
Display Cycle
With a IX zoom factor and a 640H by 480V pixel
non-interlace configuration, the 7220 GDC and associated
hardware generates an image by sending three streams of
serial data to a color monitor in the following manner.
First, the pixel clock, 0SC-CLK1, is divided by eight by a
74LS163 four bit counter U22 (see figures 6,7a, 7b, 7c, and 8)
to generate 2xWCLK. A display cycle consists of two 2xUCLK
clock cycles. Second, address latch enable, ALE, goes high
within the first quarter of the first 2xWCLK clock cycle Dl.
A pixel clock later row address select, RAS, goes high and
LOAD-MASK* goes high on the falling edge of 2xWCLK. Second,
in this configuration CONF-EN is always enabled (high), so
the 74LS194 four bit shift register, U21, shifts and ROW
goes high. Both RAS and ROW are HANDED with ALE to create
RAS-GEN* and ROW-ADDR-SEL respectively. Third, two pixel
clocks later column address select, CAS, goes low and is
NANDED with ROW to generate CAS-GEN*. Fourth, ALE goes low
before the rising edge of the next 2xWCLK clock cycle (D2)
which causes the 7220 GDC address lines to become stable. A
short time later RAS-GEN* goes low latching the address into
the 74LS374 tristate octal latches U30 and U32.
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Figure 8. Display Memory Timing Diagram.
20
ROV-ADDR-SEL remains high for a short time to allow the row
address to appear at the address lines of the dynamic
display RAMS. Uhen ROW-ADDR-SEL finally goes low the column
address is presented to the display RAMS. Shorty after
ROW-ADDR-SEL goes low CAS-GEN* goes low. Fifth, RAM data
becomes stable in the first quarter of the second 2xWCLK
clock cycle D2. Sixth, video shift register load, VSR-LD,
goes high for one pixel clock cycle latching the RAM data
into the shift registers. Last, ALE goes high in the last
quarter of the next clock cycly ending the current display
cycle. The current pixel data within the shift registers,
however, will be shifted out during the next display cycle.
RWM Cycle
A read-write-modify cycle is used to update the
display memory. The RUM cycle is similar to a display cycle
but requires four 2xWCLK cycles to execute. First, ALE goes
high during the first 2xWCLK clock cycle (El) causing
RAS-GEN* and ROW-ADDR-SEL to go high (see figure 9). The
address also becomes stable during this time. Second, ALE
returns low before the next 2xWCLK (E2) causing RAS-GEN* to
go low. RAS-GEN*, in turn, latches the address into the
74LS374 tristate latches U30 and U31. ROW-ADDR-SEL remains
high so that the row address is sent to the display RAMS. A
short time later ROW-ADDR-SEL goes low and the column
El E2 E3 E« ES
2XWCLK
ALE
ADt5-AD0
DBIN#
we#
RAS-GEN#
CAS -GEN*
ROW-ADDR-SEL
ROW/COL ADM
RAU DATA OUT
RAW DATA IN
VSR-LD
VSR-EN
VD-BLANK
VIDEO OUT
j 1 r j 1
-( valid Appi»eii~^-
J L _J
X
1
"x x-sor
i i I I 1 r
i f
/ VALID \ r
COtUMM ADDRESS
VALID OATA OUT
VALID OATA OUT x. VALID ADME3S
i r
(VALID OATA X
J~L
X
J L_
r 1
XZZDO
Figure 9. Read-Write-Modify Display Cycle Diagram.
22
address is sent to the display RAMS. CAS-GEN* then goes low
allowing the display RAMS to latch the address. Third, data
bus in, DBIN*, goes low before the rising edge of the next
clock cycle (E3) which allows the 7220 GDC access to the
data by enabling the two 74LS244 tristate octal buffers U32
and U33 (if the memory access is in the first memory plane).
Fourth, VSR-LD goes high latching the data into the shift
registers. Fifth, DBIN* returns high before the last 2xWCLK
clock cycle, and latches RAM data into the 7220 GDC for
modification. During the last 2xWCLK clock cycle (E4) write
enable, WE*, goes low and modified data from the 7220 GDC
becomes stable. Last, the modified data is then latched
into the display RAMS on the rising edge of the next 2xWCLK
cycle ending the RWM cycle. The pixel data loaded into the
shift registers during a RUM display cycle, however, are not
displayed since the blanking is high during this time. A RWM
display cycle, thus, will cause disruptions of the image and
should only be done during retrace periods.
Zoom Control
The 7220 GDC can zoom or magnify displayed images by
a factor of one to sixteen provided some external circuitry
is provided. To zoom an image, both the 7220 GDC zoom
register and hardware zoom register must be set to the same
value (see table 2a, and 2b). The zoom factors have the
23
effect of extending the display cycle timing by 2N 2xWCLK
clock cycles where N is the zoom factor (see figure 10). A
2x zoom, for example, reguires four 2xWCLK clock cycles for
one display cycle where as a 3x zoom requires six 2xWCLK
clock cycles for one display cycle. Each pixel is,
therefore, displayed for a longer period of time, and the
total displayed memory area is reduced. A 2x zoom, for
instance, will display each pixel twice as long and show
only a fourth of the display area.
Table 2a. Zoom command byte
ZOOM FACTOR 0 1 2 3
4 5 6 7 8 9 10 11 12 13
14 15
ZOOM NYBLE F E D C
B
A 9 8 7 6 5
4 3 2 1 0
24
Table 2b. Configure command byte
CONFIGURE NIBBLE FUNCTION
1 - B C
D
E F
INVALID
320H BY 240V NON-INTERLACED INVALID
640H BY 4B0V INTERLACED 640H BY 480V NON-INTERLACED
CONFIGURE NIBBLE ZOOM NIBBLE
BITS 7-4 BITS 3-0
Configure Control
The configure nibble of the zoom/config command port
allows three display modes (see table 2). These modes are
320H by 240V non-interlaced, 640H by 4B0V interlaced, and
640H by 480V non-interlaced. These configuration allows the
user the flexibility of image resolution to the cost of a
suitable monitor. In the non-interlaced mode, for example,
every vertical line is scanned sequentially, but at high
image densities slow monitors will not be able to paint the
entire image fast enough without noticeable image flicker.
Interlacing the image (displaying odd and even lines
alternately), however, will halve the effective vertical
resolution and thus reduce the cost of the monitor since
standard television timing can be used. A 74LS163 binary
counter (U19) as well as several registers within the 7220
GDC chip controls this timing.
Et
2xwclk
ale
adi5-ad0
ras-oen*
cas-genu
row-addr-sel
row/col a ddr
rah data out
vsr-lo
vsr-en
vo-blank
video out
_r
n
c VALID AD08ES3
X
EZ
"L
e3 e4 el
COLUHIV A0MCS5 DC
_TL
—L
D@C
n xx PIXCl. OAT4
Figure 10. 2X Zoom Factor Timing Diagram.
26
NON-S-lOO Bus Characteristics
The 7220 GDC and timing board conforms to all
1EEE-696 specifications except that the board only decodes
eight bits of the sixteen bit address space. Omission of
the extra address decoding was done (justified) because the
current system is not capable of using the higher order
address. The host processor board was designed before the
IEEE-696 bus standard. The prototype, however, could be
easily modified to meet the bus standard by adding an extra
address comparitor, dip switches, pull up resistors and some
minor wiring changes.
CHAPTER TWO
SLAVE PROCESSOR
The heart of the slave processor is an 8088
microprocessor made by INTEL Corporation. The 8088
microprocessor has four sixteen bit data registers for
manipulation of data in both eight, sixteen, and thirty-two
bit groupings. These registers include the accumulator, the
base register, the count register, and the data register or
AX, BX, CX, and DX in short form, respectively. The
processor, also, has several sixteen bit pointer and index
register consisting of a stack pointer register, a base
pointer register, a source index register, and a destination
index register or SP, BP, SI, and, DI respectively. In
addition, INTEL included several sixteen bit segmentation
registers to allow the processor access to more than 64K
bytes of RAH. This segmentation register group includes a
code segment register, a data segment register, a stack
segment register, and a extra segment register or CS, DS,
SS, and ES in short form, respectively. Thus, up to four
segments of 64K bytes can be accessed at any one time using
these segment registers. Internally the 6086 microprocessor
27
28
contains sixteen bit data paths and registers, but
externally the processor can only access eight bits of data
at a' time by a multiplexed data bus. This processor,
therefore, provides sixteen bit internal preformance as well
as data bus compatability with and existing eight bit
microprocessor system. The 8080 microprocessor can, in
addition, work with up to two coprocessors such as the 8089
input/output processor, and the 8088 math coprocessor. The
use of either coprocessor, however, requires a support chip,
the 8288 bus controller, to allow the 8088 to change modes
on several pins facilitating processor-coprocessor
interaction. Since, image generation and 'processing' can
reguire numerically intensive operations, the 8087 math
coprocessor was included in the design of the slave
processor prototype board. The 8087 coprocessor, however,
has not been installed into the board because, well, it
still costs to much - $1751
The 8087 math coprocessor, none the less, is an
amazing chip. The 8087 can, for instance, add, subtract,
multiply divide, load, store, perform a square root, and
scale thirty-two and sixty-four bit integers, 80 bits of
pack decimal, and thirty-two to eighty bit real numbers -
floating point. The 8087 can, also, execute transcendental
functions like E a X and can produce floating point constants
like pi. This coprocessor, more importantly, provides all
29
these features by extending the 8088 instruction set making
the 8087 transparent to the programmer and simplifying
program development of, in this case, pseudo real-time
graphics software.
As stated before, the purpose of the slave processor
is to simplify and speed up image generation and
manipulation. The host processor, on the other hand,
provides system software support through existing high level
languages, peripheral data gathering, and mass storage. The
slave processor board can, therefore, be programmed to
emmulate terminals, software drivers or execute applications
programs, from business to scientific, directly[5].
Ini tiallzatlon
Initialization for the slave processor board is
achieved through the use of the 8284 clock generator/driver
IC U19 (see figure 11). The 8284 has a Schmitt-trigger reset
input, RES*, which is used for power on reset, external
reset, and a software reset. First, when power is applied to
the board, the voltage at RES* is held below 1.05 volts for
50 microseconds by R1 and CI to insure that the 8284
generates a proper reset. Second, external clear, EXTCLR*,
from the S-100 bus may also cause a reset. When EXTCLR* goes
low (from pressing a front panel switch), the output of the
AND gate U36 goes low causing RES* to be held low for at
DRAWING NO.
LEfl 00
CLK
Utt HEADY
•«•• flCSCT
L PDY >
Figure 11. 8088 Slave Processor
DRAWING NO APPVO DATE ZONE OCH
I IOB
Ul
IM
M n
IIITJ Oft LAS
•< «£N
OC
Oft
Oft QI
04
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IfX KB
M 00
fU
*00
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PART NJMBER |
OWN
CHK
FIGURE ll> 6088 SLAVE PROCESSOR
dnAwmo Nuuau •RET 0*
[INITIAL UiE IHT OF
:e 11. 8088 Slave Processor
31
least 50 microseconds. Third, since newer microcomputers do
not provide front panels, a software reset is provided
through the use of control port one, U23. A software reset
is achieved by writing any byte into the control port with
the most significant bit set to one. A reset is
accomplished, for example, by sending say BOH to command
port one. Pin nineteen of the control port goes high (it was
initially low due to the power on reset). The resulting
rising edge on pin 19 causes pin one of a 74LS121 one shot
to go low for 50 microseconds. The resulting pulse causes
the output of AND gate U36 - RES* - to go low.
Shorty after a reset is generated at RES*, RESEST
from the 8284 goes high for as long as RES* is held low
causing control port one, and all FIFO registers to be
reset. RESET, also, causes the internal registers of the
8088 microprocessor to be set to specified values (see table
3), and cause the processor to begin execution of the first
instruction at address FFFFOH. RESET, however, is latched
into a 74LS74 flip flop U18 and is sent to the non-maskable
interrupt, NMI, input of the 8088. The 8088 ignores the NMX
while the RESET line is high. When RESET returns low the NMI
is held high for two additional clock cycles to insure that
the 8088 will acknowledge the interrupt. The 8088
acknowledge the NMI by loading the CS and instruction
pointer, IP, from the interrupt vector two located at 00008H
32
and OOOOBH ( four bytes). The 8088 microprocessor,
therefore, can be programmed to begin execution anywhere in
the address space since the above interrupt vectors are in
RAM and are set by the host processor before a software
reset.
Table 3. 8088 Microprocessor reset states
CPU CONTENTS
FLAGS CLEAR IP 0000H CS REGISTER FFFFH DS REGISTER 0000H SS REGISTER 0000H ES REGISTER 0000H QUEUE EMPTY
S-100 Bus Interface
The slave processor and the host processor
communicate through two sixteen word by eight bit first-in
first-out register memory ports. The 74LS224 FIFO registers,
and a 74LS273 eight bit latch allows, more specifically,
asynchronous communicaton of commands, and data between the
two processors as well as some control of the slave
processor. The host processor can obtain status or a
response from the slave processor by reading ports BASE+0 or
BASE+1 where BASE is set by the address decoding switches
(see table 4). These switches determine where in the I/O map
33
the ports are located so that the ports do not conflict with
other I/O devices. The host may, likewise, control or send
commands to the slave processor by writing to ports BASE+0
or BASE+1, respectively.
Table 4. Slave processor port assignments
PORT READ WRITE
BASE+0 RESPONSE COMMAND BASE+1 STATUS CONTROL
Host Command Port
To give the slave processor a command or data,
the host processor must execute an I/O instruction like OUT
30H where 30H is the port address (set by the switches) and
data to be set is in the accumulator (for a Z80
microprocessor). As a result, the following sequence occurs
on the S-100 bus. First, PSYNC goes high at the beginning
of bus cycle one, BS1 (see figures 12 and 13). With the
rising edge of PSYNC the address lines on the bus stabilize
and, in this case, SOUT goes high and SIN goes low. Second,
when SOUT goes high the 74LS689 eight bit comparator, U22,
is enabled. The address is then compared with the settings
of switch one and two, S W1 and S W 2 respectively.
If the switch settings and the current stable address are
the same board select, BDSEL*, goes low. Port select zero
and one, PBO* and PB1* , and the 7 4LS 244 tristate buffer are
enabled. The least
3 AZ 2 MICT y.
IH* >-M*
HAT -Xn_L
!W4 !W4 !W4
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LB224 DS OJH Dt Qth
«»r, DO OOP
cm on ift u »
UHCK LDCK OC
IU24 01 01 OC Ql M OJ 00 00 jfli? I
ZS Figure 12. Slave Processor I/O Interface.
AZ 2 DRAWING MO,
U» 3
>
llloN_L
*21-1
LOCK M 1*1*4
Oft Q l 01 01 01 M 00 00
£uf OR in ya>
UHC* uoe* ot
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PART NUMBER DESCRIPTION
DWN CHK E HOP. APVO TXi* OOOMT CO*JtiM p+ttrtmi HropiaiiM SMS^IUW aucaTSpu^iCo up « Mfp t* IMCO^^WATCB ^iSuer.vfmcvr p<« tppwM. ofJkr rc»u
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TITLE
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FIGURE 12, SLAVE PROCESSOR I/O INTERFACE DflAWINB NUMBER
SCALE' (iHITIAL
HE7
USE |SHTl OF 1
D
C
B
A
~zr Slave Processor I/O Interface,
35
HOST CLK
PSYNC
P5TVAL*
ADDRESS STATUS
SOUT
PWR*
DATA OUTPUT BUS
BDSEL*
HIOW-H
PBOW
HLDCLK
DATA BUS IN
PDBIN
SIN
HIOR*
HUNCK
FIFO DATA OUT
DATA BUS IN
BUFFERED DATA BUS IN
INPUT READY
OUTPUT READY
I BSI | BS2 I BS3 |
J~
valid address and status >
valid data
I
i/o write operation
J L valid data
J VALID V \ DATA r.
/ VALID r \ A PftTA../
_/ valid S-\ data r
1/0 read operation
Figure 13. Host FIFO I/O Timing Diagram.
36
significant bit of the address bus, ADO, will be zero
because OUT instruction referenced 30H as the address. This
action causes only PBO* (U33) to go low. Third, shortly
before the rising edge of the next clock cycle the data
becomes stable on the data out bus. Fourth, on the rising
edge of the next clock cycle, BS2, PWR* goes low for one
clock cycle. Fifth, PWR* is NORed with PBO creating host
load clock, HLDCK, and as a result of PWR* going low, HLDCK
goes high. When PWR* returns high at the end of bus cycle
BS2, the data on the bus is latched into the FIFO registers
U25 and U26. Last, the data becomes unstable some time in
the middle of the next clock cycle, BS3, and the address and
status lines also become unstable but at the end of BS3.
This result ends the command write operation.
Host Status Port
The host processor must read the status port,
ideally, before each byte is written to the command port to
prevent overflowing the FIFO register. The host processor
initiates a read status by executing an input instruction
like IN 31H. Again, the use of this instruction assumes that
the board is addressed at a base of 30H by the switches. The
following set of events, thus, occur on the S-100 bus (see
figure 13). First, PSYNC goes high for one clock cylce on
the rising edge of the first bus cycle, BS1. The address and
37
status lines become stable at this time SIN and AD1 high,
and SOUT low. Second, when SIN becomes active, the 74LS689
eight comparator, U22, is enabled. The comparator, then,
compares the seven address lines with the seven switch
settings. If address and switch settings are the same, board
select (BDSEL*) goes low enabling PBO*, PB1*, and the
74LS244 tristate buffer, U33 and U24 respectively. Third,
Address line zero, ADO, is high and is inverted by U34 to
create ADO* which is low. Since both ADO* and BDSEL* are
low, PB1* goes low instead of PBO*. Fourth, at the
beginning of the next clock cycle (BS2) , PDBIN goes high.
PDBIN is then inverted by U34 and ORed with PB1* (U32)
creating status port enable, SPE*. SPE* goes low just after
PDBIN goes high enabling two 74LS125 tristate buffers.
These buffers allow output ready and input ready status
lines of the FIFO registers onto the S-100 data bus DIO and
DI1 respectively. Fifth, PDBIN returns low in the middle of
the next bus cycle BS3 causing the status on the bus to be
latched into the host processor. SPE* also goes high. With
SPE* high, the tristate buffers, U30, tristate insuring that
bus collisions do not occur. Last, the address and status
lines become unstable at the end of BS3 ending the status
read operation.
38
Host Response Port
The host processor may read the response port by
i nitiating a n input instruction like IN 3 0H. This process
is similar to r eading the s tatus port except for the
following differences. First, since address bit zero, AB1,
is low P B O* goes low instead o f P B1*. Second, PDBIN is
inverted and b oth ORed and NORed to create signals host
unclock, HUNCK*, and host output enable, HOE, respectively.
Third, as a result of PDBIN going h igh, H OE goes high
enabling the outputs of the F IFO registers ( U 27 and U 28),
and H U N C K * goes low. Last, when PDBIN returns low, data from
the F IFO registers is latched into the h ost processor. H O E
returns low tristating the outputs of the FIFO registers
preventing b us conflicts. The rising edge of HUNCK*, on the
other hand, causes F IFO register to a dvance all bytes foward
o ne byte ( one nyble per c hip) by dropping the byte j ust
read. Thus, each n ew response byte becomes available at the
end o f the p revious read response operation.
Host Control Port
The host processor may control the s lave processor
by writing to t he control port. This operation is similar to
w riting the command port except for the following
differences. F irst, the host processor must execute a n
39
output instruction to port 3 1H instead of 3 0H, like O UT 31H.
Address bit o ne, ABl, becomes high instead o f ABO enabling
P B1*. PWR* and P B 1* are ORed together and inverted creating
control port enable, CPE. Second, when P WR* goes low, C PE
goes high causing the outputs of t he 74LS273 eight bit latch
( U 23) to f ollow the inputs, o r more specifically, to follow
the data o n the data bus. On the r ising edge of P WR*, CPE
returns low causing the outputs of the latch to hold the
data.
The command port only u ses three o f the eight b its
for commands ( see table 5 ) . First, bit 0 enables and
d isables the. s l a ve processors RAM space to and f rom a
portion of the host processors address spaces. Second, bits
o ne through f ive are unused. Third, bit six allows the host
processor to s t op the slave processor a t the end o f the
current instruction. This control bit, for example, allows
software debugging in that the host may inspect the slave
processors RAM space, determine state of application
program, m ake necessary modification, and continue
execution. L ast, bit seven allows the h ost to reset the
s lave processor (and software) to a known state.
40
Table 5 . Host control port bit functions
BIT SET(l) CLEAR(0)
7 RESET NORMAL 6 HALT RUN 5 -4 3 2 1 0 DISABLE SLAVE ENABLE S LAVE
NON-SIOO Bus Characteristics
T he slave processor described a bove does not meet
a ll IEEE 696 standards. T he specification, for example,
allows for 64K of I/O port address where a s the above
hardware implementation only decodes 256 I/O port a ddress.
T he full imp 1 itnen t a t i o n of the standard was not used f or two
r easons. First, the current host processor c an not generate
the upper eight I/O address bits for the s lave processor
board, to d e code. The ZBO microprocessor, more specifically,
only generates eight valid address lines during a n I/O
instruction. Second, the omission of the extra address
decoding circuitry reduced the chip count o n the prototype.
Slave S-100 Bus Interface
The slave processor receives and sends information to
the h ost processor through several I/O ports. This
communication process is very similar to t he o ne describe
41
above for the h ost processor. T he slave processor, however,
generates clock, read, and w r ite timing and strobes for this
communication which is different than the h ost processor
(especially since the two processors a re different). The
slave processor, then, can read commands or s tatus, or write
a response through two I/O port but h as no control of the
host processor control circuitry ( see table 6 ) .
Table 6 . Slave processor I/O port assignments
P ORT READ WRITE 0 Command Response 1 Status
Slave Status Port
T he slave processor obtains FIFO register status
information by executing a n input instruction like IN 01H
(this address is n o t switch selectable). T he following
sequence of events, thus, occurs. First, on the falling edge
o f the f irst ( s lave) clock cycle ( Tl), address latch enable,
ALE, goes high and the address lines AD0-AD7 and A 8-A15
become stable ( s ee figure 14). Second, the falling edge of
A L E causes the address to b e latched i nto two 7 4LS373
tristate latches ( U 3 and U 8 ) providing a 6 4 K address space
for both memory and I /O. Third, a 74LS138 three of eight
decoder, U6, continuously decodes the least significant
three bits of the address lines. Since the s lave processor
42
CLK
ALE
ADIS-8
AD7-0
IORK
PO*
SUNCK
FIFO DATA OUT
T| T2 I T3 I T4 I
_i—i n_
ADDRESS STABLE
X ADT-ADO > DATA IN y
DATA VALID
j
>
3C
r 10 READ
IOW*
SLDCK
AD7-0 "v valid Y" A addressA VALID DATA OUT X
10 WRITE
OR
IR
PI*
SSE*
J~
GOE
Figure 1 4 . Slave FIFO 1 /0 Timing Diagram.
A3
has executed a n IN 01H, the output P I * of the 7 ALS138 will
go low. Fourth, o n the following clock cycle, T 2, the
a ddress lines A D7-AD0 tristate and I/O read, IOR*, goes low.
Both P I * and I O R* are ORed together to c reate slave status
enable, SSE*. Consequently, SSE* goes l.ow a n d enables two
7 4 LS125 tristate buffers ( U 30). Fifth, at the falling edge
of the n e xt clock cycle ( T3), data is accepted into the
s lave processor from the F I FO register status bits via the
two tristate buffers. This data is not latched by t he
p rocessor until the rising edge of I OR*. Last, when I OR*
returns high, S SE* goes high disabling the two tristate
buffers ( U 30). The data bus A D7-AD0 tristates in the middle
of clock cycle T A, and the a ddress becomes unstable at the
end o f clock cycle T A. This ends the s lave status read
operation.
T h e status byte only contains two b its of u seful
information ( s ee table 7 ). First bit z ero indicates w hen a
command i s available for reading from the F IFO registers.
Second, bit o ne indicates when the F IFO registers are ready
to a c cept data ( a response). I n all cases, A z ero
represents n ot ready and a one represents read.
44
Table 7. Status Port Bit Functions
BIT HOST SLAVE
0
1
RESPONSE READY COMMAND READY
COMMAND READY RESPONSE READY
2 3
4 5
6 7
The slave processor must read the command port in
o rder to o btain commands from the host. The read command
o peration is the same as the ( a bove) read status operation
except in the following w ays. First, the slave processor
must access I/O port z ero instead o f port o ne. This read i s
accomplished by e xectuting a n IN 00H. Second, shortly after
the address is latched v ia ALE, P O * from the 74LS138 one of
three decoder will go low. Third, I OR* goes low at the
falling edge of the n ext clock cycle T 2 . Both P0»'» a n d I O R*
are ORed and NORed together to create slave unclock, SUNCK,
and slave output enable, SOE, respectively. S OE goes high
allowing the d ata within the F IFO register onto the s lave
processor data bus. Last, when I OR* returns high data is
latched into the slave processor, and S O E goes low
t ristating the outputs of the F IFO registers. T he rising
e dge of SUNCK, on the other hand, causes the F IFO registers
Slave Command P ort
45
to shift the n e xt bytes forward one position so that the
n ext command byte can be read on the next read command
operation. This ends the read command port operation.
S lave Processor Response
After the slave processor receives a command it may
w ish to respond to the command with data, program status, or
a n error condition depending o n the type of command
received. To respond, the s lave processor must write to p ort
O OH by executing the instruction O UT 00, AL. The following
events, thus, o ccur. First, ALE goes high and the a ddress
becomes stable at the falling edge of c lock cycle T l.
Second, the falling edge of A L E causes the address to b e
latched into two 7 4LS373 tristate octal latches ( U 3 and U 4).
The 74LS138 three of eight decoder decodes the latched
a ddress lines. As a result the output of the decoder, P0*,
goes low. Third, in the middle o f clock cycle T 2, IOW* ( U 5)
goes low. I OU* and P 0 * are ORed to c reate slave load c lock,
SLDCK. Fourth, the data from the slave processor h as been
stable o n the bus since clock cycle T 2. The data is latched
into the F IFO registers o n the falling edge of SLDCK which
occurs on the rising edge of IOW*. Last, the data becomes
unstable in t he middle of clock cycle T 4 ending the w rite
response operation.
46
Slave Processor Hemory Interface
The slave processor also has 8 K bytes of random
access memory and 1 6K bytes of erasable read only memory,
the EPROMS, for example, consist of four 2732 and a re 4K by
8 bytes where as the R AM consists of four 6116 and a r e 2K by
8 byte ( see figure 15). Each type o f memory, more
importantly, is placed i n the address space of the slave
processor ( and of the host processor) by address decoding
circuitry attached to the processor(s). T he RAM, for
example, resides from address X0000 to X2000 (X-don't care),
and the EPROM resides from address X2000 to X 5 FFFF. The RAM,
in particular, w ill be used f or software development and
used f or future application programs. T he EPROM, conversely,
w ill hold a FORTH kernel and graphic kernel to s i mplify
image generation. T he slave processor RAM is also connec ted
to t he S -100 bus to a l low the host processor access to this
R A M. The dual port ( m ail box RAM), therefore, allows easy
s oftware development and debugging.
Slave Memory Read
When the slave processor reads a byte from memory
( either RAM or E PROM) the following events occur ( see
figures 1 6 and 1 7). First, graphics enable, G EN*, from the
control port ( U 2 3) must be low. When G EN* is low t he S -100
47
X5000H
X4000H
X3000H
X2000H
XI800H
XIOOOH
XOSOOH
XOOOOH
EXTENDED
GRAPHICS
FUNCTIONS
EXTENDED
GRAPHICS
FUNCTIONS
GRAPHICS
KERNAL
FORTH
KERNAL
USER
RAM
USER
RAM
USER
RAM
USER
RAM
4K EPROM
4 K EPROM
4K EPROM
4K EPROM
2K RAM
2KRAM
2KRAM
2 K RAM
Figure 1 5 . Slave Processor Memory M ap.
DRAWING N O
IT9I 5E£W£
NIWfTO
HMID* > M l/Oi u ™ J2i "T At I/V9 T*-
w 1/01 T5" M u% »/M -T a u% ivw -4-
MP isvi -rr «l tj. I/Vt 4
wi4 TT MS#
Mi At
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JtSzEl
* 4 i LVI49 "
low* >
Mft >
F i g ure 1 6. Slave Processor Memory Interface.
X
REVISIONS ZONE PEV DcacnipnoN DC# DATE APPVO
DRAWING MO.
r »it>
ITO IV!
* ooj UJ4
01 0 1 0 » 0 4 09 04 0 /
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4
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l/f1 A4 l/OI Al l/OI A* l/OT AT l/OI AO At Ml
AIO
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l/OI l/OI l/DT
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= 3
ZS Lave P r ocessor Memory Interface.
PART NUMBER DESCRIPTION
OWN
CHK
EHOA
AFVD
J/\ yRESEARCH TITLE
T?
FIGURE 16, SLAVE PROCESSOR MEMORY INTERFACE DPAWIHS WJUUIH \~TTT
SCALE> INITIAL USE •HT OF
49
Tl T2 I T3 I T4
SLAVE CLK
ALE
AI5-A8
AD7-AD0
SMRD*
DT/R*
CHIP SELECT
AD7-AD0
SMWT*
RAM DATA OUT
RAM DATA IN
DT/R*
l
l^_n
r
x ADDRESS VALID
X VALID ADDRESS
"V VALID KT" 7\ ADORE 58 a-
c VALID
PATA IW
VALID DATA OUT
VALID DATA OUT
X >
X
X / VALID V \ qata r
Figure 1 7 . Slave Processor R A M Timing Diagram.
50
bus memory interface tristates and the slave processor
memory is removed from the host processor address space.
GEN* also permits the slave processor to a c cess its RAM by
e nabling a 74LS245 transceiver U 29. GEN*, therefore, only
allows one processor access to the RAM a t any one time, and
this signal is controlled only by the h ost. Second, a t the
falling edge of the f irst ( s lave) clock cycle ( T1), ALE goes
high, and the address lines A D7-AD0 and A8-A15 become
stable. Third, in the middle o f the first clock cycle, data
transmit/receive, DT/R*, goes low to t he data path direction
( r ead) to t he 74LS245 bus transceiver U29. The outputs of
the t ransceiver become active allowing RAM data into the
slave processor. Fourth, shortly after D T/R* returns low,
ALE goes low latching the valid address into two 7 4LS373
tristate latches U 3 and U 4. With G EN* low the latch address
is presented to t he R AMS or EPROMS. Latched address lines
A ll and A 12, o n the o ther hand, appear a t a 74LS139 dual o ne
of f our decoder U 7. Fifth, one of the outputs of the 74LS139
g oes low e nabling one of the f our RAM chips. The RAM chip
selected depends on the s tate of address lines All and A 12
( see table 8 ) .
51
Table 8 . Slave processor address decoding
All A12 ADDRESS CHIP SELECTED
0 0 0000-07FF 0 1 0800-0FFF 1 0 1000-17FF 1 1 1800-1FFF
Ul 2 U13 U14 Ul 5
To prevent the two processor from accessing the shared R AM
at the time, a n 74LS367 tristate buffer ( U 30) regulates when
the slave processor can select a RAM chip. At this time
G E N* is low and thus one of the outputs from the 74LS139
( U 7 ) is allowed to select o ne of the RAM chips according to
t h e a bove table. Sixth, at the falling edge of the n ext
clock cycle, T 2 , slave memory read, SMRD*, goes low.
Seventh, data within the selected RAM becomes stable on the
s lave processor data bus AD7-AD0, Eighth, S MRD* returns high
a t the rising edge of the n e xt clock cycle causing the data
to be latched i nto the slave processor. Last, the a ddress
lines become unstable in the middle o f the next clock cycle
( T 4) and chip select and D T/R* go high ending the read
memory operation.
52
Slave Memory Write
T h e slave processor may also write a byte to R A M.
This write operation is similar to a bove read operation
except for the following differences. First, after the
valid address has been latched and the particular RAM chip
has been selected, the data to b e written becomes s table on
the slave processor data bus. The 74LS245 tristate
transceiver ( U 29) is directed by DT/R-v t o a l low data to p ass
from the s lave processor to the R AM chip. Second, at the
falling edge of clock cycle T 4 data is latched into the
selected RAM chip. Last, the address becomes unstable in the
m iddle of clock cycle T 4 and chip select returns high ending
the write memory operation.
Host Processor RAM Interface
T he host processor may read and write to the s lave
processor R AM by f i rst writing a 40H and then a 41H to t he
c ontrol port. T he control byte 40H causes the slave
processor to s t op execution a t the end o f the current
instruction. T he second control byte disables the slave
processor address, data, and chip select from this shared
R A M. This two step process is used t o allow the slave
processor' t ime to finish the current instruction before the
h ost takes c ontrol of the RAM space. The control byte 4 1H,
53
more specifically causes bit zero to g o high ( see figure
1 8). It is G E N* in the h igh state that d isables the slave
processor from the R AM. GEN» is inverted to c reate host
enable, HOSTEN, which enables several tristate buffers.
These buffers allow the transfer of data between the host
processor and the RAMS, and the buffers connect the host
processor address lines to the RAMS.
Host Memory Read
Once the host processor has acquired a ccess to the
s lave processor R AM, the host may read data from the RAM by
e xecuting a memory read instruction which causes the
f ollowing events to o ccur ( see figure 1 9). First, at the
rising edge of first ( h ost) clock cycle ( BS1), PSYNC goes
high, and the address and status lines become stable, SMEMR
especially. T he address from the S-100 bus, A10-A0, are
presented to t he R AMS through two 7 4LS244 tristate buffers
V3 and V4. Address lines All and A 12 select a RAM chip to
r ead f rom by a 74LS138 one of four decoder ( V 5). One of the
f our outputs from the 74LS138 will go low depending on the
s tate of All and A 1 2 (see table 9 ) .
DRA
-m—-> «•*
•M
V4 (t/«l
•Wt
HAI> VIO
'liaa •n
OND
HAII HAII •QW IOA*
V*
IIOI
(l/tl
AJO
AO
HM
2 :— Figure 1 8. Host Memory Interface.
DRAV/ING NO REVISIONS RCV APPVD ZONE DESCRIPTION OCH
PI*
W
•AO
HAO
017
007
Odo
DESCRIPTION PART NUMBER
OWN
J/.\ ^RESEARCH
TITLE FIGURE 18, HOST MEMORY INTERFACE AC YD
TtEV DRAWINO NUMBER
iS«Tfi INITIAL USE «HT 4 OF <)
Host Memory Interface
HOST CLK
PSYNC
ADDRESS STATUS
SMEMR
PDBIN
DATA IN BUS
BSI I BS2 I BS3
j~
r VALID ADDRESS AND STATUS dct
J VALI6 V. A DATA r
DATA OUT BUS
MWRT*
RAMSEL
HMRD*
HMWT*
CHIP SELECTS
VALID DATA x
RAM DATA OUT
RAM DATA IN
VALID DATA x
CVALID V DATA r
Figure 1 9 . Host RAM Timing Diagram.
56
Table 9 . Host address selection
A 12 All ADDRESS CHIP SELECTED
0 0 1 1
0 1 0 1
0000-07FFH 0800-OFFFH 1000-17FFH 1800-1FFFH
U 1 2 U13 U14 U15
The remaining address lines A15-A13 from the S -100 bus
s elect the 8K boundary here the host c an access the s lave
processor R A M. Three exclusive OR gates ( 74LS136, V10)
compare the address lines A15-A13 with three switches ( see
table 1 0). When the switch settings and the a ddress lines
a re equal none of the 74LS136 XOR outputs g o low causing
RAMSEL to b e high. RAMSEL, thus, allows the read operation
to o ccur by e nabling the 74LS138 one o f four decoder ( V 5).
Table 10. Host-slave address selection
ADDRESS LINES SWITCHES START ADDRESS
A15 A 14 A13 SI S 2 S3 0 0 0 OFF OFF OFF 0 0 1 OFF OFF ON 0 1 0 OFF ON OFF 0 1 1 OFF ON ON 1 0 0 ON OFF OFF 1 0 1 ON OFF ON 1 1 0 ON ON OFF 1 1 1 ON ON ON
( H E X) 0000 2000 4000 6000 8000 A000 C000 E000
Second, PDBIN g oes high before the next clock cycle ( B S2)
and P SYNC returns low. RAMSEL, PSYNC, and SMEMR are ANDed
and inverted together to c reate host memory read, HMRD*.
57
HMRD* goes low on the rising edge of PDBIN and causes the
74LS244 tristate buffer V2 to become active on the S-100
input data bus DI7-DI0. The selected RAM also responds at
this time by putting data onto the bus. Third, some time
around the next clock cycle (BS3), PDBIN returns low causing
HMRD* to go high and latch the data into the host processor.
The 74LS244 tristate latch (V2) also tristates at this time.
Last, before the end of the next clock cycle (BS3), the
address and status lines become unstable. RAMSEL and SMEM
become inactive ending the host read.memory operation.
Host Memory Write
The host processor may also write to the slave
processor RAM. This write operation is the same as the read
operation except for the following differences. First, only
RAMSEL goes high after the address lines become stable.
SMEMR and PDBIN, in particular remain low. Second, MWRT goes
high at the beginning of clock cycle BS2 (see figure 19).
MWRT is then inverted to create HMWT* which goes low. A
74LS244 tristate buffer (VI) is enabled allowing data to
pass from the host processor to the RAMS. Third, MWRT»"f
r eturns low causing HMWT* to go high and latch the data into
the selected RAM. Last, at the end of clock cycle BS3, the
address, data, and status become unstable. RAMSEL, chip
select, and the tristate buffer, in turn, become inactive
58
ending the write memory operation.
NQN-S-100 Bus Characteristics
The S-100 bus standard (IEEE-696) states that no bus
line will drive more than one low power Schottky inputs per
board. The host processor RAM interface describe above,
however, puts a double input load on both the address lines
and the data input and output bus. This interface,
therefore, does not meet the standard. The omission of the
extra buffers greatly simplified the construction of the
prototype. The host-RAM interface is only for software
development and is not considered a normal function of the
slave processor.
CHAPTER THREE
SOFTWARE
Forth was first written by Charles Moore in 1969 at the
National Radio Astronomy Observatory in Charlottesville
Virginia for telescope control and astronomical data
reduction. In 1973, Charles Moore left NRAO to form his own
company - Forth Inc - which would sell an enhanced
commercial version of Forth for mimicomputers. Then in 1978
a group of Forth programmers (enthusiasts) formed the Forth
Interest Group (FIG) to promote the language Forth. FIG
began writing Forth for various microcomputers and a journal
called Forth Dimensions[6]. The August 1980 issue of Byte
magazine, the Forth issue, brought my attention to Forth and
to FIG[7]. Intrigued by the language, a copy of the Forth
implementation manual and an 8080 listing was ordered.
During the next summer, a month or so was spent implementing
Forth on a Z80 processor system. Once the FIG Forth became
operational, a new Forth enthusiast was created (like CREATE
JAY). Forth is not like basic, Pascal, Fortran nor is it
like assembly language. Forth is more of a cross between a
high and low level language. Forth is better described as
59
60
an interactive interpretive compiler because all compiled
high level words are lists of address pointing to other high
level words which, in turn, ultimately point to low level
assembly language Forth words. Forth, also, allows the
creation of assembly language words at any time for time
critical portions of applications. Forth, therefore, is
faster than basic and more compact than either Pascal or
Fortran compiled programs[8].
Forth was, then, chosen for this project for several
reasons. First, Dr. Dobb's Journal published an 8088 Forth
assembler by Ray Duncan[9]. Second, FIG provided (at
nominal cost) an 8088 Forth source listing which was written
by Thomas Newman[10][11]. This 8088 Forth, in particular,
executes the same high level Forth words as the 8080 Forth
which was currently running on my host system. Third, FIG
also provided a 8080 META-COMPILER written by John Cassady
for implementing a new version of Forth which will not run
on the host system but on a target system[12][13][14][15].
Fourth, the 8088 processor was acquired free of charge
through an INTEL promotion and this processor, more
importantly, was relatively easy to interface to the current
system. Fifth, Forth is very interactive and allows the
programmer complete control to define new high or low level
words and data structures. The programmer, more
specifically, has enough control to define experimental
61
image 'processing' languages and applications in an
interactive manner. Sixth, high level Forth words developed
on the host processor will also compile and run on the slave
processor with (ideally) no modifications. Last, with the
availabilivity of the 8088 Forth, assembler, and
META-Compi1er example at little cost, an 8088 Forth could be
written on a Z80 host microcomputer system. The 8088 Forth,
thus, can be compiled by the host, and transfered to the
8088 slave processor for testing and debugging without
spending hundreds of dollars on assemblers, operating
systems, cross-compilers, and many hours writing a dedicated
assembly language graphics software package.
Host Memory Configuration
The host can be considered somewhat unusual. First,
the North Star Disk Operating System (DOS) begins at memory
addres 2000H - the beginnig of the second 8K byte block of
memory (see figure 20). The DOS is only 2.5K bytes long and
is a very simple operating system. Second, user programs
like BASIC, the editor, the assembler, and of course Forth
must begin at memory address 2A00H. The basic 8080 Forth
kernal, in particular, is approximately 8K bytes long but
requires RAM for disk buffers add for several stacks. Forth,
thus, can be considered to reside from memory address 2A00H
to AFFFH. Third, there is no RAM at address B000H to BFFFH,
62
EOOOH
COOOK
AOOOH
8000H
6000H
4000H
2000H
USER RAM
zrzzzYzrz?. DISK I/O
OOOOH
(GP)
ADDRESS
SRACE
STACK
DISK BUFFERS
BO 80
FORTH
USER
AREA
8060 FORTH
KERNAL
—4 — DOS
6068
FORTH
DEVELOPMENT
AREA
Figure 20. Host Memory Map.
63
EOOOH to E6FFH, and EAOO to EFFFH. Fourth, vhen the host
processor has access to the slave processor RAM space, this
RAM resides at memory address COOOH to DFFFH (of the host).
Vhen the slave processor, in contrast, is given control of
the shared RAM, the above host address space from COOOH to
DFFFH contains no RAM. Fifth, a two hundred and fifty six
byte disk boot* PROM and memory mapped disk 1/0 begins at
memory address E900H. Seventh, the 4K bytes of RAM beginning
at F000H is used for the system monitor and various
utilities. Last, the 8K bytes of RAM residing at 0000H is
used to develop the 8088 Forth.
A Forth Application
During the course of prototyping the slave processor
it was necessary to determine if the I/O ports and memory
were functioning as expected. Some high level Forth words,
for instance, were written to read the status ports, to
write bytes to the command port, to reset the slave
processor and to write into the slave processor RAM (see
screen 88). several 8088 assembly language programs were
also written to test the 8088 processor, RAM, and the I/O
ports (see screen 89 and 90). To illustrate how Forth
works, then, consider some Forth words in screen 88. First,
BASE and HT.ADDR are constants which designate the base
address of the I/O ports of the slave processor and the base
Listing 1. Forth test screens
SCR 4 B6 0 ( GRAPHICS TEST ) 1 HEX 30 CONSTANT BASE COOO CONSTANT HT.ADDR 2 BASE 0 -I- CONSTANT PORTO BASE 1 + CONSTANT PORTl 3 HT.ADDR 6 + CONSTANT IP HT.ADDR A + CONSTANT CS 4 10 CONSTANT SL.ADDRO 00 CONSTANT SL.ADDR1 5 6 i 7OR BEGIN PORTl P@ 1 AND 7TERH1NAL OR UNTIL } 7 t 7IR BEGIN PORTl P@ 2 AND 7TERMINAL OR UNTIL j 8 9 : RESET 80 PORTl P! ; 10 i HALT 40 PORTl PI } : HOST HALT 41 PORTl P! ; 11 t READ 70R PORTO P@ ; t WRITE 7IR PORTO PI ; 12 13 t SET.NMI SL.ADDRO IP I SL.ADDR1 CS 1 ; 14 i GLOAD HOST HT.ADDR SL.ADDRO + SWAP CMOVE SET.NMI ; 15 ;S
SCR # 89 0 ( GRAPHICS PROCESSOR TEST - JPM 12 AUG 82 ) 1 CODE GTEST HERE 2 BEGIN 3 AL, 01 IN 4 AL, 4 1 TEST 5 0<> UNTIL 6 AL, 0 IN 7 AH, AL HOV 8 BEGIN 9 AL, 01 IN
10 AL, 4 2 TEST 11 0<> UNTIL 12 AL, AH HOV 13 0 , AL OUT 14 JMP 15 NXT (S
SCR 4 90 0 ( 8088 TEST PROGRAM 2 - 5 AUGUST 82 ) 1 CODE MGET 2 AX, 30 HOV 3 40 , AX MOV 4 HERE 5 JMP 6 NXT 7 8 9
10 11 12 13 14 15 ;S
65
address of the beginning of the shared RAM as seen by the
host processor, respectively. Constants PORTO and P0RT1
represent the port address of the command/response and
status/control ports of the slave processor and place 30H or
31H on the stack when executed, respectively. Third,
constants IP, and CS locate the address as seen by the host
processor 'of the Instruction pointer and Code segment
interrupt vectors so that these vectors can be set before
the slave processor receives a Non-maskable interrupt by the
word RESET. When the NMI occurs the values at address IP
and CS point to the start of the program. Fourth, SL.ADDRO
and SL.ADDR1 are, also, constants which are placed at
address IP and CS and place values 10H and 00H on the stack
when executed. Fifth, 70R (output ready) and 7IR (input
ready) are colon definitions. Colon definitions, more
specifically, define run time action words. Once a colon
definition, a Word, has been defined, it can be executed
from the keyboard or from within another Word. ?0R, for
example, sits in a loop via a BEGIN-UNTIL loop structure
I w aiting for bit one of the status port to be non-zero or
until a key is pressed oil t he keyboard or both. ?IR, in
contrast, has the same BEGIN-UNTIL loop structure but waits
for status port bit one to be one. These two words, thus,
make the host processor .wait until the command and response
ports are ready to write and read bytes. Sixth, reset,
66
halt, read, and write are also colon definitions which do
what the word implies to the slave processor. HOST, more
uniquely, halts the slave processor and gives the slave
processor access to the shared RAM. Seventh, SET.NMI sets
the address were the slave processor will begin execution
after a non-maskable interrupt (NMI). The phrase 'SL.ADDRO
IP for example, will place the value of SL.ADDRO (10H)
at host address IP (C008H) using ! (store). Eighth, when
GLOAD is executed with the proper address and lenght on the
stack, a previously assembled 8088 program can be moved from
the dictionary (in the host address space) to the slave
processor RAM space. GLOAD also uses the words described
above to set the execution address of the 8088 program just
loaded. Last, once the 8088 program is loaded (see screen
89) reset is executed which will cause the slave processor
to gain control of the RAM and to execute the newly loaded
program. Colon definitions READ and WRITE provide a means of
checking the execution program within the slave processor
board. When 01 WRITE is executed from the keyboard, WRITE
take a sixteen bit value off the stack, 01 in this case,
waits for the status to be ready, and writes the low byte to
the command port. Once the byte 01 progates through the
FIFO registers the slave processor will test the FIFO status
and read in the byte. The slave will test the status again,
wait until it is ready and write the same byte back out to
67
the response port. READ, then, will wait for the status on
the host side to be read and read the byte from the reponse
port. Two programs, therefore, are running concurrently.
READ and WRITE run on the host side and GTEST runs on the
slave side (see the flow cart in figure 21).
A Colon Definition
A Forth colon definition provides the programmer a
means of creating new words such as the words described
above. The Forth interpreter compiles these words into a
dictionary as a linked list of address. To understand this
process more clearly, consider ?0R described above in more
detail. First, tell Forth to defer execution unless
otherwise specified and to create a header in the dictionary
for ?0R (see figure 22). This header consists of a name
field (NFA), a link field (LFA) , and a code field (CFA). The
name field, for example, contains a length byte and the name
of the word (up to thirty-one characters). The link field
points to the name field of the previous word. This link
field provides a means of linking words together for
dictionary searches during word compilation. The code
field, on the other hand, contains an address which points
to the run time portion of 1s* called DOCOLON. Second, the
Forth interpreter searches the dictionary using the link
field address pointers for BEGIN. Since BEGIN has been
68
HOST SLAVE
READ HOST STATUS PORT
WRITE BYTE TO
CMD PORT
READ HOST
RESPONSE PORT
READ HOST
STATUS PORT
bit 1=0
READ SLAVE
STATUS PORT
WRITE SLAVE RESPONSE PORT
READ SLAVE CMD PORT
READ SLAVE STATUS PORT
Figure 21. Host-Slave Coprocessor Flowchart.
69
NFA LFA CFA PFA
E8 SL ADDR I
0000
NFA LFA CFA
NFA LFA CFA
NFA LFA CFA
83 ? OR NFA LFA CFA
NFA LFA CFA
—» PFA ADDRESS —» PFA —» PFA —» PFA —» PFA —» PFA —» PFA —» PFA
ADDRESS ADDRESS
_1
POINTER TO SL ADDR 0
POINTER TO D0D0E5)
POINTER TO NFA OF SL ADDR I POINTER TO DOCOLON POINTER TO PORT I POINTER TO P2 POINTER TO 2 POINTER TO AND POINTER TO ? TERMINAL POINTER TO OR POINTER TO 0BRANCH.
POINTER TO ;5
Figure 22. Memory Map of a Colon Definition.
70
defined before ?0R the search procedure succeeds. The code
field address of BEGIN, however, is not compiled into the
dictionary as is the usual case because BEGIN belongs to a
special class of Forth words. These words have precedence
which cause them to execute immediately. BEGIN and all words
in the same class have a precedence bit set which is within
the length byte within the name field. When BEGIN executes
it puts the address of the next available dictionary
location on the stack and an error handling byte. Third, the
Forth interpreter again searches the dictionary for P0RT1
and will find it. The interpreter then writes a two byte
address, the code field address, of P0RT1 into the next
available dictionary locations. Fourth, the CFA of 2 is
compiled into the next available dictionary locations just
after the CFA of P0RT1. 12 *, however, has been defined as
constant which speeds up compilation and saves dictionary
space especially for frequently used numbers. All words, in
particular, that are compiled into the dictionary for a new
word must already exist in the dictionary so that the
interpreter can find them. Forward word references, thus,
are not possible (but recurrsion is with special
techniques'). Fifth, the code field addresses of P@ (port
fetch), AND, 7TERMINAL, and OR are, likewise, compiled into
the dictionary. Sixth, UNTIL also has precedence and
executes immediately. UNTIL, for instance, removes the error
71
byte from stack and compiles OBRANCH into the dictionary
along with the address left on the stack by BEGIN. OBRANCH
and this address will cause the inner interpreter to branch
back to the first word within 70R (P@) for as long as the
value on the stack, the status of the FIFO register, is zero
when the word is executed. Last, again, has precedence
and executes immediately by checking for any leftover error
flags and compiles the CFA of ;S into the dictonary. ;S is
like a 'return' from subroutine in other languages because
it causes the inner interpreter to clean up the return stack
and to execute the next word. also ends compilation
mode.
Once defined ?0R can be executed from the keyboard by
typing it or by including it within another colon
definition. When 20R is executed from the keyboard, however,
the Forth interpreter searches the dictionary for ?0R. Once
70R has been found the interpreter executes the code pointed
to by the code field address of ?0R. In this case, the CFA
of ?0R contains a pointer to DOCOLON. When DOCOLON is
executed by the interpreter, the return stack and the Forth
instruction (word) pointer are set so the interpreter will
remember what word to execute next. DOCOLON i s , in effect,
functioning as an assembly language call instruction without
actually executing a call instruction. The word P0RT1, for
example, is 'called' first. P0RT1 executes by 'calling' the
72
run time portion of DOES> which is part of the definition of
a constant. Once P0RT1 has finished execution P<3 w ill
execute by 'calling' words within P@. (P@ is a low level
assembly language word.) Each word, in general, 'called'
contains other words which 'call' other words which...so on
and so forth until machine language primitives are
ultimately executed. When all words 'called* have completed
execution, the interpreter will then look at the keyboard
for more instructions.
In conclusion, Forth has some very unique features.
First, all Forth words are linked lists of address or linked
groups of machine code, and are part of a dictionary.
Second, all Forth words interact with each other through a
parameter stack. The return stack is usually used to keep
account of where to come back to. Third, Forth has three
modes of operation like 'run time', 'compile time', and
'definition time' (not discussed above). Fourth, once Forth
words are defined, they do not search the dictionary to
execute. Last, all words, once defined, can be tested and
debugged interactively[16][17][18] .
A Code Definition
A code definition is a Forth word which contains
machine language code as part of the word and is linked into
the dictionary in a way similar to a colon definition
73
described above. To illustrate how a code definition is
constructed, consider the word GTEST in screen 89. First,
CODE invokes the assembler and creates a header in the
dictionary. This header contains a name field, a link field,
and a code field just like the colon definition. The name
field, in contrast, contains a different length byte and
characters 'GTEST', and the code field address points to the
start of the machine code in the next successive dictionary
locations (see figure 23). Second, HERE executes
immediately by leaving the address of the next available
dictionary location on the stack which turns out to be the
start of the machine language code. Third, BEGIN also
executes immediately and leaves the same address on the
stack. Fourth, the next instruction, 'AL, 01 IN* is written
in Forth assembly language mnemonics. 'AL,', for instance,
sets several assembler variables to designate that the AL
8088 register is the destination. *01', on the other hand,
is a number which is placed on the stack. 'IN', then, comes
and looks at the assembler variables and takes 01 off the
stack to build the actual machine language code into the
dictionary, E4 01. Fifth, the words 'AL # 1 TEST' execute
ultimately creating F6 CO 01 (HEX) in the dictionary. 'AL,',
as before, sets the AL register as the destination but '#'
designates that TEST should be an immediate instrution where
'1' is the value to be used. Sixth, 0<> UNTIL places a 74H
74
NFA
LFA
CPA
PFA
85 GTEST
E4 01
F6 CO 01
74 F9
E4 00
E4 EO
E4 01
F6 CO 02
74 F9
BA CA
E6 00
E7 E9
73 POINTER TO 6L0AD
POINTER TO PFA
AL, 01 IN
AL,# 01 TEST
-7 JUMP
AL, 00 IN
AH, AL MOVE
AL, 01 IN
AL,#02 TEST
-7 JUMP
At- AH MOV
00, AL OUT
- 24 JUMP POINTER TO NEXT
Figure 23. Memory Map of a Code Definition.
75
into the dictionary along with the address on the stack that
was put there by BEGIN. The resulting instruction placed in
the dictionary is a jump relative if zero. Seventh, in a
similar manner, Forth words 'AL, 00 IN' puts bytes E4 00
into the dictionary. Eighth, 'AH, AL MOV 1 causes 8A E0 to be
placed in the dictionary next. 1AL 1 specifies the AL
register as the source, where as 'AH* defines the
destination of the move instruction. Ninth, BEGIN leaves the
address of the next dictionary location on the stack. Tenth,
forth words 'AL, 01 IN', 'AL, # 2 TEST*, and 0<> UNTIL cause
E4 01 F6 CO 02 74 F9 to be put into the dictionary by a
similar procedure used in the above instructions. Eleventh,
'AL, AH MOV',\'00 , AL OUT', and JMP are the last to execute
and place bytes 8A C4 E6 00 E9 E7 into the dictionary. The
OUT instruction is somewhat unique in that the comma sets 00
as the destination (port) and register AL as the source. The
jump instruction, on the other hand, gets its operand from
the stack which was originally placed on the stack by the
word HERE. Last, NEXT ends the code definition by placing a
jump to the inner interpreter and checks for errors
[15] [16][17][18] .
76
APPENDIX A
8088 FORTH ASSEMBLER
The 8088 Forth Assembler in listing 2 appeared in
the February 1982 issue of Dr. Dobb's Journal and was
written by Ray Duncan[8]. This assembler, however, has been
modified slightly to facilitate the compilation of the 8088
Forth. A more extended IF-ELSE-THEN, more specifically,
structure was added to the assembler. Readers will notices
from the previous example that all assembly language
instrustions are backwards. The instructions, in general,
take the form DESTINATION, SOURCE OP-CODE. The operands,
then, place values onto the stack or manipulate assembler
variables. When the op-code executes, it uses the variables
and the values on the stack to create the desired machine
language code. In addition, the 8087 instruction set has
not been added to this assembler.
Listing 2. 8086 Forth Assembler
SCR # 88 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 VOCABULARY ASH88 IMMEDIATE 2 ASM88 DEFINITIONS MEX 3 0 VARIABLE <#> 4 0 VARIABLE <TD> 5 0 VARIABLE <TS> 6 0 VARIABLE <RD> 7 0 VARIABLE A
£
V
8 0 VARIABLE
A
V
9 0 VARIABLE
A
s V
10 0 VARIABLE <0D> 11 0 VARIABLE <0S> 12 0 VARIABLE <D> 13 0 VARIABLE <SP> 14 15 —>
SCR # B9 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 ( CASE STATEMENT BY CHARLES EAKER ) 2 : CASE 7C0MP CSF @ ICSP 4 ; IMMEDIATE 3 4 I OF 4 7PAIRS COMPILE OVER COMPILE -5 COMPILE OBRANCH HERE 0 , 6 COMPILE DROP 5 } IMMEDIATE 7 8 t ENDOF 5 7PAIRS COMPILE BRANCH HERE 0 , 9 SWAP 2 [COMPILE1 ENDIF 4 } IMMEDIATE 10 11 t ENDCASE 4 7PAIRS COHPILE DROP 12 BEGIN SP@ CSP 0 - 0-13 WHILE 2 [COMPILE] ENDIF 14 REPEAT CSP 1 f IMMEDIATE 15 —>
SCR # 90 0 < 8088 ASSEMBLER DDJ FEB 82 ) 1 i *%
KSP> SPG <SP> I ;
3 t a
?<SP> <SP> G SP@ - 2 - 2 / ; h
5 3 a
ERROR 7" MESSAGE SP1 QUIT j 0 7 t 7ERROR SWAP IF ERROR ELSE DROP ENDIF 8 9 10 11 12 13 14 15 -->
Listing 2. 8068 Forth Assembler
SCR # 91 0 ( 8088 ASSEMBLER DDJ FEB 82 )
I <WD> I ENDIF
1 2 : DREG <BUILDS C, C, C, D0ES> 3 DUP C@ DUP OFF -4 IF DROP ELSE DUP <V> 5 1+ DUP C@ <TD> 1 6 1+ C@ <RD> 1 7 <#> @ 24 ?ERROR 8 <TD> @ 4 -9 IF ?<SP> 0 > IF <OD> 10 11 12 13 14 15 -->
I ENDIF EMDXF }
SCR # 92 0 ( 8088 ASSEHBLER DDJ FEB B2 ) 1 2 t SREG <BUILDS C, C, C, D0ES> 3 DUP C@ DUP OFF -4 IF DROP ELSE <W> ! ENDIF 5 1+ DUP C<3 <TS> 1 6 1+ C@ <RS> t 7 <TS> @ 4 » 8 IF 2<SP> 0 > IF <0S> ! ENDIF ENDIF ; 9 10 11 12 13 14 15 -->
SCR # 93 0 ( 80B8 ASSEHBLER DDJ FEB 82 ) 1 2 ( REG TYPE W NAME 3 4 0 2 0 SREG AL 5 1 2 0 SREG CL 6 2 2 0 SREG DL 7 3 2 0 SREG BL 8 4 2 0 SREG AH 9 5 2 0 SREG CH
10 6 2 0 SREG DH 11 7 2 0 SREG BH 12 13 14
Listing 2. 8068 Forth Assembler
SCR # 94 0 ( 8088 ASSEHBLER 1 2 ( REG TYPE U NAHE 3 4 0 3 1 SREG AX 5 1 3 1 SREG cx 6 2 3 1 SREG DX 7 3 3 1 SREG BX 8 4 3 1 SREG SP 9 5 3 1 SREG BP 10 6 3 1 SREG SI 11 7 3 1 SREG DX 12 13 14 15 -->
SCR # 95 0 ( 8088 ASSEHBLER 1 2 ( REG TYPE W NAHE 3 0 4 -1 SREG [BX+SI] 4 0 4 -1 SREG [S1+BXI 5 1 4 -1 SREG [BX+DI] 6 1 4 -1 SREG {DI+BX] 7 2 4 -1 SREG [BP+SI] 8 2 4 -1 SREG [SI+BP] 9 3 4 -1 SREG [BP+Dlj
10 3 4 -1 SREG [DI+BP] 11 4 4 -1 SREG [SIJ 12 5 4 -1 SREG IDIJ ' 13 6 4 -1 SREG IBP] 14 7 4 -1 SREG [BX]
SCR # 96 0 ( 8088 ASSEHBLER 1 2 ( REG TYPE V NAME 3 4 0 5 -1 SREG ES 5 1 5 -1 SREG cs 6 2 5 -1 SREG ss 7 3 5 -1 SREG DS 8 9 0 5 -1 DREG ES,
10 1 5 -1 DREG CS, 11 2 5 -1 DREG SS, 12 3 5 -1 DREG DS, 13 14 15 -->
DDJ FEB 82 )
)
DDJ FEB 82 )
)
DDJ FEB 82 )
)
Listing 2. 8088 Forth Assembler
SCR # 97 0 < 8088 ASSEHBLER 1 2 ( REG TYPE V HAHE 3 4 0 2 0 DREG AL, 5 1 2 0 DREG CL, 6 2 2 0 DREG DL, 7 3 2 0 DREG BL, 8 4 2 0 DREG AH, 9 5 2 0 DREG CH,
10 6 2 0 DREG DH, 11 7 2 0 DREG BH, 12 13 14 15 - • • >
SCR # 98 0 ( 8088 ASSEHBLER 1 2 ( REG TYPE W HAHE 3
4 0 3 1 DREG AX, 5 1 3 1 DREG CX, 6 2 3 1 DREG DX, 7 3 3 1 DREG BX, 8 4 3 1 DREG SP, 9 5 3 1 DREG BP, 10 6 3 1 DREG si, 11 7 3 1 DREG DI, 12 13 14 15 -->
SCR # 99 0 ( 8088 ASSEHBLER 1 2 ( REG TYPE V HAHE 3 0 4 -1 DREG [SX+SI] 4 0 4 -1 DREG [Sl+BX] 5 1 4 -1 DREG [BX+DI] 6 1 4 -1 DREG [Dl+BX] 7 2 4 -1 DREG [BP+SI] 8 2 4 -1 DREG [SI+BP] 9 3 4 -1 DREG [BP+DI] 10 3 4 -1 DREG [DI+BP] 11 4 4 -1 DREG [SI], 12 5 4 -1 DREG [DI], 13 6 4 -1 DREG [BP], 14 7 4 -1 DREG [BX], 15 ->
DDJ FEB 82 )
)
DDJ FEB 82 )
>
DDJ FEB 82 )
)
Listing 2. 8088 Forth Assembler
SCR # 100 •
0 ( 8088 ASSEMBLER DDJ FEB 82 ; 1 t ? W <W> @ ; 2 t ?TD <TD> @ ; 3 t 7TS <TS> <? ; 4 : 7RD <RD> @ ; 5 t 7RS <RS> @ ; 6 i 70D <0D> <? ; 7 t 70S <0S> @ ; B i + D <D> @ 2 * + | 9 t +V <W> @ + i
10 i +RD <RD> Q + ; 11 t +RS <RS> <a + ; 12 • • MODI 3F AND 40 OR j 13 : K0D2 3F AND 80 OR ; 14 : M0D3 3F AND CO OR j 15 -->
SCR # 101 0 < 8088 ASSEMBLER DDJ FEB 82 ) 1 0 CONSTANT DIRECT 3 CONSTANT REG16 2 1 CONSTANT 1MMED 4 CONSTANT INDEXED 3 A 2 CONSTANT REGS 5 CONSTANT SEGREG
H
5 : RESET 0 <#> ! 0 <W> I 0 <OS> 1 0 <RD> ! 6 0 <TD> I 0 <TS> ! 0 <0D> 1 1<SP> 7 O
0 <D> 1 0 <UD> I 0 <RS> ! ; O 9 • • DSET 7TS INDEXED - <D> ! » 1
1 0 11 i DT 1 <D> I } 12 13 14 15 -->
SCR # 102 0 1
< 8088 ASSEMBLER DDJ FEB A 2 •a : OFFSETS, HERE 1+ - DUP ABS 7F > 23 7ERROR C,
J 4 C : OFFSET16, HERE 2+ - , j
6 i DISP, <D> Q IF 70S ELSE 70D ENDIF DUP 7 IF DUP ABS 7F > 8 IF SUAP H0D2 c, , 9 ELSE SUAP MODI C, C, ENDIF 10 ELSE DROP DUP 7 AND 6 « 11 IF MODI C, 0 C, ELSE C, ENDIF 12 ENDIF ; 13 14 15 -->
Listing 2. 8088 Forth Assembler
SCR # 103 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 2 I 1MI <BUILDS C, D0ES> C@ C, RESET ; 3 4 : 2HX <BU1LDS C, D0ES> C@ C, OFFSETS, RESET ; 5 6 : 3HI <BUILDS C, D0ES> C@ +W C, RESET } 7 8 9 t +RD1 C@ H0D3 +RD C, ; 10 : +RS1 C@ +RS M0D3 C, ; 11 t ?W1 ?W IF , ELSE C, ENDIF } 12 13 14 15 —>
SCR # 104 0 ( 8088 ASSEMBLER DDJ FEB 82 ) X 2 s 4MI <BUILDS C, C, D0ES> 3 . 7TS CASE 4 REG16 OF 1+ C@ +RS C, ENDOF 5 SEGREG OF C@ 7RS 8 * + C, ENDOF 6 "1
28 ERROR ENDCASE RESET ; / 8 > SHI <BUILDS C, C, D0ES> 9 7TS CASE 10 DIRECT OF 14 C@ C, OFFSET16, ENDOF 11 REG16 OF OFF C, C@ H0D3 +RS C, ENDOF 12 INDEXED OF DSET OFF C, C@ +RS DISP, ENDOF 13 28 ERROR ENDCASE RESET ; 14 15 - • ->
SCR * 105 0 < 8088 ASSEMBLER DDJ FEB 82 ) 1 t 6MI <BUILDS C, C, D0ES> 2 DUF C@ 2 AND 3 IF 7TD 7TS ELSE 7TS 7TD ENDIF 4 REG16 - <U> 1 REG16 -5 IF 1+ C@ +W C, ELSE C@ +W C, C, ENDIF 6 RESET t f
8 i IND1 DSET C@ +RD DISP, ; 9 : 7RS1 7RS 8 * +RD M0D3 C, ;
10 i 7RS2 7RS 8 * +RD DISP, j 11 t 7RS3 C, 7RS 8 * 6 + C, , f 12 t 7RD1 7RD 8 * +RS DISP, ; 13 I 7RD2 7RD 8 * +RS MOD3 C, ; 14 • • 7RD3 C, 7RD 8 * 6 + C, , ; 15 --•>
Listing 2. 8086 Forth Assembler
SCR # 106 0 ( 8088 1 t 7MI 2 3 -
4 5 6 7 8 9 10 11 12 13 14 15 -->
SCR # 107 0 < 8088 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -->
SCR # 108 0 ( 8088 1 t 8MI 2 3 4 5 6 7 t 9HI 8 9 10 11 12 13 14 15 ~ >
ASSEMBLER DDJ FEB 82 ) <BUILDS C, C, C, D0ES> ITS IMHED -IF 1+ DUP 1+ C@ +V C, 7ID CASE REG8 OF +RD1 C, ENDOF REG16 OF +RD1 , ENDOF INDEXED OF 1ND1 7W1 ENDOF 28 ERROR ENDCASE
ELSE DSET C@ +D +W C, ?TD CASE REG8 OF 7TS CASE REG8 OF 7RS1 ENDOF INDEXED OF 7RD1 ENDOF 28 ERROR ENDCASE ENDOF
ASSEMBLER DDJ FEB 82 )
REG16 OF 7TS CASE REG16 OF 7RSI ENDOF INDEXED OF 7RD1 ENDOF 28 ERROR ENDCASE ENDOF
INDEXED OF 7TS CASE REG8 OF 7RS2 ENDOF RE616 OF 7RS2 ENDOF 28 ERROR ENDCASE ENDOF
28 ERROR ENDCASE ENDIF RESET f
ASSEMBLER DDJ FEB 82 ) <BUILDS C, C, DOES> DUP 1+ C@ +V C, 7TS CASE REGS OF +RS1 ENDOF REG16 OF +RS1 ENDOF INDEXED OF DSET C@ +RS DISP, ENDOF 28 ERROR ENDCASE RESET ; <BUILDS C, C, DOES> DUP 1+ C@ <WD> @ + 7TS 1 > IF 2 + ENDIF C, 7TD CASE REGS OF +RD1 ENDOF REG16 OF +RD1 ENDOF INDEXED OF IND1 ENDOF 28 ERROR ENDCASE 7TS 2 < IF DROP ENDIF RESET ;
84
Listing 2. 8086 Forth Assembler
SCR # 109 0 1
< 8088 ASSEMBLER DDJ FEB 82 )
2 t 10MI <BUILDS C, C, D0ES> 3 A
DUP C@ SWAP 1+ C@ C, C, RESET ( H
5 : 11MI <BUXLDS C, C, D0ES> 6 ITS CASE 7 REG8 OF OFE C, 1+ C@ M0D3 +RS C, ENDOF 8 REG16 OF C@ +RS C, ENDOF 9 INDEXED OF DSET OFE +VC. 1+ C@ +RS DISP, ENDOF 10 28 ERROR 11 ENDCASE RESET ; 12
ENDCASE RESET ;
13 14 15 — •>
SCR # 110 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 : 12MI <BUILDS DOES> 2 DROP DSET 7TD CASE 3 DIRECT OF ?TS CASE 4 REGS OF 7RS IF 88 7RS3 ELSE A2 +W C, , ENDIF 5 ENDOF 6 RE616 OF 7RS IF 89 7RS3 ELSE A2 +W C, , ENDIF 7 ENDOF 8 SEGREG OF 8C 7RS3 ENDOF 9 28 ERROR ENDCASE ENDOF
10 REG8 OF 7TS CASE 11 DIRECT OF 7RD IF 8A 7RD3 ELSE 8A +V C, , ENDIF 12 ENDOF 13 IMMED OF BO +RD C, C, ENDOF 14 REG8 OF DT 88 +D C, 7RD2 ENDOF 15 -->
SCR # 111 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 REG16 OF 2D ERROR ENDOF 2 INDEXED OF 88 +D +W C, 7RD1 ENDOF 3 28 ERROR ENDCASE ENDOF 4 REG16 OF 7TS CASE 5 DIRECT OF 7RD IF 8B 7RD3 ELSE AO +V C, , ENDIF 6 ENDOF 7 IMMED OF B8 +RD C, , ENDOF 8 REG16 OF DT 88 +W +D C, 7RD2 ENDOF 9 INDEXED OF 88 +D +W C, 7RD1 ENDOF 10 SEGREG OF 8C C, 7RS1 ENDOF 11 28 ERROR ENDCASE ENDOF 12 13 14 15 -->
85
Listing 2. 8088 Forth Assembler
SCR # 112 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 INDEXED OF ITS CASE 2 IHHED OF C6 +V C, 7RD DISP, 7VI ENDOF 3 REGS OF 88 +D +W C, 7RS2 ENDOF ' 4 REG16 OF 88 +D +W C, 7RS2 ENDOF 5 SEGREG OF 8C C, 7RS2 ENDOF 6 28 ERROR ENDCASE ENDOF 7 SEGREG OF 7TS CASE 8 DIRECT OF 8E 7RD3 ENDOF 9 REG16 OF 8E C, 7RD2 ENDOF 10 INDEXED OF 8E C, 7RD1 ENDOF 11 28 ERROR ENDCASE ENDOF 12 28 ERROR ENDCASE RESET ; 13 14 15 —>
SCR # 113 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 2 : 13HI <BUILDS DOES> 3 DROP DSET 7TD CASE 4 DIRECT OF I T S REG16 -5 IF 90 +RS C, ELSE 28 ERROR ENDIF ENDOF 6 REG8 OF 86 +V C, 7TS CASE 7 REGB OF 7RD2 ENDOF 8 INDEXED OF 7RD1 ENDOF 9 28 ERROR ENDCASE ENDOF 10 REG16 OF 86 +W C, 7TS CASE 11 REG16 OF 7RD2 ENDOF 12 INDEXED OF 7RD1 ENDOF 13 "28 ERROR ENDCASE ENDOF 14 .28 ERROR ENDCASE RESET ; 15 -->
SCR # 114 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 t 14MI <BUILDS DOES> DROP 7TS CASE 2 DIRECT OF 28 ERROR ENDOF 3 IMMED OF OF6 +V C, 7TD CASE 4 REGS OF 7RD MOD3 C, 7U1 ENDOF 5 REG16 OF 7RD H0D3 C, 7U1 ENDOF 6 INDEXED OF 7RD DISP, 7V1 ENDOF 7 28 ERROR ENDCASE ENDOF 8 SEGREG OF 28 ERROR ENDOF 9 7TD REGS < 7TD REG16 > OR 28 7ERROR 10 84 +W C, 7RD 8 * +RS 7TS INDEXED < 11 IF MOD3 C, ELSE DISP, ENDIF 12 ENDCASE RESET } 13 14 15 —>
Listing 2. 8088 Forth Assembler
SCR #115 0 ( 8088 ASSEHBLER DDJ FEB 82 ) 1 37 1MX AAA 80 38 38 7MI CMP 2 D5 OA 10MI AAD A6 3MI CMPS 3 D4 OA 10HI AAM 99 1HI CWD 4 3F 1MI AAS 27 1HZ DAA 5 80 10 10 7MI ADC 2F 1MI DAS 6 80 00 00 7HI ADD 08 48 11MI DEC 7 80 20 20 7H1 AND F6 30 SMI D1V 8 E8 10 SMI CALL ( ESC ) 9 98 1HI CBU F4 1MI HLT 10 F8 1HI CLC F6 38 8MI IDIV 11 FC lhl CLD F6 28 8M1 1MUL 12 FA 1MI CLZ EC E4 6MI IN 13 F5 1HI CMC 00 40 11MI INC 14
SCR # 116 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 < INT ) E9 20 5MI JMP 2 CE 1MI INTO 76 2MI JNA 3 CF 1MI IRET 72 2MI JNAE 4 77 2MX JA 73 2HI JNB 5 73 2MI JAE 77 2MI JNBE 6 72 2MX JB 75 2MI JNE 7 76 2MI JBE 7E 2MI JNG 8 E3 2MI JCXZ 7C 2MI JNGE 9 74 2MI JB 7D 2MI JNL 10 7F 2MI JG 7F 2MI JNLE 11 7D 2MI J6E 71 2MI JNO 12 7C 2MI JL 7B 2MI JNP 13 7E 2MI JLE 79 2MI JUS 14 15 -->
SCR # 117 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 75 2MI JNZ E2 2HI LOOP 2 70 2MI JO El 2MI LOOPE 3 7A 2MI JP EO 2MI LOOPNE 4 7A 2MI JPE EO 2MI LOOPNZ 5 7B 2MI JPO El 2MI LOOPZ 6 78 2MI JS 12MX MOV 7 74 2MI JZ A4 3MI MOVS 8 9F 1MI LAHF F6 20 SMI MUL 9 ( LDS ) F6 18 8MI NEC 10 8A 8A 8A 7MI LEA 90 1HI NOP 11 ( LES ) F6 10 SMI NOT 12 FO 1MI LOCK 80 08 08 7MX OR 13 AC 3MI LODS EE E6 6KX OUT 14
Listing 2. 8088 Forth Assembler
SCR # 118 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 58 07 4MI POP DO 08 9M1 ROR 2 9D 1MX POPF 9E 1M1 SAMF 3 50 06 4MI PUSH DO 38 9MI SAR 4 9C 1MI PUSHF 80 18 18 7M1 SBB 5 DO 10 9MI RCL AE 3MI SCAS 6 DO 18 9MZ RCR ( SEG ) 7 F3 1H1 REP DO 20 9MX SAL 8 F3 1MI REPE DO 20 9MI SHL 9 F2 1HI REPNE DO 28 9HI SHR 10 F2 1MI REPMZ F9 1MI STC 11 F3 1MX REPZ FD 1MI STD 12 C3 1MI RET FB 1MI STI 13 DO 00 9MI ROL AA SMI STOS 14
SCR # 119 0 ( 8088 ASSEMBLER 1 80 28 28 7HI SUB 2 14MI TEST 3 9B 1M1 WAIT 4 13M1 XCHG 5 D7 1MI XLAT 6 80 30 30 7MI XOR 7 8 9 10 11 12 13 14 15 -->
SCR # 120 0 ( 8088 ASSEMBLER - DDJ FEB 82 1 I IF 0 C, HERE RESET ; 2 t ELSE EB C, 0 C, DOP 3 0 C, HERE SWAP - DUP ABS 4 SWAP 1 - CI HERE RESET t 5 : ENDIF DUP HERE SWAP - DUP ABS 6 SWAP 1 - C! RESET | 7 8 t BEGIN HERE RESET ; 9 i UNTIL HERE 1+ -10 DUP ABS 7F > 23 7ERROR C 11 12 13 14 15 -->
DDJ FEB 82 )
> 23 ?ERROR
Listing 2. 8088 Forth Assembler
SCR # 121 0 ( 8088 ASSEMBLER - DDJ FEB 82 1 : BYTE 0 <W> I 0 <WD> 1 J 2 t WORD 1 <W> t 1 <Vn» I ; 3 t # 1 <#> I 1 <TS> 1 ; 4 5 i DB C, J 6 i DM 7 8 t DEPTH SO <? SP@ - 2 - 2 / } 9 i , DEPTH 1 < 2E 7ERROR 0 <TD> 1 f 10 11 12 13 14 15 -->
SCR # 122 0 ( 8068 ASSEMBLER EXTENTION - 29 OCT 83 JPM 1 ( CHDITIOHALS FOR IF [TRDE] ELSE [FALSE] ENDIF 2 ( SIGHED 3 t 0- 75 ( JNE.JNZ ) c, ( EQ ) 4 i 0<> 74 ( JZ,JE ) c, < NE ) 5 t > 7E < JliE|JNG ) C, ( GT ) 6 t < 7D ( JGE,JNL ) C, ( I»T ) 7 : -> 7C { JL.JNGE ) c, ; < GE ) 8 i <- 7F { JG,JNLE ) C, ; ( LE ) 9 ( UNSIGNED 10 i 0> 76 ( JBE,JNA ) c, ( GT ) 11 i 0< 73 { JAE,JNB ) c, < LT > 12 i 0-> 72 ( JB,JNAE ) c, ( GE ) 13 t 0<- 77 < JA.JNBE ) c, ( LE ) 14
SCR # 123 0 ( 8088 ASSEMBLER - EXTENSIONS 1 t NOV ( JNO ) 71 C, ; 2 : OV < JO > 70 C, ; 3 > PO ( JNP,JPO ) 7B C, ; 4 i PE ( JPE.JP ) 7A C, | 5 i NSS ( JNS ) 79 C, i 6 j SS ( JS ) 78 Cf ; 7 > 00 ( JMP ) EB C, | 8 9 ( SEGMENT RESITER OVER RIDES - 17 FEB 84 ) 10 26 1MI ESOV 11 2E 1MI CSOV 12 36 1MI SSOV 13 3E 1MI DSOV 14 15 -->
Listing 2. 8088 Forth Assembler
SCR 4 124 0 ( 8088 ASSEMBLER DDJ FEB 82 ) 1 2 : NXT RESET 7EXEC 7CSP SMUDGE [COMPILE] FORTH ; IMMEDIATE 3 4 5 FORTH DEFINITIONS 6 7 t JCODE 7CSP COMPILE ({CODE) [COMPILE] [ 8 ASM88 RESET FORTH [COMPILE] ASM88 ; IMHEDIATE 9 10 t CODE 7EXEC ICSP CREATE ASM88 RESET FORTH 11 [COMPILE] ASH88 ; IMMEDIATE 12 13 ASM88 LOADED " CR 14 DECIMAL *
15 }S •
SCR # 125 0 1 -
2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCR # 126 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
90
APPENDIX B
FORTH METACOMPILER
The meta-compiler was written by John Cassady for
the 8080 FIG-Forth and has been modified to meta-compi1e the
8088 FIG-Forth[l2][13][14][15] . This meta-compi1er,
basicaly, keeps track of two vocabularies, NEWFORTH and
0LDF0RTH. The 8088 target Forth, thus, is compiled into the
NEWFORTH vocabulary where as all label references and
meta-compiler supervisory words are compiled into OLDFORTH.
Once the 8088 Forth has been loaded, words like BYTE:IN and
REPLACED:BY resolve all forward label reference which
OLDFORTH can not handle directly.
Listing 3. Forth Metacompiler
SCR # 68 0 ( META1 COMPILER - JJC 17JAN81 X HEX 2 0100 CONSTANT BASE-ADDR 3 BASE-ADDR CONSTANT COHPILE-ADDR 4 0000 CONSTANT DELTA 5 BASE-ADDR 1EFF + CONSTANT EM 6 0040 CONSTANT US 7 00A0 CONSTANT RTS 8 0000 CONSTANT CO 9 10 11 12 13 14 15 -->
SCR # 89 0 ( HETA1 COMPILER - JJC 17JAN81 1 FORTH DEFINITIONS 2 00 CONSTANT *(.")* 3 00 CONSTANT *DOES>* 4 00 CONSTANT *<;CODE)* 5 00 CONSTANT *VARIABLE* 6 7 ' LIT CFA DUP CONSTANT *LIT* 8 CONSTANT OF*LIT* 9 00 CONSTANT NF*LIT* 10 11 12 13 14 15 -->
00 CONSTANT *USER* 00 CONSTANT *COLON* 00 CONSTANT *CONSTANT* 00 CONSTANT *VOCAB*
SCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
# 90 ( META1 COMPILER - JJC 05DEC80 VOCABULARY NEWFORTH IMMEDIATE l OF/NF [COMPILE] NEWFORTH DEFINITIONS [COMPILE] FORTH f 00 VARIABLE DPOLD BASE-ADDR VARIABLE DPNEW 00 VARIABLE O/N I SETOLD
t SETNEU
LAST ->
( SWITCH TO OLD DICTIONARY ) O/N @ IF 0 O/N 1 HERE DPNEW ! DPOLD @ DP 1 0F*LIT* [ 1 *LIT* ] LITERAL ! ENDIF
( — SWITCH TO NEW DICTIONARY O/N @ 0- IF 1 O/N 1 HERE DPOLD DPNEW 0 DP t NF*LIT* [ • *LIT*
CURRENT @ ;
> 1 ] LITERAL ! ENDIF
Listing 3. Forth Metacompiler
SCR # 91 0 ( META1 COMPILER - JJC 04JUNB0 1 00 VARIABLE <XMHED> 40 ALLOT <IMMED> 2+ <IMMED> 1 2 3 I /SMUDGE <IMMED> @ <IMMED> 2+ DO I @ 20 TOGGLE 2 +LOOP ; 4 t NFFIND BL WORD HERE [ * NEWFORTH 4 + ] LITERAL Q (FIND) j 5 6 i *NF /SMUDGE NFFIND DUP 7 IF SWAP DROP ENDIF /SMUDGE 0-8 IF HERE COUNT TYPE SPACE NF7" HOOP ( QUIT ) ENDIF ; 9 10 t REPLACED:BY 'HF CFA SWAP 1 ; 11 I BYTEiIN 'HF + ; 12 t 1FROM:HEWFORTH] 'HF CFA , ; IMMEDIATE 13 14 15 -->
SCR # 92 0 ( META1 COMPILER - JJC 05DEC80 1 : CREATE-NEW SETNEW 2 BL WORD HERE DUP C@ WIDTH @ M1H l-l- ALLOT 3 DUP 80 TOGGLE HERE 1-80 TOGGLE 4 . [COMPILE] NEWFORTH DEFINITIONS 5 LATEST , CURRENT 0 ! J 6 7 I HFs ICSP SETOLD [COMPILE] NEWFORTH DEFINITIONS 8 CREATE -2 ALLOT [ 1 QUIT CFA Q ] LITERAL t
9 [COMPILE] FORTH LATEST 40 TOGGLE ] ; 10 11 : NF; ?CSP COMPILE ;S SMUDGE 12 [COMPILE] [ ; IMMEDIATE 13 14 15 -->
SCR # 93 0 ( META1 COMPILE - JJC 05DEC80 1 ! LITERAL STATE <3 IF *LIT* , , ENDIF ; IMMEDIATE 2 3 1 DLITERAL STATE @ IF SWAP [COMPILE] LITERAL 4 [COMPILE] LITERAL ENDIF ; IMMEDIATE 5 6 t IMMEDIATE LATEST <IMMED> @ ! 2 <XMMED> +1 SMUDGE IMMEDIATE 1 6 I INTERPRET BEGIN -FIND 9 IF ( FOUND ) STATE <? < 10 IF CFA , ELSE CFA EXECUTE ENDIF 11 ELSE HERE NUMBER DPL @ 1+ 12 IF [COMPILE] DLITERAL ELSE DROP [COMPILE] 13 LITERAL ENDIF 14 ENDIF AGAIN ; 15 —>
Listing 3. Forth Metacompiler
SCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
# 94 ( HETA1 COMPILER - JJC 05DEC80 : QUIT
t NLOAD
i LOADS
I EQUATE
i LABEL
t 95
0 BLK ! [COMPILE] [ BEGIN-RPI CR QUERY INTERPRET STATE Q 0-IF NK" ENDIF AGAIN ;
BLK @ >R IN @ >R 0 IN ! B/SCR * BLK ! INTERPRET R> IN I R> BLK 1 } OVER + SWAP DO I LOAD LOOP j
7EXEC SETOLD CURRENT @ >R [COMPILE] ASM88 DEFINITIONS CONSTANT R> CURRENT ! t
SETOLD DPNEW <3 EQUATE SETNEW }
7EXEC !CSP CREATE-NEW SHUDGE HERE 2+ , [COMPILE] ASMS8 ; 7EXEC 7CSP SMUDGE [COMPILE] FORTH ;
SCR 0 ( META1 COMPILER - JJC 05DEC80 1 i CODE 2 3 t C; 4 5 I CONSTANT 6 7 i VARIABLE 8 9 : USER 10 11 12 t VOCABULARY 13 14 15 —>
CREATE-NEW •CONSTANT* CREATE-NEW •VARIABLE* CREATE-NEW *USER* , ,
, [COMPILE] FORTH
, [COMPILE] FORTH
[COHPILE] FORTH ;
CREATE-NEW *DOES>* , *VOCAB* , A081 , LATEST , 0 , [COMPILE] FORTH ;
SCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
# 96 ( 8088 FORTH AND META1 COHPILER IN1TIZATI0N
! : 7EXEC tCSP CREATE-NEW SHUDGE *COLON* , ] ;
NFt OF/NF [COMPILE] NEWFORTH DEFINITIONS [COMPILE] FORTH NF}
' QUIT CFA * *NF 24 + I ' 0 'NF OF/NF LFA !
DECIMAL QUIT
;s
94
APPENDIX C
8088 FORTH
The 8088 Forth was written by Thomas Newman and is
distributed by the Forth Interest Group[10][11] . FORTH88 in
listing 4, however, has been modified to work in the slave
processor. The disk buffers, for example, have been removed
and special I/O routines were incorporated. Several
initialization routines for the NEC 7220 GDC have also been
added as well as some graphics routines.
Listing 4. 8088 Forth
SCR # 97 0 < 80SB FORTH - SETUP 1 HEX 2 NF: X BLK @ 3 IF 1 BLK +1 0 IN 1 BLK @ B/SCR 1 - AND 0-4 IF 7EXEC R> DROP ENDIF 5 ELSE R> DROP ENDIF NF; 6 80C1 'NF X NFA ] 7 80C1 'NF NF:
8 NF: 9 NF: 10 NF: 11 NF: 12 13 14 NF: 15 -->
( GAP LITERAL [COHPILE] (CODE
[COHPILE] 0 , NF} [COMPILE] [COHPILE] *( (CODE)*
( NFj
LITERAL NF; [FROH:NEUFORTH] NF; , HERE DELTA - -2 CSP +1
ASH88 RESET FORTH [COHPILE] ASH88 [COMPILE] [ NF; *(.")* . 22 WORD HERE CO 1+ ALLOT NF;
SCR t 98 0 ( 8086 FORTH - BLANK SCREEN ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 —>
SCR # 99 0 ( 8088 FORTH - BLANK SCREEN ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -->
Listing 4. 8086 Forth
SCR # 100 0 ( 8088 1 FORTH - START 1 LABEL ORG KOP HERE JHP 2 NOP HERE JMP 3 0000 DU 4 0000 DU 5 0000 DU 6 0008 DU 7 EM CO - US - DU 8 EM CO - US - RTS - DU 9 EM CO - us - DU 10 EH CO - us - RTS - DU 11 0020 DU 12 0000 DU 13 0000 DU 14 0000 DU 15 0000 DU
SCR # 101 0 ( 8088 FORTH - USEP, RETP 1 2 LABEL UP EM CO - US - DW 3 LABEL RSP EM CO - US - DU 4 5 6 7 8 9 10 11 12 13 14 15 -->
SCR # 102 0 ( 8088 FORTH - BLANK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
97
Listing 4. 8088 Forth
SCR # 103 0 ( 8088 FORTH - BLANK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 —>
SCR # 104 0 ( 8088 FORTH - NEXT 1 LABEL DPUSH DX PUSH 2 LABEL APUSH AX PUSH 3 LABEL NEXT AX LODS 4 BX, AX HOV 5 LABEL NEXT1 DX, BX HOV 6 DX INC 7 8 9 10 11 WORD [BX] JMP 12 13 14 15 -->
SCR # 105 0 ( 8088 FORTH - DICTIONARY STARTS HERE - LIT ) 1 CODE LIT AX LODS 2 APUSH JMP 3 NXT 4 'NF LIT CFA ' NF*LIT* I 5 CODE EXECUTE BX POP 6 NEXT1 JMP 7 NXT 8 9 CODE BRANCH 10 LABEL BRANl SI, [SI] ADD 11 NEXT JMP 12 NXT 13 14 15 -->
Listing 4. 8088 Forth
SCR # 106 0 { 80B8 FORTH 1 CODE OBRANCH 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -->
- OBRANCH POP AX
AX, AX OR BRAN1 JZ SI SI NEXT NXT
INC INC JMP
SCR # 107 0 < 80B8 FORTH 1 CODE (LOOP) 2 LABEL XLOOl 3 4 5 6 7 8 9 10 11 12 13 14 15 ~ >
[LOOP] BX, # 1 HOV [BP], BX ADD AX, [BP] HOV AX, 2 [BP] SUB AX, BX XOR BRAN1 ' JS BP, # 4 ADD SI INC SI INC NEXT JMP NXT
SCR # 108 0 ( 8088 FORTH 1 CODE (-(-LOOP) 2 3 4 CODE (DO) 5 6 7 8 9 10 11 12 CODE I 13 14 15 -->
[+LOOP] BX XLOOl NXT DX AX BP, SP AX DX BP, SP NEXT NXT AX, [BP] APUSH NXT
POP JMP
POP POP XCHG PUSH PUSH XCHG JMP
MOV JMP
99
Listing 4. 8088 Forth
SCR # 109 0 ( 8088 FORTH - DIGIT 1 CODE DIGIT 2 DX POP AX POP AL, # 30 SUB 3 0-> IF AL, # 9 CMP 4 0> IF AL, # 7 SUB AL, # OA CMP 5 0-> IF SWAP ENDIF AL, DL CMP 6 0< IF DX, DX SUB DL, AL HOV 7 AL, # 1 MOV DPUSH JMP 8 ENDIF 9 ENDIF 10 ENDIF 11 AX, AX SUB APUSH JMP NXT 12 13 14 — > 15
SCR # 110 0 ( 8088 FORTH - PF1ND 1 CODE (FIND) AX, DS MOV ES, AX MOV BX POP CX POP 2 BEGIN DI, CX MOV AL, [BX] MOV DL, AL MOV 3 AL, [DI] XOR AL, * 3F AND 4 0- IF BEGIN BX INC DI INC AL, [BX] MOV 5 AL, [DI] XOR AL, AL ADD 6 0- IF SWAP 7 0< UNTIL 8 BX, 4 5 ADD BX PUSH AX, # 1 MOV DH, DH SUB 9 DPUSH JMP 10 ENDIF 11 ENDIF BEGIN BX INC 12 0-> IF AL, [BX] HOV AL, AL ADD SWAP 13 00 UNTIL 14 ENDIF BX, [BX] MOV BX, BX OR 15 0- UNTIL AX, # 0 HOV APUSH JMP NXT —>
SCR # 111 0 ( 8088 FORTH - BLANK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -->
Listing 4. 8088 Forth
SCR # 112 0 < 8088 FORTH - EHCLOSE 1 CODE EHCLOSE AX POP BX POP BX PUSH AH, # 0 HOV 2 DX, # -1 HOV BX DEC 3 BEGIH BX INC DX INC AL, [BX] CMP 4 0<> UNTIL DX PUSH AH, [BX] CHP 5 0- IF AX, DX HOV DX INC DPUSH JHP ENDIF 6 BEGIN BX INC DX INC AL, [BX] CHP 7 0<> IF AH, [BX] CHP SWAP 8 0- UNTIL 9 AX, DX HOV DPUSH JHP 10 ENDIF 11 AX, DX HOV AX INC DPUSH JHP NXT 12 13 14 15 —>
SCR # 113 0 ( 8086 FORTH - BLANK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -->
SCR # 114 0 ( 8088 FORTH -1 CODE KEY 2 CODE 7TERMINAL 3 CODE CR 4 CODE EMIT 5 CODE CMOVE
EMIT HERE JHP NXT HERE JHP NXT HERE JHP NXT HERE JHP NXT
CLD 6 BX, SI HOV 7 CX POP 8 DI POP 9 SI POP 10 - AX, DS HOV 11 ES, AX HOV 12 REP AL, AL HOVS 13 SI, BX MOV 14 NEXT JHP 15 NXT -->
101
Listing 4. 8088 Forth
SCR # 115 0 ( 8088 FORTH - U* 1 CODE U* AX POP 2 BX POP 3 „ BX HUL 4 AX, DX XCHG 5 DPUSH JHP 6 CODE U/ BX POP 7 DX POP 8 AX POP 9 DX, BX CMP 10 0< IF BX DIV 11 AX, # -1 MOV 12 DX, AX HOV. 13 DPUSH JHP 14 NXT
NXT
DPUSH JHP EHDIF
15 -->
SCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
# 116 ( 8088 FORTH - AND CODE AND AX
BX AX, BX APDSH
CODE OR AX BX AX, BX APUSH
POP POP AND JHP NXT
POP POP OR JHP NXT
-->
SCR # 117 0 ( 8088 FORTH - XOR 1 CODE XOR AX POP 2 BX POP 3 AX, BX XOR 4 A&USH JHP 5 NXT 6 7 CODE SP@ AX, SP HOV 8 APDSH JHP 9 NXT 10 11 CODE SPI CSOV BX, IIP HOV 12 SP, 6 [BX] NOV 13 NEXT JHP 14 NXT 15 -->
Listing 4. 808B Forth
SCR # 118 0 < 8088 FORTH - RP@ 1 CODE RP@ AX, BP HOV 2 APUSH JHP 3 NXT 4 5 CODE RPI CSOV BX, UP MOV 6 BP, 8 [BX] MOV 7 NEXT JHP 8 NXT 9 10 CODE ;S SI, [BP] MOV 11 BP INC 12 BP INC 13 NEXT JHP 14 NXT 15 —>
SCR # 119 0 ( 8088 FORTH - LEAVE 1 CODE LEAVE AX, [BP] HOV 2 2 [BP], AX HOV 3 NEXT JMP 4 NXT 5 CODE >R BX POP 6 BP DEC 7 BP DEC 8 [BP], BX MOV 9 NEXT JHP 10 NXT 11 CODE R> AX, [BP] MOV 12 BP INC 13 BP INC 14 APUSH JMP 15 NXT
SCR # 120 0 ( 8088 FORTH - R 1 CODE R AX, [BP] MOV APUSH JMP NXT 2 3 4 5 CODE 0- AX POP 6 AX, AX OR 7 AX, # 1 MOV 8 0<> IF AX DEC I 9 APUSH JMP NXT 10 11 12 13 14 15 -->
Listing 4. 8088 Forth
# 121 ( 8088 FORTH - 0< CODE 0<
SCR 0 1 2 3 4 5 6 7 8 9 CODE + 10 11 12 13 14 15 -->
AX POP AX, AX OR AX, # 1 MOV SS IF AX DEC ENDIF APUSH JHP HXT
AX BX AX, BX APUSH
POP POP ADD JHP NXT
SCR # 122 0 ( 8086 FORTH - D+ 1 CODE D+ AX POP 2 DX POP 3 BX POP 4 CX POP 5 DX, CX ADD 6 AX, BX ADC 7 DPUSH JHP 8 NXT 9 10 CODE MINUS AX POP 11 AX NEG 12 APUSH JHP 13 NXT 14
SCR # 123 0 ( 8088 FORTH - DHINUS 1 CODE DHINUS BX POP 2 CX POP 3 AX, AX SUB 4 DX, AX HOV 5 DX, CX SUB 6 AX, BX SBB 7 DPUSH JHP 8 NXT 9 10 CODE OVER DX POP 11 AX POP 12 AX PUSH 13 DPUSH JHP 14 NXT 15 --> .
Listing 4. BOSS Forth
SCR # 124 0 ( 8088 FORTH - DROP 1 CODE DROP AX POP 2 NEXT JMP 3 NXT 4 5 CODE SWAP DX POP 6 AX POP 7 DPUSH JMP 8 NXT 9 10 CODE DUP AX POP 11 AX PUSH 12 APUSH JMP 13 NXT 14
SCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
4 125 ( 8088 FORTH CODE 2DUP
CODE +1
- 2DUP AX DX DX AX DPtJSH
POP POP PUSH PUSH JMP NXT
BX POP AX POP [BX], AX ADD NEXT JMP
NXT
-->
SCR t 126 0 ( 8088 FORTH - TOGGLE 1 CODE TOGGLE AX pop 2 BX POP 3 [BX], AL XOR 4 NEXT JMP 5 NXT 6 7 CODE @ BX POP 8 AX, [BX] MOV 9 APUSH JMP
10 NXT 11 CODE C@ BX POP 12 AL, [BX] MOV 13 AH, AH SUB 14 APUSH JMP NXT 15 - ->
Listing 4. 8088 Forth
SCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
# 127 ( 8068 FORTH - 20 CODE 20 ' BX
AX, DX, DPUSH
CODE t
POP [BX] MOV 2 [BX] MOV
JMP NXT
BX AX [BX], AX NEXT
POP POP MOV JMP NXT
- - >
SCR # 128 0 ( 6088 FORTH - CI 1 CODE Ct BX • POP 2 AX POP 3 [BX], AL MOV 4 NEXT JMP 5 NXT 6 7 CODE 2! BX POP 8 AX POP 9 [BX], AX HOV 10 AX POP 11 2 [BX] , AX HOV 12 NEXT JMP 13 NXT 14
SCR # 129 0 ( 8088 FORTH - META1 COMPILER STUFF 1 NF: ; ?CSP COMPILE [FROHtNEWFORTH] ;S 2 SMUDGE [COMPILE] FORTH [COMPILE] [ NF; 3 NFs ENDIF HERE OVER - SWAP I NF; 4 NFi BEGIN HERE NF; 5 NF: DO COMPILE [FROMiNEWFORTH] (DO) HERE NF; 6 NF: LOOP • COMPILE [FROM:NEWFORTH1 (LOOP) HERE - , NF; 7 NF: +LOOP COMPILE [FROMiNEWFORTH] (+LOOP) HERE - , NF 8 NF: UNTIL COMPILE [FROM:NEWFORTH] OBRANCH HERE - , NF; 9 NF: AGAIN COHPILE [FROMiNEWFORTH] BRANCH HERE - , NF; 10 NF: REPEAT SWAP COMPILE [FROHtNEWFORTH] BRANCH HERE -11 HERE OVER - SWAP I NF; 12 NF: IF ~ COMPILE [FROM:NEWFORTH] OBRANCH HERE 0 , NF; 13 NF: ELSE COMPILE [FROHtNEWFORTH] BRANCH HERE 0 , 14 SWAP HERE OVER - SWAP I NF; 15 NF: WHILE COMPILE [FROHtNEWFORTH] OBRANCH HERE 0 , NF
Listing.4. 808B Forth
SCR #130 0 ( 8086 FiORTH - COLON 1 t I GAP GAP GAP ( 7EXEC ICSP CURRENT ) 2 <3 GAP ( CONTEXT ) 1 3 GAP GAP ( CREATE ] ) ;CODE IMMEDIATE 4 DX INC 5 BP DEC 6 BP DEC 7 [BP], SI HOV 8 SI, DX HOV 9 NEXT JHP 10 NXT 11 ' *COLON* I 12 13 « ; GAP GAP ( 7CSP COMPILE ) ;S 14 GAP GAP ( SMUDGE I ) ; IMMEDIATE 15 -->
SCR # 131 0 ( 80BB FORTH - HOOP 1 t NOOP { 2 t COHSTANT GAP GAP GAP { CREATE SHUSGE , ) ;CODE 3 DX INC 4 BX, DX HOV 5 AX, [BX] HOV 6 APUSH JHP 7 NXT 8 ' *C0NSTANT* ! 9 : VARIABLE CONSTANT jCODE 10 DX INC 11 DX PUSH 12 NEXT JHP 13 NXT 14 1 *VARIABLE* 1 15 — >
SCR # 132 0 ( 8088 FORTH - USER 1 t USER CONSTANT (CODE 2 DX INC 3 BX, DX HOV 4 BL, [BX] HOV 5 BH, BH SUB 6 CSOV DI, UP HOV 7 AX, [BX+DI] LEA 8 APUSH JHP 9 NXT 10 * *USER* t 11 0 CONSTANT 0 01 CONSTANT 1 02 CONSTANT 2 12 20 COHSTANT BL 40 CONSTANT C/L 13 ASH88 EH CO - CONSTANT FIRST 14 ASM88 EH CONSTANT LIMIT 15 -->
Libting 4. 8088 Forth
SCR # 133 0 ( 8088 FORTH - USER VARIABLES 1 s +0RIGIN GAP GAP ( LIT 'ORIG* ) + ; 2 06 USER SO 3 08 USER RO 4 OA USER TIB 5 OC USER WIDTH 6 OE USER WARMING 7 10 USER FENCE 8 12 USER DP 9 14 USER VOC-LINK 16 USER BLK 10 18 USER XN 11 1A USER OUT 12 20 USER CONTEXT 13 22 USER CURRENT 14 24 USER STATE 15 —>
SCR # 134 0 < 8088 FORTH • BASE
" 1 26 USER BASE 2 2A USER FLD 3 2E USER R# 4 5 l 1+ 1 + } 6 : HERE DP @ } 7 I , HERE t 2 ALLOT | 8 9 CODE - DX POP 10 AX FOP 11 AX, DX SUB 12 APUSH JHP 13 NXT 14 15 - ->
28 USER DPL 2C USER CSP 30 USER HLD
t 2+ 2 + j 1 ALLOT DP +! ; i C, HERE CI 1 ALLOT
SCR # 135 0 ( 8088 FORTH - < 1 i • • 0" | 2 CODE < DX POP 3 AX POP 4 BX, DX MOV 5 BX, AX XOR 6 SS IF AX, DX SUB ENDIF 7 AX, AX OR 8 AX, t 0 HOV 9 NSS IF AX INC ENDIF 10 APUSH JHP NXT 11 12 t U< 2DUP XOR 0< IF DROP 0< 0- ELSE - 0< ENDIF J
13 : > SWAP < ; 14 15 -->
Listing 4. 8088-Forth
SCR # 136 0 ( 8088 FORTH - ROT 1 CODE ROT DX POP 2 BX POP 3 AX POP 4 BX PUSH 5 DPUSH JMP 6 MXT 7 : SPACE BL EMIT j 8 J -DUP DUP IF DUP ENDIF ; 9 1 TRAVERSE SWAP BEGIN OVER + 7F OVER C@ < mtTIL SWAP DROP 10 I LATEST CURRENT Q @ ; 11 i LFA 4 - ; : CFA 2 - j t NFA 5 - -1 TRAVERSE t 12 : PFA 1 TRAVERSE 5 + ; 13 t 1CSP SPG CSP ! $ 14 I 7ERROR SWAP IF GAP ( ERROR ) ELSE DROP ENDIF ; 15 —>
SCR # 137 0 ( 8088 FORTH - 7C0MP 1 t 7C0MP STATE @ 0- 11 ?ERROR } 2 : 7EXEC STATE @ 12 7ERROR ; 3 t 7PAIRS - 13 7ERROR { 4 : 7 CSP SP@ CSP <3 - 14 7ERROR ; 5 J COMPILE 7C0HP R> DUP 2+ >R 0 , } 6 : [ 0 STATE ! ; IMMEDIATE 7 :] CO STATE 1 j 8 : SMUDGE LATEST 20 TOGGLE ; 9 I HEX 10 BASE ! ; 10 t DECIMAL OA BASE I } 11 i (;CODE) R> LATEST PFA CFA 1 * 12 'NF (;CODE) CFA ' *{}CODE)* 1 13 : {CODE 7CSP COMPILE (;CODE> [COMPILE] [ SMUDGE 14 NOOP ( ASSEMBLER ) ; IMMEDIATE 15 -->
SCR # 138 . 0 ( B088 FORTH - <BUILDS 1 i <BUILDS 0 CONSTANT ; 2 t DOES> R> LATEST PFA t {CODE 3 BP, SP XCHG 4 SI PUSH 5 BP, SP XCHG 6 DX INC 7 BX, DX MOV 8 SI, [BX] MOV 9 DX INC 10 DX INC 11 DX PUSH 12 NEXT JMP 13 NXT 14 * *DOES>* 1 15 —>
Listing 4. 8068 Fortta
SCR #139 0 ( 8068 FORTH - COUNT ) 1 t COUNT BOP 1+ SWAP C@ ; 2 i TYPE -DUP IF OVER + SWAP DO I C@ EMIT LOOP 3 ELSE DROP ENDIF ; 4 s -TRIALING DUP 0 DO OVER OVER + 1 - C@ BL -5 IF LEAVE ELSE 1 - ENDIF LOOP ; 6 t (.") R COUNT DUP 1+ R> + >R TYPE } 7 *NF (.") CFA ' *(.")* 1 8 t 22 STATE 0 IF COMPILE (.") CAP ( WORD ) HERE C@ 1+ ALLOT 9 ELSE GAP ( WORD ) HERE COUNT TYPE ENDIF ; IMMEDIATE 10 t EXPECT OVER + OVER 11 DO KEY DUP OE +ORIGIN @ -12 IF DROP DUP I - DUP R> 2 - + >R 13 IF GAP GAP ( LIT PNOT ) ELSE GAP GAP ( LIT PBS ) 14 ENDIF ELSE DUP OD - IF LEAVE DROP BL 0 ELSE DUP 15 ENDIF I C! 0 I 1+ 1 ENDIF EMIT LOOP DROP ; —>
SCR # 140 0 < 8088 FORTH - QUERY ) 1 t QUERY TIB @ 50 EXPECT 0 IN I ; 2 i X ( 3 4
. 5 6 CODE FILL AX POP 7 CX POP 8 DI POP 9 BX, DS MOV 10 ES, BX MOV 11 CLD 12 REP AL STOS 13 NEXT JMP 14 NXT
SCR t 141 0 ( 8088 FORTH - BLANK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -->
Listing 4. 80B6 Forth
SCR # 142 0 ( 8086 FORTH - BLANK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 —>
SCR # 143 0 ( 8088 FORTH - BLANK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -->
SCR # 144 0 ( 8088 FORTH - BLANK 1 2 3 4 5 6 7 8 9 10 11 .12 13 14
Ill
Listing 4. 8088 Forth
SCR # 145 0 ( 80B8 FORTH - ERASE ) 1 : ERASE 0 FILL ; 2 t BLANKS BL FILL ; 3 i HOLD -1 HLD +1 HLD @ CI j 4 t PAD HERE 44 + ; 5 t WORD TIB @ IK @ + SWAP ENCLOSE HERE 22 BLANKS IN +! 6 OVER - >R R HERE CI + HERE 1+ R> CHOVE J 7 > (NUMBER) BEGIN 1+ DUP >R C@ BASE @ DIGIT 8 WHILE SWAP BASE @ U* DROP ROT BASE Q U* D+ 3 DPL Q 1+ IF 1 DPL +1 ENDIF R>
10 REPEAT R> f 11 : NUMBER 0 0 ROT DUP 1+ C@ 2D - DUP >R + -1
. 12 BEGIN DPL t (NUMBER) DUP C@ BL -13 WHILE DUP C@ 2E - 0 7ERROR 0 14 REPEAT DROP R> IF DMINUS ENDIF j 15 —>
SCR # 146 0 ( 8088 FORTH - -FIND ) 1 t -FIND BL WORD HERE CONTEXT <a @ (FIND) 2 DUP 0- IF DROP HERE LATEST (FIND) ENDIF ; 3 t (ABORT) GAP ( ABORT ) ; 4 : ERROR WARNING @ 0< 5 IF (ABORT) ENDIF HERE COUNT TYPE 7 ,r
6 GAP ( MESSAGE ) SP1 BLK @ -DUP 7 IF IN @ SWAP ENDIF GAP ( QUIT ) } -2 ALLOT 8 t ID. PAD 20 5F FILL DUP PFA LFA OVER -9 PAD SWAP CMOVE PAD COUNT IF AND TYPE SPACE J
10 i CREATE -FIND IF DROP NFA ID. 4 GAP ( MESSAGE ) SPACE ENDIF 11 HERE DUP C@ WIDTH @ GAP ( MIN ) 1+ ALLOT 12 DUP AO TOGGLE HERE 1-80 TOGGLE 13 LATEST , CURRENT 0 1 HERE 2+ , ; 14 15 —>
SCR # 147 0 ( 8088 FORTH - [COMPILE] ) 1 t [COMPILE] -FIND 0- 0 7ERROR DROP CFA , J IMMEDIATE 2 t LITERAL STATE @ IF COMPILE LIT , ENDIF ; IMMEDIATE 3 t DL1TERAL STATE @ IF SWAP [COMPILE] LITERAL 4 [COHPILE] LITERAL ENDIF f IMMEDIATE 5 t 7STACK SP@ SO @ SWAP U< 1 7ERROR SP@ 6 HERE 80 + U< 7 7ERROR ; 7 : INTERPRET BEGIN -FIND IF ( FOUND ) STATE @ < 8 IF CFA , ELSE CFA EXECUTE ENDIF 7STACK 9 ELSE HERE NUMBER DPL Q 1+
10 IF [COMPILE] DLITERAL ELSE DROP [COHPILE] 11 LITERAL ENDIF 7STACK 12 ENDIF AGAIN ; -2 ALLOT 13 14 15 —>
Listing 4. 6088 Forth
SCR # 14B 0 ( 8088 FORTH - IMMEDIATE 1 t IMMEDIATE LATEST 40 TOGGLE ; 2 t VOCABULARY <BUILDS A081 , CURRENT 6 CFA , 3 HERE VOC-LINK 6 , 4 VOC-LINK 1 DOES> 2+ CONTEXT ! ; 5 HERE 8 - DELTA - ' *VOCAB* t 6 VOCABULARY FORTH IMMEDIATE 7 : DEFINITIONS CONTEXT @ CURRENT 1 ; 8 j < 29 WORD ; IMMEDIATE 9 : QUIT 0 BUC I [COMPILE] [ BEGIN RP! CR QUERY INTERPRET
10 STATE @ 0- IF OK" ENDIF AGAIN ; -2 ALLOT 11 12 t ABORT SP! DECIMAL 7STACK CR 13 FIG-FORTH GDC VI.1" [COMPILE] FORTH 14 DEFINITIONS QUIT } -2 ALLOT 15 -->
SCR # 149 0 ( 8088 FORT H - WARM 1 LABEL VRM1 0 DW 2 LABEL WRM . SI, # VRM1 MOV 3 t WARM ABORT t -2 ALLOT 4 5 LABEL CLD1 0 DW 6 LABEL CLDO SI, # CLD1 MOV 7 AX, CS HOV 8 DS, AX MOV 9 CSOV SP, WORD 12 ORG + MOV
10 SS, AX HOV 11 ES, AX HOV 12 CLD 13 CSOV BP, RPP HOV 14 NEXT JHP 15 - ->
SCR # 150 0 ( 8088 FORTH • COLD 1 t COLD GAP GAP GAP GAP ( LIT ORIG 12+ LIT UP ) 2 @ 6 + 1 0 C M O V E G A P G A P ( L I T O R I G 0 C + ) @ 3 GAP GAP ( LIT FORTH 6+ ) I ABORT ; -2 ALLOT 4 5 CODE SOD DX POP 6 AX, AX SUB 7 DX, DX OR 8 NSS IF AX DEC ENDIF 9 DPUSH JHP NXT 10 11 12 13 14 15 -->
Listing 8086 Forth
SCR # 0 ( 1 2 3 4 5 6 7 8 9 10 11 12 13 14
151 8088 FORTH - +-+- 0< IF HINUS ENDIF } D+- 0< IF. DHINUS ENDIF ; ABS DUP +- i DABS DDP IH- { HIN 2DUP > IF SWAP ENDIF DROP f MAX 2DUP < IF SWAP ENDIF DROP ; H* 2DUP XOR >R ABS SWAP ABS U* R> D+ M/ OVER >R >R DABS R ABS D/ R> R XOR
+- SWAP R> +- SWAP ; * M* DROP } /MOD >R SOD R> H/ » / /HOD SWAP DROP j HOD /HOD DROP ; */MOD >R H* R> H/ }
15 —>
SCR # 152 0 ( 8088 FORTH - */
t */ */H0D SWAP DROP } I H/HOD >R 0 R U/ R> SWAP >R U/ R> ;
HSG # " HOOP ( . > J DX POP AL, DX IN AH, AH SUB APUSH JMP
NXT DX POP AX POP DX, AL OUT NEXT JMP
NXT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -->
HESSAGE CODE P@
CODE P!
SCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
# 153 ( 8088 FORTH - P@ CODE 2P@
CODE 2P1
DX AX, DX APUSH
DX AX DX, AX NEXT
POP IN JMP NXT POP POP OUT JMP NXT
-->
Listing 4. 8088 Forth
SCR # 154 0 < 8088 FORTH - BLANK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -->
SCR # 155 0 ( 8088 FORTH - BLANK 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 -->
SCR # 156 0 < 8088 FORTH - CUSTOM I/O ROUTINES 1 LABEL (7TERMINAL) AL, 01 IN 2 AX, # 01 AND 3 AFUSH JHP 4 5 LABEL (KEY) BEGIN 6 AL, 01 IN 7 AL, # 01 TEST 8 0<> UNTIL 9 AL, 0 IN
10 AH, # 0 HOV 11 APDSH JMP 12 13 14 15 —> •
Listing 4. 6068 Forth
SCR # 157 0 ( 8088 FORTH - CUSTOH I/O ROUTINES 1 LABEL POUT BEGIN 2 AL, 01 IN 3 AL, # 02 TEST 4 0<> UNTIL 5 AL, BL HOV 6 0 , AL OUT 7 RET 8 LABEL (EMIT) 9 AX POP
10 BL, AL HOV 11 POUT CALL 12 CSOV BX, UP HOV 13 1A [BX] INC 14 NEXT JMP 15 —>
SCR # 158 0 ( 8068 FORTH - CUSTOH 1/0 ROUTINES 1 LABEL (CR) BL, # OD MOV 2 POUT CALL 3 BL, # OA HOV 4 POUT CALL 5 NEXT JMP 6 7 8 9 10 11 12 13 14 15 -->
SCR # 159 0 ( 8088 FORTH - BLANK 1 2 3 4 5 6 7 8 9
10 11 12 13 14
116
Listing 4. 8068 Forth
SCR # 0 < 1 : 2 t 3 4 5 6 7 8 9 10 11 12 13 14 15
160 80BB FORTH - 1
1 -FIND 0- 0 7ERROR DROP [COMPILE] LITERAL j IMMEDIATE FORGET CURRENT @ CONTEXT <? - 18 7ERROR
[COMPILE] ' DUP FENCE @ < 15 7ERROR DUP NFA DP t LFA Q CONTEXT @ I »
- - >
SCR # 161 0 ( 8088 FORTH - META1 STUFF 1 •COLON* -2 BYTE:IN : t 2 00 BYTE:IN : REPLACED:BY 7 EXEC 3 02 BYTE:IN : REPLACED:BY ICSP 4 04 BYTE:IN : REPLACED:BY CURRENT 5 08 BYTE:IN : REPLACED:BY CONTEXT 6 OC BYTE:IN : REPLACED:BY CREATE 7 OE BYTE:IN : REPLACED:BY ] 8 A
10 BYTE:IN : REPLACED:BY (;C0DE) V
10 00 BYTE:IN i REPLACED:BY 7CSP 11 02 BYTE:IN i REPLACED:BY COMPILE 12 06 BYTE:IN i REPLACED:BY SMUDGE 13 08 BYTE:IN • t REPLACED:BY [ 14 15 —>
# 162 ( 8088 FORTH - HETA1 00 BYTE:IN CONSTANT 02 BYTE;IN CONSTANT 04 BYTEIIN CONSTANT 06 BYTEiIN CONSTANT
02 BYTE:IN VARIABLE 02 BYTE!IN USER
SCR 0 1 2 3 4 5 6 7 8 9 00 BYTEiIN +ORIGIN
10 02 BYTEtIN +ORIGIN 11 06 BYTEtIN 7ERROR 12 13 10 BYTEsIN 14 IE BYTE:IN 15 -->
STUFF REPLACED:BY CREATE REPLACED:BY SMUDGE REPLACED:BY , REPLACED:BY (;CODE)
REPLACED:BY (;CODE) REPLACED:BY ({CODE)
NF*LIT* SWAP I COMPILE-ADDR DELTA - SWAP ! REPLACED:BY ERROR
REPLACED:BY WORD REPLACED:BY WORD
Listing 4. 8086 Forth
SCR # 163 0 ( 8088 FORTH - META1 STUFF 1 30 BYTEtIN EXPECT NF*LIT* SWAP t 2 32 BYTEtIN EXPECT 07 SWAP i FORTH 3 38 BYTEiIN EXPECT HF*LIT* SWAP t 4 3A BYTEtIN EXPECT 08 SWAP 1 FORTH 5 0 BYTEtIN (ABORT) REPLACED!BY ABORT 6 17 BYTEtIN ERROR REPLACEDtBY MESSAGE 7 2B BYTEtIN ERROR REPLACEDtBY QUIT 8 10 BYTEtIN CREATE REPLACEDtBY MESSAGE 9 IE BYTEiIN CREATE REPLACED!BY MIN 10 11 12 13 14
SCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
* 164 ( 8088 FORTH - META1 STUFF 0 BYTEtIN COLD NF*LIT* SWAP !
02 BYTEiIN COLD 12 COMPILE-ADDR 04 BYTElIN COLD NF*LIT* SUAF ! 06 BYTEtIN COLD ASH88 UP SVAP ! 16 BYTE:IN COLD NF*LIT* SWAP J 18 BYTEtlH COLD OC COMPILE-ADDR 1C BYTE:IK COLD NF*LIT* SWAP ! IE BYTEtIN COLD 'NF FORTH CFA 6
+ DELTA - SWAP I
+ DELTA - SWAP 1
+ SWAP 1
'NF WARH CFA ASM88 WRHl FORTH DELTA + ! ASH88 WRM ORG 8 + - FORTH 6 COMPILE-ADDR + t
'NF COLD CFA ASM88 ASM88 CLDO ORG 4 + - - >
CLDl FORTH DELTA + ! - FORTH 2 COMPILE-ADDR +
# 165 ( 8088 FORTH - META1 STUFF ASH88 {EMIT) FORTH 'NF EHIT 3 + - 'NF EMIT 1+ DELTA + ! ASM88 (KEY) FORTH 'NF KEY 3 + - 'NF KEY 1+ DELTA + t ASM88 (7TERMINAL) FORTH 'NF 7TERMINAL 3 + - 'NF 7TERHINAL
1+ DELTA + I ASMB8 (CR) FORTH 'NF CR 3 + - 'NF CR 1+ DELTA + 1
-->
118
Listing 4. B08B Forth
SCR # 166 0 ( 8088 FORTH - BACK 1 t BACK HERE - , j 2 t BEGIN 7COHP HERE 1 ; IHHEDIATE 3 J ENDIF 7C0MP 2 7PAIRS HERE OVER - SWAP t ; IHHEDIATE 4 : THEN [COMPILE] ENDIF ; IHHEDIATE 5 t DO COMPILE (DO) HERE 3 ; IHHEDIATE 6 t LOOP 3 7PAIRS COMPILE (LOOP) BACK J IMMEDIATE 7 I +LOOP 3 7PAIRS COHPILE (+LOOP) BACK | IHHEDIATE 8 ; UNTIL 1 7PAIRS COHPILE OBRANCH BACK ; IMMEDIATE 9 i END [COMPILE] UNTIL j IHHEDIATE
10 i AGAIN 1 7PAIRS COMPILE BRANCH BACK } IMMEDIATE 11 t REPEAT >R >R [COMPILE] AGAIN R> R> 12 2 - [COMPILE] ENDIF J IHHEDIATE 13 t IF COMPILE OBRANCH HERE 0,2; IMMEDIATE 14 15 —>
SCR # 167 0 ( 8088 FORTH - ELSE 1 i ELSE 2 7PAIRS COMPILE BRANCH HERE 0 , 2 SWAP 2 [COHPILE] ENDIF ; IHHEDIATE 3 t WHILE [COHPILE] IF 2+ ; IMMEDIATE 4 t SPACES 0 MAX -DUP IF 0 DO SPACE LOOP ENDIF ; 5 > <# PAD HLD ! ; 6 t #> DROP DROP HLD @ PAD OVER - } 7 t SIGN ROT 0< IF 2D HOLD ENDIF } 8 i # BASE Q H/HOD ROT 9 OVER < IF 7 + ENDIF 30 + HOLD } 9 : #S BEGIN # OVER OVER OR 0- UNTIL ;
10 i D.R >R SWAP OVER DABS <# #S SIGN #> 11 R> OVER - SPACES TYPE ; 12 t .R >R S->D R> D.R { 13 : D. 0 D.R SPACE ; 14 t . SOD D. ; 15 —>
SCR # 168 0 ( 8088 FORTH - 7 1 : 7 @ { 2 I U. 0 D, | 3 t VLIST 80 OUT t CONTEXT @ Q 4 BEGIN OUT @ C/L > IF CR 0 OUT 1 ENDIF 5 DUP ID. SPACE SPACE PFA LFA Q DUP 0-6 7TERMINAL UNTIL DROP ; 7 8 9 10 11 12 13 14 15 —>
119
Listing 4. 8088 Forth
SCR # 169 0 ( 8088 FORTH - HATCH ) 1 CODE MATCH DI, SI MOV CX FOP BX POP DX POP 2 SI POP SI PUSH 3 BEGIN AL LODS AL, [BX] CMP 4 0- IF BX PUSH CX PUSH SI PUSH 5 BEGIN CX DEC 0<> IF DX DEC 6. 0<> IF BX INC AL LODS AL, [BX] CMP 7 ROT 0<> UNTIL 8 SI POP CX POP BX POP DX POP 9 ROT ENDIF
10 DX DEC ROT 0- UNTIL 11 BEGIN AX, SI MOV SI POP SI, DI MOV DPUSH JMP 12 SWAP ENDIF SWAP ENDIF 13 CX POP CX POP CX POP 00 UNTIL NXT 14 15 -->
SCR # 170 0 ( 8088 FORTH - TASK 1 2 i TASK ; 3 4 --> 5 6 7 8 9 10 11 12 13 14 15
SCR # 171 0 < 8088 FORTH AND HETAl COMPILER - FINISH UP ) 1 09 BYTEIIN MESSAGE REPLACED:BY . 2 LAST @ DELTA - OC COHPILE-ADDR + ! 3 LAST 0 DELTA - 04 BYTEtIN FORTH ! 4 80E1 'NF X CFA 4 - DELTA +1 5 HERE DELTA - 1C COMPILE-ADDR + ! 6 HERE DELTA - IE COMPILE-ADDR + 1 7 04 BYTE!IN FORTH DELTA - 20 COMPILE-ADDR + ! 8 00 BYTEtIN 21 NFA DELTA - -4 BYTEsIN i t 9 00 -4 BYTEtIN LIT t 10 11 /SMUDGE 12 ;S 13 14 15
Listing 4. 8088 Forth
#100 HEC 7220 Graphics routines - defining words )
HEX { RDJ status WTt data port ) ( RDt data WTs command port ) < WT: soom/cofig port ( internal variable for "TO"
0 CONSTANT PTO 51 CONSTANT FT1
2 CONSTANT PT2 00 VARIABLE %TO
OTO 0 XTO I TO 1 XTO I GET 2 XTO 1 PT 3 XTO I ; 2* 2 * }
ARRAY <BUILDS 2* ALLOT D0ES> SWAP 2* + ;
ARRAY - defining word to create an array n ARRAY array.name - m array.name will leave the address of the mth element of the stack ) -->
101 NEC 7220 Graphics ARRAY FUNCTION PTO! @ PTO P! ;
( . ) @ • I PTO! 0 FUNCTION I 1 FUNCTION
@ 2 FUNCTION (.) 3 FUNCTION
routines - defining words
put address of functions ) to be used in the extended TO variable )
VALUE <BUILDS
t < ! ( 1 t D0ES> XTO @ OTO FUNCTION
0 CFA EXECUTE ;
a VALUE has three possible execution statest Formt n VALUE vname 1. vname will send n to port PTO 2. ra TO vname will save m in vname 3. GET vname puts value of vname on stack
102 NEC 7220 Graphics routines - defining words ) CMD <BUILDS , DOES> Q PT1 PJ ;
-->
a CMD has one execution state Formi n CHD cname 1. cname sends n to port PT1
CMD2 <BUILDS , DOES> @ PT2 P! ;
a CMD2 has one execution state ) Form: n CMD2 cname ) 1. cname sends n to port PT2 )
-->
Listing 4. 8068 Forth
SCR 0 1 2 3 4 5 6 7
# 103 ( NEC 7220 Graphics routines - defining words ) ( reset or sync command ) 06 VALUE FLAGS 04 VALUE HFPVSH F1 VALUE ALL ( pram command 00 VALUE SAD1L OF VALUE IMLEN1
8 10 VALUE LEH2SAD2 9 FF VALUE PTNH
10 ( cchar command ) 11 00 VALUE LR 12 ( soom , curs commands 13 00 VALUE ZFACT 14 00 VALUE EADL 00 VALUE EADM 15 -->
3E VALUE AU 07 VALUE HBP 3C VALUE VBPALH
) 00 VALUE SAD1H 40 VALUE SAD2L 3F VALUE XMLEN2
00 VALUE CTOP )
65 VALUE VSLHS 03 VALUE VFP
10 VALUE LEN1SAD1 3C VALUE SAD2M FF VALUE PTNL
00 VALUE CBOT
00 VALUE EACH
SCR 0 1 2 3 4 5 6 7 8 9 10
# 104 ( NEC 7220 Graphics routines - defined words ) ( figs command ) 00 VALUE DIR 00 VALUE DL 00 VALUE D2H 00 VALUE DHL ( mask command FF VALUE ML ( wdat command 00 VALUE VBL ( pitch )
11 40 VALUE PIT 12 ( pramS ) 13 00 VALUE PT08 14 00 VALUE PT11 15 00 VALUE PT14
00 VALUE DCL 00 VALUE DCM 00 VALUE DH 00 VALUE D2L 00 VALUE D1L 00 VALUE D1H 00 VALUE DMH
FF VALUE HH
00 VALUE WBH
00 VALUE PT09 00 VALUE PT12 00 VALUE PT15
00 VALUE PT10 00 VALUE PT13
- - >
SCR # 105 0 ( NEC 7220 Graphics routines - commands ) 1 2 3 4 00 CHD RESET 6F CHD VSYNC 4B CHD CCHAR 5 6B CHD START OD CHD DON OC CHD DOFF 6 46 CHD ZOOH 49 CHD CURS 47 CHD PITCH 7 4A CHD MASK 4C CHD FIGS 6C CHD FIGD 8 68 CHD GCHRD EO CHD CURD CO CHD LPRD 9 70 CHD PKAHO 74 CHD PRAH4 78 CHD PRAMS
10 22 CHD CLEAR 23 CHD SET 21 CHD COHP 11 20 CHD REPL AO CHD READW OF CHD SYNC 12 13 FF CHD2 ZOCON 14
Listing 4. 808S Forth
SCR # 106 0 ( NEC 7220 Graphics routines - initialisation ) 1 2 I INIT RESET FLAGS AW VSLHS HFFVSH HBP 3 VFP ALL VBPALH 4 VSYNC 5 PITCH PIT 6 PRAMO SADIL SADIH LEN1SAD1 XHLEHl 7 PRAH4 SAD2L SAD2H LEN2SAD2 XHLEH2 8 PRAH8 PTNL PTNH 9 CCHAR LR CTOP CBOT
10 ZOOM ZFACT ZOCON 11 MASK ML HH 12 CURS EADL EADM EADL 13 START ; *4 15 —>
SCR # 107 0 ( NEC 7220 Graphics routines - clear screen ) 1 i 7BUSY BEGIN,PT0 P@ OA AND 0- UNTIL f 2 : (FGl) 7BUSY FIGS DIR DCL DCH ; 3 : (WD1) CLEAR WBL WBH ; 4 i (WD2) ' SET WBL WBH ; 5 J (MSK) MASK ML MH j 6 t PCUR CURS EADL EADH EADH 7 i (STCL) 02 TO DIR FF TO DCL 8 . FF TO ML FF TO HH 9 FF TO WBH 00 TO EADL
10 00 TO EADH ; 11 t (HC) 15 0 DO (FGl) (WD1) LOOP ; 12 t (HS) 15 0 DO (FGl) (WD2) LOOP ; 13 t CLS (STCL) PCUR (MSK) (HC) ; 14 t STS (STCL) PCUR (HSK) (HS) ; 15 —>
SCR # 108 0 ( NEC 7220 Graphics routines - drawline ) 1 t VAL <BUILDS , DOES> XTO @ IF 1 OTO ELSE Q ENDIF ; 2 00 VAL XI 00 VAL X2 00 VAL DX 00 VAL ADX 3 00 VAL Y1 00 VAL Y2 00 VAL DY 00 VAL ADY 4 00 VAL +-X 00 VAL +-Y 00 VAL DLI 00 VAL DLD 5 40 VAL P 6 7 : STOXY TO Y2 TO X2 TO Y1 TO XI J 8 ( NIB> SP@ 1+ C@ SWAP DROP J 9 t <NIB 10 * ;
10 t NIB FF AND } 11 x IEAD XI 10 /HOD P Yt * + DUP NIB TO EADL HIB> TO EADM 12 <NIB TO EADH PCUR j 13 i 7CUR CURD 5 0 DO PTl P@ CR . LOOP ; 14 ; PUT TO Y1 TO XI 7EAD j 15 —>
f 3F TO DCH FF TO WBL 00 TO EADH
Listing 4. 8088 Forth
SCR #109 0 ( NEC 7220 Graphics routines - drawline ) 1 j DLX X2 XI - TO DX j 2 t DLY Y2 Y1 - TO DY ; 3 ( signi 1-poeitlve O-negative ) 4 i SIGNX DX S->D 0- TO +-X AfiS TO ADX j 5 J SIGNY DY SOD 0- TO +-Y ABS TO ADY J
6 7 : 2ARRAY <BVXLDS DUP 2* , * 2* 2-1- ALLOT DOES> 8 DUP @ >R SWAP 2* + SWAP R> * + 2+ j 9 ( n m 2ARRAY name +-x +-y name addr )
10 2 2 2ARRAY 7 QUAD 11 2 0 0 7QUAD I 12 3 0 1 7QUAD 1 ( 7QAUD is a look up table to ) 1 3 1 1 0 7 Q U A D 1 ( d e t e r m i n e t h e q u a d r a n t o f t h e l i n e ) 14 4 11 7QUAD I ( found by the sign of DX and DY ) 15 — >
SCR # 110 0 ( NEC 7220 Graphics routines - drawline ) 1 t 7X>Y ADX ADY > IF 0 ENDIF } 2 : 7X<Y ADX ADY < IF 1 ENDIF ; 3 I 7X-Y ADX ADY - IF 2 ENDIF ; 4 5 3 2ARRAY 7OCT 5 ( 7OCT ia a look up table to determine the octant ) 6 (from the quadrant and the magnitude of ADX and ADY ) 7 ( val quad oflag ) B 9 2 1 0 70CT 1 6 3 0 7 OCT !
10 3 1 1 70CT t 7 3 1 70CT I 11 3 1 2 70CT ! 7 3 2 7 OCT 1 12 5 2 0 70CT I 1 4 0 70CT 1 13 4 2 1 7OCT i 0 4 1 70CT 1 14 5 2 2 70CT I 1 4 2 70CT 1
SCR # 111 0 ( NEC 7220 Graphics routines - drawline ) 1 8 ARRAY 7AXIS 2 3 ( 7AXIS is a look up table to detemine the ) 4 ( dependent and independent axis ) 5 ( 1-Y Indep • 0-X indep > 6 7 10 7AXIS t 1 4 7AXIS t 8 0 1 7AXIS 1 0 5 7AXIS I 9 0 2 7AXIS t 0 6 7AXIS !
10 1 3 7AXIS 1 1 7 7AXIS t 11 12 t 71ND 7AXIS <3 IF ADY TO DLI ADX TO DLD ELSE 13 ADX TO DLI ADY TO DLD ENDIF j 14
. 15 -->
Listing 4. 8088 Forth
SCR #112 0 ( NEC 7220 Graphics routines - drawline+ 1 ( direction masks for figure drawing ) 2 3 t LINES 08 OR TO DIR ; 4 t ARCS 20 OR TO DIR f 5 t RECT 40 OR TO DIR ; 6 l DOT 00 OR TO DIR { 7 t AREA 10 OR TO DIR { 8 A
t SLANT 90 OR TO DIR { J
10 t (FG2) 7BUSY FIGS DIR 11 •
• (FG3) 7BUSY FIGS DIR 12 DHL 13 I (FG4) 7BUSY FIGS DIR
[, DCH DL DH D2L D2H D1L D1H [< DCH DL DH D2L D2H D1L D1H * i L DCH DL DH D2L D2H }
14 15 —>
SCR # 113 0 < NEC 7220 Graphics routines - drawline ) 1 t PARTS DUP NIB> 3F AND ; 2 t (DC) PARTS TO DCH TO DCL ; 3 : (D) PARTS TO DH TO DL ; 4 t (D2) PARTS TO D2H TO D2L ; 5 : (Dl) PARTS TO D1H TO D1L ; 6 I D DLD 2* DLI - J 7 t D2 DLD DLI - 2* ; 8 t Dl DLD 2* j 9
10 ( xl yl *2 y2 DRAVLINE ) 11 t DRAVLINE STOXY 7EAD DLX DLY SIGNX SICNY 12 +-X +-Y 7QUAD <3 7X>Y 7X<Y 7X-Y 70CT @ 13 DUP LINES 7IND DLI (DC) D (D) D2 (D2) Dl (Dl) 14 (FG2) FIGD } 15 -->
SCR # 114 0 ( NEC 7220 Graphics routines - set, clear dots ) 1 t SETRU TO DIR TO DCL TO DCH (FG1) ; 2 t 7READ PTO P@ 1 AND ; 3 : CHORD 7READ IF PT1 P@ . ENDXF { 4 t SETH FF TO ML FF TO MH (HSK) j 5 t SETHI 01 TO HL 00 TO HH (HSK) f 6 : REP REPL PTNL PTNH ; 7 6 ( wdcountH wdcountL direction RUORDS ) 9 t RUORDS SETH SETRU READU BEGIN GUORD 7READ UNTIL } 10 11 ( wdcountH wdcountL direction UUORD ) 12 i UUORD SETRU REP } 13 t 1D0T SETHI 0 0 2 UUORD ; 14 15 -->
Listing 4. 8088 Forth
SCR #115 0 ( NEC 7220 Graphics routines - zoom ) 1 : SETZ1 1+ MINUS FO OR PT2 PI ; 2 1 SETZ2 <NXB FO AND TO ZFACT ZOOM ZFACT ; 3 4 ( n ZM - room display by n ) 5 : ZM DUP SETZ1 SETZ2 ; 6 7 ( n CZH - zoom character size ) B : CZH OF AND GET ZFACT FO AND OR TO ZFACT ZOOH ZFACT j 9
10 11 12 13 14 15 -->
SCR # 116 0 ( NEC 7220 Graphics routines - rectangle ) 1 j 1- 1 - } 2 : SETR RECT 1- DUP TO D2L NIB> TO D2H 3 1- DUP TO DL DUP TO DHL NIB> DUP 4 TO DH TO DCL 03 TO DCL 00 TO DCH 5 FF TO D1L 3F TO D1H ; 6 7 ( xl yl ilen plen pdir RECTANGLE ) 6 t RECTANGLE SETR PUT (FG3) FZGD { 9 10 11 12 13 14 15 -->
SCR # 117 0 ( NEC 7220 Graphics routine - characters, fill ) 1 t (CHAR) 7 TO DCL 0 TO DCH 2 7 TO D2L 0 TO D2H 3 8 TO DL 0 TO DH ; 4 5 ( pl5, pl4, pl3, pl2, pll, plO, p9, p8 CHAR cname ) 6 ( cname will put character at current cpostion ) 7 ( based o£ pram ram data pl5-p8 ) 8 9 t CHAR <BUXLDS C, C, C, C, C, C, C, C, D0ES>
10 PRAM8 DUP 8 + SWAP DO I C@ PTO P! LOOP 11 (CHAR) (FG4) GCHRD ; 12 13 ( preceeded by n AREA or n SLANT n is the direction ) 14 15 -->
Listing 4. 8088 Forth
SCR #116 0 ( NEC 7220 Graphics routines - circle ) 1 0 VAL RAD 00 VAL RX1 00 VAL RY1 2 t 1/SQR2 RAD 3624 4C91 */ , 3 t 2MSK 3FPF AMD ; 4 t STOXYR TO RAD TO RY1 TO RX1 ; 5 1 1PT RX1 RAD + TO XI RY1 TO Y1 ; 6 : 2PT RY1 RAD + TO Y1 RX1 TO XI ; 7 t 3PT RX1 RAD - TO XI RY1 TO Y1 ; 8 t 4PT RY1 RAD - TO Yi RX1 TO XI { 9 i <CIR) ARCS 1/SQR2 2MSK DUP TO DCL NXB> TO DCH
10 RAD 1- DUP DUP TO DL NIB> TO DH 11 2 * 2HSK DUP TO D2L NIB> TO D2H 12 FF TO D1L 3F TO D1H 13 00 TO DHL 00 TO DHK <FG3> FIGD } 14 15 -->
SCR # 119 0 ( NEC 7220 Graphics routines - circle ) 1 2 ( xl yl r circle ) 3 t CXRCLE STOXYR 4 1PT 7EAD 4 (CIR) 5 7EAD 7 (CIR) 6 2PT 7BAD 5 (CIR) 7 7EAD 2 (CIR) 8 3PT 7EAD 3 (CIR) 9 7EAD 0 (CIR)
10 4PT 7EAD 1 (CIR) 11 7EAD 6 (CIR) | 12 13 14 15 -->
SCR # 120 0 ( NEC 7220 Graphics routines - area fill ) 1 J (FILL) 1- DUP TO DCL NIB> TO DCH 2 DUP TO DL DUP TO D2L 3 NXB> DUP TO DH TO D2H ; 4 5 ( ptl5....pt8 PFXLL cname ) 6 ( xl yl ilen plen dir cname ) 7 t PFXLL <BUXLDS C, C, C, C, C, C, C, C, D0ES> 8 PRAMS DUP 8 + SWAP DO X C@ PTO PI LOOP 9 (FILL) PUT (FG4) GCHRD ; 10 11 ( used with n AREA or n SLANT ) 12 13 14 15 -->
Listing 4. 8088 Forth
SCR #121 0 { NEC 7220 Graphics routines - partions ) 1 00 VAL SXl 00 VAL SYl P VAL SPl 2 00 VAL SX2 00 VAL SY2 P VAL SP2 3 i (SD1) PRAMO SADIL SAD1H LEN1SAD1 IMLEN1 ; 4 1 (SD2) PRAM4 SAD2L SAD2M LEN2SAD2 IMLEN2 ; 5 t STOSl SWAP TO SYl SWAP TO SXl | 6 J STOS2 SWAP TO SY2 SUAP TO SX2 » 7 ( xl yl lien 7SAD1 - sat area partionl ) 8 ( 7SAD1 STOSl SXl 10 /MOD SPl SYl * + DUP TO SADIL 9 HIB> TO SAD1M DROP DUP <HIB TO LEN1SAD1
. 10 HIB> TO IMLEN1 (SD1) J
11 ( xl yl lien 7SAD2 - set area partion2 ) 12 t 7SAD2 ST0S2 SX2 10 /MOD SP2 SY2 * + DUP TO SAD2L 13 HIB> TO SAD2M DROP DUP <NIB TO LEN2SAD2 14 NIB> TO IMLEN2 (SD2) ; 15 ;S
SCR # 122 0 ( NEC 7220 Graphics routines - demo ) 1 : (PTN) TO PTHL TO PTNH PRAM8 PTNL PTHH ; 2 J SLINE 255 255 (PTN) ; 3 i BORDER SLINE 0 0 240 1023 0 RECTANGLE ; 4 0 VAL CNT 32 VAL CNT2 5 t OCNT 0 TO CNT ; 6 t CNT+ CNT CNT2 + TO CNT j 7 t CUPT CNT+ CNT DUP NIB> SUAP (PTN) } B j LNS CLS SET OCNT 1023 0 DO I 0 1023 I - 240 DRAWLINE 9 CHPT CNT2 +LOOP ; 10 11 ! DEHOO CLS 0 0 240 7SAD1 32 TO CMT2 LNS ; 12 ! DEMOl 0 0 240 CLS 7SAD1 1 TO CNT2 LNS j 13 14 15 -->
SCR # 123 0 ( NEC 7220 Graphics routines - demo ) 1 t 7VSYNC BEGIN PTO P@ 96 AND UNTIL ; 2 i SLIDE 1024 0 DO I 0 240 7VSYNC 7SAD1 CNT2 +LOOP \ 3 HEX 4 55 55 55 55 55 55 55 55 PFILL PAT1 5 00 00 00 00 00 00 00 00 PFILL PAT2 6 FF FF FF FF FF FF FF FF PFILL PAT3 7 33 CC 33 CC 33 CC 33 CC PFILL PAT4 8 77 EE 77 EE 77 EE 77 EE PFILL PAT5 9 88 11 88 11 88 11 88 11 PFILL PAT6
10 FF FE FC F8 EO CO 10 00 PFILL PAT7 11 00 01 CO EO F8 FC FE FF PFILL PAT8 12 IF 10 10 IE 10 10 IF 00 CHAR EEE 13 14 DECIMAL 15 -->
128
Listing 4. 6088 Forth
SCR #124 0 ( NEC 7220 Graphics routines - demo ) 1 0 VAL WH 0 VAL LH 2 0 VAL CX 0 VAL CY 3 : (CUB) TO LH TO UH TO CY TO CX ; 4 5 ( xl yl width length CUBE ) 6 I CUBE (CUB) REPL 6 AREA CX CY VH LH PAT6 7 2 SLANT CX WH - CY VH LH PAT4 8 3 SLANT CX CY LH + LH LH PAT3 ; 9 10 11 12 13 14 15 -->
SCR # 125 0 ( NEC 7220 Graphics routines - demo ) 1 : VSLIDE 240 0 DO 0 I 240 7VSYNC 7SAD1 LOOP j 2 t TIME 20000 TO CNT ; 3 i WAIT TIME CNT 0 DO LOOP ) 4 : DZH TIME -1 14 DO I ZM WAIT -1 +L00P j 5 : BOXES 32 7 10 10 CUBE 32 260 10 10 CUBE 6 64 30 20 30 CUBE 64 270 20 30 CUBE 7 700 50 20 40 CUBE 700 300 20 40 CUBE 8 128 60 10 60 CUBE 128 300 10 60 CUBE 9 500 100 200 50 CUBE 500 340 200 50 CUBE
10 700 190 50 75 CUBE 700 430 50 75 CUBE j 11 12 J DEMO2 CLS 15 ZM BOXES DZH WAIT VSLIDE ( 13 14 15 -->
SCR # 126 0 ( NEC 7220 Graphics routines - demo ) 1 t SEE 0 CZH 5 1 DO EEE I CZH LOOP } 2 I PL1 350 120 PUT ; 3 t PL2 700 120 PUT ; 4 : DH1 7 0 DO PL1 I AREA 5EE 2 +L00P ; 5 I DH2 8 1 DO PL2 I AREA 5EE 2 +LOOP j 6 t DM3 7 0 DO PL1 I SLANT 5EE 2 +LOOP ; 7 t DM4 8 1 DO PL2 I SLANT 5EE 2 +LOOP ; 8 t DEM03 CLS REPL 0 0 240 7SAD1 DM1 DM2 ; 9 » DEM04 CLS REPL 0 0 240 7SAD1 DM3 DM4 ; 10 11 » CR1 300 120 100 CIRCLE ; 12 i CR2 700 70 50 50 7 RECTANGLE ; 13 t DEM05 CLS SET BORDER CR1 CR2 { 14 15 ;S
129
APPENDIX D
THE PROTO-TYPE
The following figures show the prototype graphics
display controller in more detail. First, figure 24 shows
the chip layout for the slave processor board. Figure 25, in
addition, shows both the front and the back of the slave
processor. Second, figure 26 shows the chip placement for
the GDC and timing board with front and back photographs in
figure 27. Third, figure 28 shows the chip layout for the
display memory board with corrisponding photographs in
figure 29. Last, figure 30 shows the whole system.
U U
U39 029
74 LS 74 LS 249 245
us
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Figure 24. Slave Processor Layout Diagram.
Figure 25., Slave Processor. Photo/ -
J2 J3
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* uts ' 74LS00
h u'4
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\ U« ' 74S04 Dues
74SOO . UIJ
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v UI3 ' 74LS74 > 74521
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Y 74S04 I K UZO * 745163
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v UIV ' 745163
S*2 SWI \ U2 74L56B9
) M4 ' 74LS244
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v UIO J 74LS373
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Figure 26. Graphics Controller Layout.
to KJ
Figure 27. CDC and Timing board Photo,
J4
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137
REFERENCES
[1] CONRAC DIVISION, Raster Graphics Handbook, Conrac Corperation, 1980.
[2] J.D. Foley and A. Van Dam, Fundamentals of Interactive Computer Graphics, Addison Wesley 1982.
13] NEC Electronics USA Inc, MPD7 220/GDC DESIGN MANUAL, (NEC 1982), V3.
[4] Sol Libes and Mark Garetz, Interfacing to S-100/IEEE 696 Microcomputers, OSBORNE/Mcgraw Hill 1981.
[5] INTEL Corperation, iAPX 86,88 User' Manual, Aug 1981.
[6] Larry P. Forsley, IEEE Computer Society Chapter Tutorial Workbook: Introduction to Forth, IEEE Computer Society 1980.
[7] John James, "What is FORTH? A Tutorial Introduction," BYTE, Aug. 1980, plOO-126.
[8] Larry P. Forsley, IEEE Computer Society Chapter Tutorial to Forth, University of Rochester, IEEE Computer Society 1982.
[9] Ray Duncan, "FORTH 8086 Assembler", Dr. Dobb's Journal, Feb. 1982, pl4-18.
[10] Thomas Newman, fig-FORTH for the 8086/88 Version 1.0, Forth Interest Group, Feb, 1981.
[11] William F. Ragsdale, fig-FORTH INSTALLATION MANUAL GLOSSARY MODEL, Forth Interest Group, Rel. 1, Aug 1980 .
[12] John Cassady, METAFORTH A Matacompiler for FIG-FORTH, 1980.
[13] Henry Laxen, A Techniquess Tutorial: Meta Compiling 1, FORTH Dimensions Mar/Apr 1983,
P 1 9 - 2 2 .
138
REFERNCES--continued
[14] Hency Laxen, Techniques Tutorial: Meta Compiling 2, FORTH Dimensions Jul/Aug 1983,
P23-24.
[15] Henry Laxen, Techniques Tutorial: Meta Compiling 3, FORTH Dimensions Sept/Oct 1983, P31-32.
[16] Leo Brodie, Starting Forth, Forth Inc. 1981.
[17] Mitch Derick & Linda Baker, Forth Encyclopedia: The Complete FORTH Programmer's Manual, Mountian
View Press, Inc. 1982.
[18] Tomothy Huang, And So Forth, Revised 1983.
[19] Russell Recter and George alexy, THE 8086 BOOK, OSBORNE/Mcgraw-Hill 1980.