integrated cmos hall microsystems and application for current...

IMS University of Pavia

Integrated Microsystems LaboratoryUniversity of Pavia

Integrated CMOS Hall Microsystemsand Application for Current Sensors

PROF. FRANCO MALOBERTITutor

HADI HEIDARIPh.D. Student

1st Year PhD Activities Report 2011/2012


OUTLINE

INTRODUCTION AND MOTIVATION

SYSTEM ARCHITECTURE AND HALL EFFECT DEVICES

RESEARCH STATUS AND IMPLEMENTATION

CONCLUSION AND FUTURE WORK


There is still room to change the concepts for new Hall devices and push the limits of Hall

sensors in existing applications.

• Looking for new approach to design the sensor system with:

Low Power - High Sensitivity

• Integrate a test chip for experimental verification of model

MOTIVATION

INTRODUCTION

GOAL OF THIS PROJECT

• Model of the sensor in the Hall configuration and Current-Mode configuration

• Design of the Current-Mode Sensor and readout circuit


- A bias voltage across the hall plate sets up a fixed current

- The moving charges in the hall plate are acted upon by the Lorentz force: F=q(VxB)

- In the presence of magnetic field, this force pushes charges to opposite sides of Hall plate

- This signal is cleaned up and amplified to provide a sensitivity in mV/A

How Hall Effect Devices Work

The Hall Effect was discovered by E. F. Hall in 1879.

INTRODUCTION

The cross-shaped structure of Hall device is

optimized to reduce Hall offset and improve

sensitivity.


STATE-OF-THE-ART IN CMOS HALL EFFECT MAGNETIC SENSORSINTRODUCTION

Over the last decade there were four major

achievements in the development of Hall effect

magnetic sensors in CMOS technology:

• increase of magnetic resolution,

• development of monolithic three dimensional (3D)

Hall effect sensors,

• increase of sensors’ bandwidth,

• and stabilization of sensors’ sensitivity and offset

drift.


New Approach for Problems of Conventional Hall DevicesINTRODUCTION

PROBLEMS OF CONVENTIONAL HALL DEVICES

• OFFSET

• SENSITIVITY

• POWER

Conventional Hall-Effect Device New Idea: Current Differences approach


SPIN SPLIT CURRENT HALL PLATE

• Input Current is rotated, while the Current

output is summed during spinning

• Symmetrical offsets are canceled out

• Spinning-current conventional Hall sensor

offset 10-100µT

SPINNING CURRENT


HALL SENSOR OFFSET REDUCTIONSPINNING CURRENT

• Offset drift of electronics must be lower than 25nV

• CMOS Amplifiers exhibit a typical offset of 1mV and corresponding drift

• Offset and drift reduction methods:

– Chopper instrumentation amplifier(10µV)

– Charge-injection dead band(200nV)

– A nested chopper architecture(100nV)

Combine them all


OUTLINE

INTRODUCTION





SENSOR ARCHITECTURESYSTEM ARCHITECTURE


SENSOR ARCHITECTURESYSTEM ARCHITECTURE

1. the Hall device level

2. the front end level comprising the

device and interface electronics

3. system level topology with

optimization of analog building

blocks.


OUTLINE

INTRODUCTION






ARCHITECTURE STUDY FOR THE HALL EFFECT SENSORS

COMSOL SIMULATION

VERILOG-A MODELING AND SIMULATION

TRANSISTOR LEVEL IMPLEMENTATION

LAYOUT, TAPEOUT AND MEASUREMENT

RESEARCH STATUS


COMSOL SIMULATIONCOMSOL SIMULATION


TOP PLATE INPUT AND OUTPUT CURRENTS

COMSOL SIMULATION

Magnetic Field Current [uA]

Bz [Hz] A,B C D0 12 6 6

0.001 12 6.00033 5.999670.002 12 6.00067 5.999330.003 12 6.001 5.9990.004 12 6.00133 5.998670.005 12 6.00166 5.998340.006 12 6.002 5.9980.007 12 6.00233 5.997670.008 12 6.00266 5.997340.009 12 6.00299 5.997010.01 12 6.00333 5.99667

0.011 12 6.00366 5.996340.012 12 6.00399 5.996010.013 12 6.00432 5.995680.014 12 6.00466 5.995340.015 12 6.00499 5.995010.016 12 6.00532 5.994680.017 12 6.00565 5.994350.018 12 6.00599 5.994010.019 12 6.00632 5.993680.02 12 6.00665 5.99335


COMSOL SIMULATION

AVERAGE TOP PLATE AFTER SPINNING-CURRENT

First Output AV1 = C1 + D2 + A3 + B4Second Output AV2 = D1 + A2 + B3 + C4

Magnetic Field Current [A]

Bz [Hz] AV1 AV20 24 24

0.001 24.00133 23.998670.002 24.00266 23.997340.003 24.00399 23.996010.004 24.00532 23.994680.005 24.00665 23.993350.006 24.00798 23.992020.007 24.00931 23.990690.008 24.01064 23.989360.009 24.01197 23.988030.01 24.0133 23.9867

0.011 24.01463 23.985370.012 24.01597 23.984030.013 24.0173 23.98270.014 24.01863 23.981370.015 24.01996 23.980040.016 24.02129 23.978710.017 24.02262 23.977380.018 24.02395 23.976050.019 24.02528 23.974720.02 24.02661 23.97339


COMSOL SIMULATION

* Initial Spinning Current** Average of π/2 Rotation

*** Average of π Rotation**** Average of Overall Spinning

DIFFERENCE AVERAGE BOTH PLATE AFTER SPINNING-CURRENT

Diff1 = AV1(Top Plate) + AV2(Bottom Plate)Diff2 = AV2(Top Plate) + AV1(Bottom Plate)


DIFFERENCE AVERAGE BOTH PLATE AFTER SPINNING-CURRENTCOMSOL SIMULATION

MagneticField Current (uA)

Bz(T) Diff1(uA) Diff2(uA)0 -1.92E-06 1.92E-06

0.001 0.00317 -0.003170.002 0.00634 -0.006340.003 0.00952 -0.009520.004 0.01269 -0.012690.005 0.01586 -0.015860.006 0.01903 -0.019030.007 0.0222 -0.02220.008 0.02538 -0.025380.009 0.02855 -0.028550.01 0.03172 -0.03172

0.011 0.03489 -0.034890.012 0.03807 -0.038070.013 0.04124 -0.041240.014 0.04441 -0.044410.015 0.04758 -0.047580.016 0.05076 -0.050760.017 0.05393 -0.053930.018 0.0571 -0.05710.019 0.06027 -0.060270.02 0.06344 -0.06344

Diff1 = AV1(Top Plate) + AV2(Bottom Plate)Diff2 = AV2(Top Plate) + AV1(Bottom Plate)


VERILOG-A IMPLEMENTATION OF HALL DEVICEVERILOG-A IMPLEMENTATION

MAGNETIC FIELD COMSOL VERILOG-A

BZ [mT] ID [uA] IC [uA] ID [uA] IC [uA]

0 mT 6 6 6 6

10 mT 6.0033 5.99667 6.003373 5.996627

20 mT 6.00665 5.99335 6.006746 5.993254

* Input current to IA,B=12uA


Op-Amp for 180nm CMOS Technology

Parameter Symbol [Unit] Value Parameter Symbol [Unit] Value

TECHNOLOGY CMOS 180nm DC GAIN Av [dB] 82

POWER SUPPLY VDD [V] 1.8 UNIT FREQUENCY GBW [MHz] 17.6

LOAD CONDITION CL [fF] 250 PHASE MARGIN ΦM [Degree] 60

OP-AMP


OUTLINE

INTRODUCTION





CONCLUSION

• The research activities started by modeling the Hall sensor with optimized cross-shaped

hall plate to reduce Hall offset and improve sensitivity. A novel technique for current

injection has been developed for saving power and improving the sensitivity of the sensor.

• The model has been simulated at the first using COMSOL Multiphysics. After that the model

has been then implemented in Verilog-A description language, for behavioral simulations in

the Cadence environment.

• The readout circuit consists of an Op-Amp that behaves like an integrator, two Hall plates,

the bias circuit and the Common Mode Feedback (CMFB). In order to eliminate the

dynamic offset cancellation technique through Hall current spinning is applied.

• The achieved results improve the state-of-the-art conventional Hall sensors in consumed

power and sensitivity.

• After the sensor modeling, the activity is now focused on the transistor level design in a

0.18 µm CMOS technology.



FUTURE WORK AND OTHER ACTIVITIES

FUTURE WORK:

• Layout and doing the chip measurements

OTHER ACTIVITIES:• “Galvanic Insulated Data Transmission via Short Range Magnetic Coupling”, Report

within University project and STMicroelectronics, May 2012.

COURSE:• TOM 2012• RFIC Workshop Istanbul• PhD Seminars

CREDITS: 12.2



AKNOWLEDGMENT

FRANCO MALOBERTI

HEAD OF THE INTEGRATED MICRO SYSTEM GROUP

THANKS FOR YOUR ATTENTION!

integrated cmos hall microsystems and application for current...

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