intel 2-mbit smart voltage device guide

8/12/2019 Intel 2-Mbit Smart Voltage device guide

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E SEE NEW DESIGN RECOMMENDATIONS

December 1997 Order Number: 290531-005

Intel SmartVoltage Technology 5 V or 12 V Program/Erase 3.3 V or 5 V Read Operation

Very High-Performance Read 5 V: 60 ns Access Time 3 V: 110 ns Access Time

Low Power Consumption Max 60 mA Read Current at 5 V Max 30 mA Read Current at

3.3 V3.6 V

x8/x16-Selectable Input/Output Bus 28F200 for High Performance 16- or

32-bit CPUs

x8-Only Input/Output Architecture 28F002B for Space-Constrained

8-bit Applications

Optimized Array Blocking Architecture One 16-KB Protected Boot Block Two 8-KB Parameter Blocks 96-KB and 128-KB Main Blocks Top or Bottom Boot Locations

Extended Temperature Operation40 C to +85 C

Extended Block Erase Cycling 100,000 Cycles at Commercial Temp 10,000 Cycles at Extended Temp

Automated Word/Byte Program andBlock Erase Command User Interface Status Registers Erase Suspend Capability

SRAM-Compatible Write Interface

Automatic Power Savings Feature

Reset/Deep Power-Down Input 0.2 A ICCTypical

Provides Reset for Boot Operations

Hardware Data Protection Feature Absolute Hardware-Protection for

Boot Block Write Lockout during Power

Transitions

Industry-Standard Surface MountPackaging 40-, 48-, 56-Lead TSOP 44-Lead PSOP

Footprint Upgradeable to 4-Mbit and8-Mbit Boot Block Flash Memories

ETOX IV Flash Technology

New Design Recommendations:

For new 2.7 V3.6 V VCC designs with this device, Intel recommends using the Smart 3 Advanced BootBlock. Reference Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family datasheet,order number 290580.

For new 5 V VCCdesigns with this device, Intel recommends using the 2-Mbit Smart 5 Boot Block. ReferenceSmart 5 Flash Memory Family2, 4, 8 Mbitdatasheet, order number 290599.

These documents are also available at Intels website, http://www.intel.com/design/flcomp.

REFERENCE ONLY

2-MBIT SmartVoltage BOOT BLOCK

FLASH MEMORY FAMILY

28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B


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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel orotherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions ofSale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating tosale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, orinfringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, lifesaving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B may contain design defects or errors known as errata. Currentcharacterized errata are available on request.

*Third-party brands and names are the property of their respective owners.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may beobtained from:

Intel CorporationP.O. Box 5937Denver, CO 8021-9808

or call 1-800-548-4725or visit Intels website at http:/ /www.intel.com

COPYRIGHT INTEL CORPORATION, 1997 CG-041493

*Third-party brands and names are the property of their respective owners..


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E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

3SEE NEW DESIGN RECOMMENDATIONS

CONTENTS

PAGE PAGE

1.0 PRODUCT FAMILY OVERVIEW.....................51.1 New Features in the SmartVoltage Products5

1.2 Main Features..............................................5

1.3 Applications..................................................6

1.4 Pinouts.........................................................7

1.5 Pin Descriptions .........................................11

2.0 PRODUCT DESCRIPTION............................13

2.1 Memory Blocking Organization...................13

2.1.1 One 16-KB Boot Block.........................13

2.1.2 Two 8-KB Parameter Blocks................13

2.1.3 One 96-KB + One 128-KB Main Block.13

3.0 PRODUCT FAMILY PRINCIPLES OF

OPERATION ................................................153.1 Bus Operations ..........................................15

3.2 Read Operations........................................15

3.2.1 Read Array..........................................15

3.2.2 Intelligent Identifiers ............................17

3.3 Write Operations ........................................17

3.3.1 Command User Interface (CUI) ...........17

3.3.2 Status Register....................................20

3.3.3 Program Mode.....................................21

3.3.4 Erase Mode.........................................21

3.4 Boot Block Locking ....................................22

3.4.1 VPP= VILfor Complete Protection .......22

3.4.2 WP# = VILfor Boot Block Locking .......22

3.4.3 RP# = VHHor WP# = VIHfor Boot BlockUnlocking ...........................................22

3.4.4 Upgrade Note for 8-Mbit 44-PSOPPackage .............................................22

3.5 Power Consumption...................................26

3.5.1 Active Power .......................................26

3.5.2 Automatic Power Savings (APS) .........26

3.5.3 Standby Power ....................................26

3.5.4 Deep Power-Down Mode.....................26

3.6 Power-Up/Down Operation.........................26

3.6.1 RP# Connected To System Reset .......26

3.6.2 VCC, VPPAND RP# Transitions............27

3.7 Power Supply Decoupling ..........................27

3.7.1 VPPTrace On Printed Circuit Boards..27

4.0 ELECTRICAL SPECIFICATIONS..................28

4.1 Absolute Maximum Ratings........................28

4.2 Commercial Operating Conditions..............28

4.2.1 Applying VCCVoltages.........................29

4.3 Capacitance ...............................................29

4.4 DC CharacteristicsCommercial ...............30

4.5 AC CharacteristicsCommercial ...............34

4.6 AC CharacteristicsWE#-Controlled Write

OperationsCommercial ..........................374.7 AC CharacteristicsCE#-Controlled Write

OperationsCommercial ..........................40

4.8 Erase and Program TimingsCommercial.43

4.9 Extended Operating Conditions..................43

4.9.1 Applying VCCVoltages.........................44

4.10 Capacitance .............................................44

4.11 DC CharacteristicsExtendedTemperature Operations............................45

4.12 AC CharacteristicsRead OnlyOperationsExtended Temperature .........49

4.13 AC CharacteristicsWE#-Controlled WriteOperations Extended Temperature ........50

4.14 AC CharacteristicsCE#-Controlled Write

Operations Extended Temperature ........524.15 Erase and Program TimingsExtended

Temperature..............................................53

5.0 ORDERING INFORMATION..........................54

6.0 ADDITIONAL INFORMATION.......................55

Related Intel Information ..................................55


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2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4 SEE NEW DESIGN RECOMMENDATIONS

REVISION HISTORY

Number Description

-001 Initial release of datasheet.

-002 Status changed from Product Preview to Preliminary28F200CV/CE/BE references and information added throughout.

2.7 V CE/BE specs added throughout.The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,

3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.Sections 5.1, 6.1 changed to Applying VCCVoltages. These sections completely

changed to clarify VCCramp requirements.IPPD3.3 V Commercial spec changed from 10 to 5 A.Capacitance tables added after commercial and extended DC Characteristics tables.Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.Test configuration drawings (Fig. 14, 22) consolidated into one, with component

values in table. (Component values also rounded off).tELFL, tELFH, tAVFLchanged from 7 to 5 ns for 3.3 V BV-60 commercial and 3.3 V

TBV-80 extended, 10 to 5 ns for 3.3 V BV-80 and BV-120 commercial.tWHAXand tEHAXchanged from 10 to 0 ns.tPHWLchanged from 1000 ns to 800 ns for 3.3 V BV-80, BV-120 commercial.tPHELchanged from 1000 ns to 800 ns for 3.3 V BV-60, BV-80, and BV-120 commercial.

-003 Applying VCCvoltages (Sections 5.1 and 6.1) rewritten for clarity.Minor cosmetic changes/edits.

-004 Corrections: This pin not available on 44-PSOP inaccurate statement removed from pindescription for WP# pin; Spec tQWL corrected to tQVVL; intelligent identifier valuescorrected; Intel386 EX block diagram updated because new 386 specs require lessglue logic.

Max program times for parameter and 96-KB main block added.Specs tELFLand tELFHchanged from 5 ns (max) to 0 ns (min).Specs tEHQZand tHQZimproved.New specs tPLPHand tPLQZadded from Specification Update document (297612).

-005 Corrections: Figure 4, corrected pin designation 3 to NC from A17on PA28F200.Corrected typographical errors in Ordering Information.

Added New Design Recommendationssection to cover page.UpdatedErase Suspend/Resume Flowchart


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1.0 PRODUCT FAMILY OVERVIEW

This datasheet contains the specifications for thetwo branches of products in the SmartVoltage2-Mbit boot block flash memory family. These-BV/CV suffix products offer 3.0 V3.6 V operationand also operate at 5 V for high-speed accesstimes. Throughout this datasheet, the 28F200refers to all x8/x16 2-Mbit products, while

28F002B refers to all x8 2-Mbit boot blockproducts. Section 1.0 provides an overview of theflash memory family including applications, pinoutsand pin descriptions. Sections 2.0 and 3.0describe the memory organization and operationfor these products. Section 4.0 contains thefamilys operating specifications. Finally, Sections5.0 and 6.0 provide ordering and documentreference information.

1.1 New Features in theSmartVoltage Products

The SmartVoltage boot block flash memory familyoffers identical operation with the BX/BL 12 Vprogram products, except for the differences listed

below. All other functions are equivalent to currentproducts, including signatures, write commands,and pinouts.

WP# pin has replaced a DU (Dont Use) pin.Connect the WP# pin to control signal or to

VCCor GND (in this case, a logic-level signal

can be placed on DU pin). Refer to Tables 2

and 9 to see how the WP# pin works.

5 V program/erase operation has been added.If switching VPP for write protection, switch to

GND (not 5 V) for complete write protection.

To take advantage of 5 V write-capability,

allow for connecting 5 V to VPP and

disconnecting 12 V from VPPline.

Enhanced circuits optimize low VCCperformance, allowing operation down to

VCC= 3.0 V.

If you are using BX/BL 12 V VPP boot blockproducts today, you should account for thedifferences listed above and also allow forconnecting 5 V to VPP and disconnecting 12 Vfrom VPPline, if 5 V writes are desired.

1.2 Main Features

Intels SmartVoltage technology is the mostflexible voltage solution in the flash industry,providing two discrete voltage supply pins: VCCforread operation, and VPP for program and eraseoperation. Discrete supply pins allow systemdesigners to use the optimal voltage levels fortheir design. This product family, specifically the28F200BV/CV, and 28F002BV provide program/erase capability at 5 V or 12 V. The 28F200BV/CVand 28F002BV allow reads with VCC at 3.3 V 0.3 V or 5 V. Since many designs read from theflash memory a large percentage of the time, readoperation using the 3.3 V ranges can provide greatpower savings. If read performance is an issue,however, 5 V VCC provides faster read accesstimes.

For program and erase operations, 5 V VPPoperation eliminates the need for in systemvoltage converters, while 12 V VPP operationprovides faster program and erase for situationswhere 12 V is available, such as manufacturing ordesigns where 12 V is in-system. For designsimplicity, however, just hook up VCCand VPP tothe same 5 V 10% source.

The 28F200/28F002B boot block flash memoryfamily is a high-performance, 2-Mbit (2,097,152bit) flash memory family organized as either256 Kwords of 16 bits each (28F200 only) or512 Kbytes of 8 bits each (28F200 and 28F002B).

Table 1. SmartVoltage Provides Total Voltage Flexibility

Product Bus VCC VPP

Name Width 3.3 V 0.3 V 5 V 5%5 V 10%

5 V 10% 12 V 5%

28F002BV-T/B x8

28F200BV-T/B x8 or x16

28F200CV-T/B x8 or x16


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Separately erasable blocks, including a hardware-lockable boot block (16,384 bytes), two parameterblocks (8,192 bytes each) and main blocks (oneblock of 98,304 bytes and one block of 131,072bytes), define the boot block flash familyarchitecture. See Figures 7 and 8 for memorymaps. Each block can be independently erased andprogrammed 100,000 times at commercialtemperature or 10,000 times at extended

temperature.

The boot block is located at either the top (denotedby -Tsuffix) or the bottom (-Bsuffix) of the addressmap in order to accommodate differentmicroprocessor protocols for boot code location.The hardware-lockable boot block providescomplete code security for the kernel code requiredfor system initialization. Locking and unlocking ofthe boot block is controlled by WP# and/or RP#(see Section 3.4 for details).

The Command User Interface (CUI) serves as theinterface between the microprocessor ormicrocontroller and the internal operation of theboot block flash memory products. The internalWrite State Machine (WSM) automatically executes

the algorithms and timings necessary for programand erase operations, including verifications,thereby unburdening the microprocessor ormicrocontroller of these tasks. The Status Register(SR) indicates the status of the WSM and whether itsuccessfully completed the desired program orerase operation.

Program and Erase Automation allows program anderase operations to be executed using an industry-standard two-write command sequence to the CUI.Data programming is performed in word (28F200family) or byte (28F200 or 28F002B families)increments. Each byte or word in the flash memorycan be programmed independently of other memorylocations, unlike erases, which erase all locationswithin a block simultaneously.

The 2-Mbit SmartVoltage boot block flash memoryfamily is also designed with an Automatic PowerSavings (APS) feature which minimizes systembattery current drain, allowing for very low powerdesigns. To provide even greater power savings,the boot block family includes a deep power-downmode which minimizes power consumption byturning most of the flash memorys circuitry off. Thismode is controlled by the RP# pin and its usage isdiscussed in Section 3.5, along with other powerconsumption issues.

Additionally, the RP# pin provides protectionagainst unwanted command writes due to invalidsystem bus conditions that may occur duringsystem reset and power-up/down sequences. Forexample, when the flash memory powers-up, itautomatically defaults to the read array mode, butduring a warm system reset, where powercontinues uninterrupted to the system components,the flash memory could remain in a non-read mode,

such as erase. Consequently, the system Resetsignal should be tied to RP# to reset the memory tonormal read mode upon activation of the Resetsignal. See Section 3.6.

The 28F200 provides both byte-wide or word-wideinput/output, which is controlled by the BYTE# pin.Please see Table 2 and Figure 16 for a detaileddescription of BYTE# operations, especially theusage of the DQ15/A1pin.

The 28F200 products are available in aROM/EPROM-compatible pinout and housed in the44-lead PSOP (Plastic Small Outline) package, the48-lead TSOP (Thin Small Outline, 1.2 mm thick)package and the 56-lead TSOP as shown inFigures 4, 5 and 6, respectively. The 28F002

products are available in the 40-lead TSOPpackage as shown inFigure 3.

Refer to the DC Characteristics, Section 4.4(commercial temperature) and Section 4.11(extended temperature), for complete current andvoltage specifications. Refer to the ACCharacteristics, Section 4.5 (commercialtemperature) and Section 4.12 (extendedtemperature), for read, write and erase performancespecifications.

1.3 Applications

The 2-Mbit boot block flash memory familycombines high-density, low-power, high-

performance, cost-effective flash memories withblocking and hardware protection capabilities. Theirflexibility and versatility reduce costs throughout theproduct life cycle. Flash memory is ideal for Just-In-Time production flow, reducing system inventoryand costs, and eliminating component handlingduring the production phase.

When your product is in the end-users hands, andupdates or feature enhancements becomenecessary, flash memory reduces the update costsby allowing user-performed code changes insteadof costly product returns or technician calls.


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The 2-Mbit boot block flash memory family providesfull-function, blocked flash memories suitable for awide range of applications. These applicationsinclude extended PC BIOS and ROM-ableapplications storage, digital cellular phone programand data storage, telecommunication boot/firmware,printer firmware/font storage and various otherembedded applications where program and datastorage are required.

Reprogrammable systems, such as personalcomputers, are ideal applications for the 2-Mbitflash memory products. Increasing softwaresophistication greatens the probability that a codeupdate will be required after the PC is shipped. Forexample, the emerging of plug and play standardin desktop and portable PCs enables auto-configuration of ISA and PCI add-in cards.However, since the plug and play specificationcontinues to evolve, a flash BIOS provides a cost-effective capability to update existing PCs. Inaddition, the parameter blocks are ideal for storingthe required auto-configuration parameters,allowing you to integrate the BIOS PROM andparameter storage EEPROM into a singlecomponent, reducing parts costs while increasing

functionality.

The 2-Mbit flash memory products are alsoexcellent design solutions for digital cellular phoneand telecommunication switching applicationsrequiring very low power consumption, high-performance, high-density storage capability,modular software designs, and a small form factorpackage. The 2-Mbits blocking scheme allows foreasy segmentation of the embedded code with16 Kbytes of hardware-protected boot code, four

main blocks of program code and two parameterblocks of 8 Kbytes each for frequently updated datastorage and diagnostic messages (e.g., phonenumbers, authorization codes).

Intels boot block architecture provides a flexiblevoltage solution for the different design needs ofvarious applications. The asymmetrically-blockedmemory map allows the integration of several

memory components into a single flash device. Theboot block provides a secure boot PROM; theparameter blocks can emulate EEPROMfunctionality for parameter store with propersoftware techniques; and the main blocks providecode and data storage with access times fastenough to execute code in place, decreasing RAMrequirements.

1.4 Pinouts

Intels SmartVoltage Boot Block architectureprovides upgrade paths in every package pinout tothe 4 or 8-Mbit density. The 28F002B 40-leadTSOP pinout for space-constrained designs isshown in Figure 3. The 28F200 44-lead PSOP

pinout follows the industry-standard ROM/EPROMpinout, as shown in Figure 4. For designs thatrequire x16 operation but have space concerns,refer to the 48-lead pinout inFigure 5. Furthermore,the 28F200 56-lead TSOP pinout shown in Figure 6provides compatibility with BX/BL family productpackages.

Pinouts for the corresponding 4-Mbit and 8-Mbitcomponents are also provided for convenientreference. 2-Mbit pinouts are given on the chipillustration in the center, with 4-Mbit and 8-Mbitpinouts going outward from the center.


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i386 EX CPU(25 MHz)

A[17:1]

CS#

RD#

WR#

CE#

A[16:0]

OE#

WE#

D[15:0] D[15:0]

RP#RESET

RESET

28F200BV-60

NOTE:

A data bus buffer may be needed for processor speeds above 25 MHz. 0530_01

Figure 1. 28F200 Interface to Intel386 EX Microprocessor

UCS#

80C188EB

-A15

A8

ALE

P1.X

WR#RD#

RESIN#

System Reset

WE#OE#

VPP

ADDRESSLATCHES

LE

ADDRESSLATCHES

LE

CE#

RP#

28F002-T-AD7AD0

A[16:17]

DQ0-DQ7

WP#

VCC

10K

P1.X

VCC

A0-A

17

0530_02

Figure 2. 28F002B Interface to Intel80C188EB 8-Bit Embedded Microprocessor


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28F002B

Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

32313029

2827262524232221

33343536

3738

3940

2019

1718

1234

56789

10

11121314

1615

A1

A2

A3

RP#WE#

VPP

A16A15

A7A6A5A4

A14A13

A8

A9

A11

A12

WP#

DQ7

CE#

OE#GND

A0

DQ6DQ5DQ4

DQ2DQ1DQ0

VCC

DQ3

A17GND

NC

A10

NCNC

NC

28F004B 28F004B

A1

A2

A3

RP#WE#

VPP

A16A15

A7A6A5A4

A14A13

A8

A9

A11

A12

WP#A18

DQ7

CE#

OE#GND

A0

DQ6DQ5DQ4

DQ2DQ1DQ0

VCC

DQ3

A17GND

NC

A10

NCNC

VCCVCC

28F008B

DQ7

CE#

OE#GND

A0

DQ6DQ5DQ4

DQ2DQ1DQ0

VCC

DQ3

A17GND

NC

A10

NC

VCC

28F008B

A1

A2

A3

RP#WE#

VPP

A16A15

A7A6A5A4

A14A13

A8

A9

A11

A12

WP#A18

A19

0530_03

Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications

PA28F200BOOT BLOCK

44-Lead PSOP0.525" x 1.110"

TOP VIEW GND

WE#

RP#

BYTE#

A8A9

A11A12A13A14

A16

DQ7DQ14DQ6DQ13

DQ12DQ4VCC

DQ5

A10

A15

32

31

30

2928

27

26

25

2423

33

34

3536

37

38

39

40

4142

43

44

CE#

WP#

GND

OE#

A7

A5

A6

A4A 3A 2A 1A 0

DQ0DQ8DQ1DQ9DQ2DQ10DQ3DQ11 22

21

20

19

17

18

1

2

34

5

6

7

8

910

11

12

13

14

16

15

VPP

NC

CE#

WP#

GNDOE#

A7

A5

A6

A4A 3A 2A 1A 0

DQ0DQ8DQ1DQ9DQ2DQ10DQ3DQ11

VPP

GND

WE#

RP#

BYTE#

A8A9

A11A12A13A14

A16

DQ7DQ14DQ6DQ13

DQ12DQ4VCC

DQ5

A10

A15

28F400 28F400

DQ15 -1/A DQ15 -1/A

CE#

GNDOE#

A7

A5

A6

A4A 3A 2A 1A 0

DQ0DQ8DQ1DQ9DQ2DQ10DQ3DQ11

VPP

28F800

GND

WE#

RP#

BYTE#

A8A9

A11A12A13A14

A16

DQ7DQ14DQ6DQ13

DQ12DQ4VCC

DQ5

A10

A15

28F800

DQ15 -1/A

A 17 A17

A 18

0530_04

NOTE:Pin 2 is WP# on 2- and 4-Mbit devices but A18on the 8-Mbit because no other pins were available for the high orderaddress. Thus, the 8-Mbit in the 44-lead PSOP cannot unlock the boot block without RP# = VHH(12 V). To allow upgrades tothe 8 Mbit from 2/2 Mbit in this package, design pin 2 to control WP# at the 2/4 Mbit level and A18at the 8-Mbit density. SeeSection 3.4 for details.

Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards


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28F200

Boot Block48-Lead TSOP

12 mm x 20 mm

TOP VIEW333435363738

3940

414243

4445464748

242322212019

1718

123456789

10

11121314

1615

2526

27

282930

3132

CE#

OE#GND

A0

VCC

GNDBYTE#

A16

DQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4

DQ11

DQ10DQ2DQ9DQ1DQ8DQ0

DQ3

CE#

OE#GND

A0

VCC

GNDBYTE#

A16


DQ11

DQ10DQ2DQ9DQ1DQ8DQ0

DQ3

CE#

OE#GND

A0

VCC

GNDBYTE#

A16


DQ11

DQ10DQ2DQ9DQ1DQ8DQ0

DQ3

28F400 28F80028F40028F800

1

RP#WE#

NC

NCNC

WP#

A15A14A13A12A11A10A9A8

VPP

A17

A6

A7

A4

A5

A3A2A

RP#WE#

NC

NCNC

WP#

A15A14A13A12A11A10A9A8

VPP

A6

A7

A4

A5

A3A2A

RP#WE#

NC

NCNC

WP#

A18

A15A14A13A12A11A10A9A8

VPP

A17

A6

A7

A4

A5

A3A2A

NC NC

NC

0530_05

Figure 5. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation

28F200Boot Block

56-Lead TSOP

14 mm x 20 mm

TOP VIEW

28

2726252423222120

19

1718

123456789

1011121314

1615

A1

A2

A3

RP#WE#

A15

A7A6A5A4

A14A13

A8

A9

A11

A12

NC

VPP

NCNC

NCNC

NCNC

A10

WP#NC

NC

A1

A2

A3

RP#WE#

A15

A7A6A5A4

A14A13

A8

A9

A11

A12

NC

VPP

NCNC

NCNC

NCNC

A10

WP#NC

DQ7

CE#

OE#

GND

A0

DQ6

DQ5

DQ4

DQ2

DQ1

DQ0

VCC

VCC

DQ3

GND

NCNC

DQ9

DQ10

DQ11

DQ8

BYTE#

DQ15/A-1

DQ14

DQ13

DQ12

A16NC

28F400 28F400

4142434445464748

495051

5253545556

32313029

33

3435

3637

383940

DQ7

CE#

OE#

GND

A0

DQ6

DQ5

DQ4

DQ2

DQ1

DQ0

VCC

VCC

DQ3

GND

NCNC

DQ9

DQ10

DQ11

DQ8

BYTE#

DQ15/A-1

DQ14

DQ13

DQ12

A16NC

A17

0530_06

Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits


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1.5 Pin Descriptions

Table 2. 28F200/002 Pin Descriptions

Symbol Type Name and Function

A0A17 INPUTADDRESS INPUTSfor memory addresses. Addresses are internally latchedduring a write cycle. The 28F200 only has A0 A16 pins, while

the 28F002B has A0 A17.

A9 INPUT ADDRESS INPUT:When A9is at VHHthe signature mode is accessed. During

this mode, A0decodes between the manufacturer and device IDs. When BYTE#is at a logic low, only the lower byte of the signatures are read. DQ 15/A1is adont care in the signature mode when BYTE# is low.

DQ0DQ7 INPUT/OUTPUT

DATA INPUTS/OUTPUTS:Inputs array data on the second CE# and WE# cycleduring a Program command. Inputs commands to the Command User Interfacewhen CE# and WE# are active. Data is internally latched during the write cycle.Outputs array, Intelligent Identifier and status register data. The data pins float totri-state when the chip is de-selected or the outputs are disabled.

DQ8DQ15 INPUT/OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycleduring a Program command. Data is internally latched during the write cycle.Outputs array data. The data pins float to tri-state when the chip is de-selected orthe outputs are disabled as in the byte-wide mode (BYTE# = 0). In the byte-widemode DQ15/A1becomes the lowest order address for data output on DQ0DQ7.The 28F002B does not include these DQ8DQ15 pins.

CE# INPUT CHIP ENABLE:Activates the devices control logic, input buffers, decoders and

sense amplifiers. CE# is active low. CE# high de-selects the memory device andreduces power consumption to standby levels. If CE# and RP# are high, but notat a CMOS high level, the standby current will increase due to current flowthrough the CE# and RP# input stages.

OE# INPUT OUTPUT ENABLE:Enables the devices outputs through the data buffers duringa read cycle. OE# is active low.

WE# INPUT WRITE ENABLE:Controls writes to the Command Register and array blocks.WE# is active low. Addresses and data are latched on the rising edge of the WE#pulse.

RP# INPUT RESET/DEEP POWER-DOWN:Uses three voltage levels (V IL, VIH, and VHH) tocontrol two different functions: reset/deep power-down mode and boot blockunlocking. It is backwards-compatible with the BX/BL/BV products.

When RP# is at logic low, the device is in reset/deep power-down mode,which puts the outputs at High-Z, resets the Write State Machine, and draws

minimum current.

When RP# is at logic high, the device is in standard operation. When RP#transitions from logic-low to logic-high, the device defaults to the read array mode.

When RP# is at VHH, the boot block is unlockedand can be programmed orerased. This overrides any control from the WP# input.


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Table 2. 28F200/002 Pin Descriptions

Symbol Type Name and Function

WP# INPUT WRITE PROTECT:Provides a method for unlocking the boot block in a systemwithout a 12 V supply.

When WP# is at logic low, the boot block is locked, preventing program anderase operations to the boot block. If a program or erase operation is attemptedon the boot block when WP# is low, the corresponding status bit (bit 4 for

program, bit 5 for erase) will be set in the status register to indicate the operationfailed.

When WP# is at logic high, the boot block is unlocked and can beprogrammed or erased.

NOTE: This feature is overridden and the boot block unlocked when RP# is atVHH. See Section 3.4 for details on write protection.

BYTE# INPUT BYTE# ENABLE:Not available on28F002B. Controls whether the deviceoperates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pinmust be controlled at CMOS levels to meet the CMOS current specification in thestandby mode.

When BYTE# is at logic low, the byte-wide mode is enabled , where data isread and programmed on DQ0DQ7and DQ15/A1becomes the lowest orderaddress that decodes between the upper and lower byte. DQ8DQ14are tri-statedduring the byte-wide mode.

When BYTE# is at logic high, the word-wide mode is enabled, where data isread and programmed on DQ0DQ15.

VCC DEVICE POWER SUPPLY: 5.0 V 10%, 3.3 V 0.3 V, 2.7 V3.6 V (BE/CEonly)

VPP PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks orprogramming data in each block, a voltage either of 5 V 10% or 12 V 5% mustbe applied to this pin. When VPP< VPPLKall blocks are locked and protectedagainst Program and Erase commands.

GND GROUND:For all internal circuitry.

NC NO CONNECT:Pin may be driven or left floating.


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2.0 PRODUCT DESCRIPTION

2.1 Memory Blocking Organization

This product family features an asymmetrically-blocked architecture providing system memoryintegration. Each erase block can be erasedindependently of the others up to 100,000 times for

commercial temperature or up to 10,000 times forextended temperature. The block sizes have beenchosen to optimize their functionality for commonapplications of nonvolatile storage. The combinationof block sizes in the boot block architecture allowthe integration of several memories into a singlechip. For the address locations of the blocks, seethe memory maps in Figures4 and 5.

2.1.1 ONE 16-KB BOOT BLOCK

The boot block is intended to replace a dedicatedboot PROM in a microprocessor or microcontroller-based system. The 16-Kbyte (16,384 bytes) bootblock is located at either the top (denoted by -Tsuffix) or the bottom (-B suffix) of the address map

to accommodate different microprocessor protocolsfor boot code location. This boot block featureshardware controllable write-protection to protect thecrucial microprocessor boot code from accidentalmodification. The protection of the boot block iscontrolled using a combination of the VPP, RP#, andWP# pins, as is detailed in Section 3.4.

2.1.2 TWO 8-KB PARAMETER BLOCKS

The boot block architecture includes parameterblocks to facilitate storage of frequently updatedsmall parameters that would normally require anEEPROM. By using software techniques, the byte-rewrite functionality of EEPROMs can be emulated.These techniques are detailed in Intels applicationnote AP-604, Using Intels Boot Block Flash

Memory Parameter Blocks to Replace EEPROM.Each boot block component contains two parameterblocks of 8 Kbytes (8,192 bytes) each. Theparameter blocks are not write-protectable.

2.1.3 ONE 96-KB + ONE 128-KB MAINBLOCK

After the allocation of address space to the bootand parameter blocks, the remainder is divided intomain blocks for data or code storage. Each 2-Mbitdevice contains one 96-Kbyte (98,304 byte) blockand one 128-Kbyte (131,072 byte) block. See thememory maps for each device for more information.


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28F200-B

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK


96-Kbyte MAIN BLOCK

00000H

0FFFFH10000H

1BFFFH1C000H

1CFFFH1D000H

1DFFFH1E000H

1FFFFH

28F200-T



16-Kbyte BOOT BLOCK


96-Kbyte MAIN BLOCK

1FFFFH

10000H0FFFFH

04000H

03FFFH03000H02FFFH

02000H01FFFH

00000H0530_07

NOTE: In x8 operation, the least significant system address should be connected to A-1. Memory maps are shown for x16operation.

Figure 7. Word-Wide x16-Mode Memory Maps



16-Kbyte BOOT BLOCK


96-Kbyte MAIN BLOCK

3FFFFH

20000H

1FFFFH

08000H07FFFH06000H05FFFH

04000H03FFFH

00000H



16-Kbyte BOOT BLOCK


96-Kbyte MAIN BLOCK

00000H

1FFFFH20000H

37FFFH38000H

39FFFH3A000H

3BFFFH3C000H

3FFFFH

28F002-T 28F002-B

0530_08

NOTE: These memory maps apply to the 28F002B or the 28F200 in x8 mode.

Figure 8. Byte-Wide x8-Mode Memory Maps


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3.0 PRODUCT FAMILY PRINCIPLESOF OPERATION

Flash memory combines EPROM functionality within-circuit electrical program and erase. The bootblock flash family utilizes a Command UserInterface (CUI) and automated algorithms tosimplify program and erase operations. The CUIallows for 100% TTL-level control inputs, fixed

power supplies during erasure and programming,and maximum EPROM compatibility.

When VPP< VPPLK, the device will only successfullyexecute the following commands: Read Array,Read Status Register, Clear Status Register andintelligent identifier mode. The device providesstandard EPROM read, standby and output disableoperations. Manufacturer identification and deviceidentification data can be accessed through the CUIor through the standard EPROM A9 high voltageaccess (VID) for PROM programming equipment.

The same EPROM read, standby and outputdisable functions are available when 5 V or 12 V isapplied to the VPPpin. In addition, 5 V or 12 V onVPP allows program and erase of the device. All

functions associated with altering memory contents:Program and Erase, Intelligent Identifier Read, andRead Status are accessed via the CUI.

The internal Write State Machine (WSM) completelyautomates program and erase, beginning operationsignaled by the CUI and reporting status throughthe status register. The CUI handles the WE#interface to the data and address latches, as wellas system status requests during WSM operation.

3.1 Bus Operations

Flash memory reads, erases and programs in-system via the local CPU. All bus cycles to or fromthe flash memory conform to standard

microprocessor bus cycles. These bus operationsare summarized in Tables 3 and 4.

3.2 Read Operations

3.2.1 READ ARRAY

When RP# transitions from VIL (reset) to VIH, thedevice will be in the read array mode and willrespond to the read control inputs (CE#, addressinputs, and OE#) without any commands being

written to the CUI.

When the device is in the read array mode, fivecontrol signals must be controlled to obtain data atthe outputs.

RP# must be logic high (VIH)

WE# must be logic high (VIH)

BYTE# must be logic high or logic low

CE# must be logic low (VIL)

OE must be logic low (VIL)

In addition, the address of the desired location mustbe applied to the address pins. Refer to Figures 15and16 for the exact sequence and timing of these

signals.

If the device is not in read array mode, as would bethe case after a program or erase operation, theRead Mode command (FFH) must be written to theCUI before reads can take place.

During system design, consideration should betaken to ensure address and control inputs meetrequired input slew rates of


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Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH)

Mode Notes RP# CE# OE# WE# A9 A0 VPP DQ015

Read 1,2,3 VIH VIL VIL VIH X X X DOUT

Output Disable VIH VIL VIH VIH X X X High Z

Standby VIH VIH X X X X X High Z

Deep Power-Down 9 VIL X X X X X X High Z

Intelligent Identifier(Mfr)

4 VIH VIL VIL VIH VID VIL X 0089 H

Intelligent Identifier(Device)

4,5 VIH VIL VIL VIH VID VIH X SeeTable 5

Write 6,7,8 VIH VIL VIH VIL X X X DIN

Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE# OE# WE# A9 A0 A1 VPP DQ07 DQ814

Read 1,2,3 VIH VIL VIL VIH X X X X DOUT High Z

Output

Disable

VIH VIL VIH VIH X X X X High Z High Z

Standby VIH VIH X X X X X X High Z High Z

Deep Power-Down

9 VIL X X X X X X X High Z High Z

IntelligentIdentifier (Mfr)

4 VIH VIL VIL VIH VID VIL X X 89H High Z

IntelligentIdentifier(Device)

4,5 VIH VIL VIL VIH VID VIH X X SeeTable

5

High Z

Write 6,7,8 VIH VIL VIH VIL X X X X DIN High Z

NOTES:

1. Refer to DC Characteristics.

2. X can be VIL

, VIH

for control pins and addresses, VPPLK

or VPPH

for VPP

.

3. See DC Characteristicsfor VPPLK, VPPH1, VPPH2, VHH, VIDvoltages.

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1A16= X, A1A17= X.

5. See Table 5 for device IDs.

6. Refer to Table 7 for valid DINduring a write operation.

7. Command writes for block erase or word/byte program are only executed when VPP= VPPH1or VPPH2.

8. To program or erase the boot block, hold RP# at VHHor WP# at VIH. See Section 3.4.

9. RP# must be at GND 0.2 Vto meet the maximum deep power-down current specified.


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3.2.2 INTELLIGENT IDENTIFIERS

To read the manufacturer and device codes, thedevice must be in intelligent identifier read mode,which can be reached using two methods: bywriting the Intelligent Identifier command (90H) orby taking the A9 pin to VID. Once in intelligentidentifier read mode, A0 = 0 outputs the manu-

facturers identification code and A0= 1 outputs thedevice code. In byte-wide mode, only the lower byteof the above signatures is read (DQ15/A1 is adont care in this mode). See Table 5 for productsignatures. To return to read array mode, write aRead Array command (FFH).

Table 5. Intelligent Identifier Table

Product Mfr. ID Device ID

-T(Top Boot)

-B(Bottom Boot)

28F200 0089 H 2274 H 2275 H

28F002 89 H 7C H 7D H

3.3 Write Operations

3.3.1 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) is the interfacebetween the microprocessor and the internal chipcontroller. Commands are written to the CUI using

standard microprocessor write timings. Theavailable commands are Read Array, ReadIntelligent Identifier, Read Status Register, ClearStatus Register, Erase and Program (summarizedin Tables 6 and 7). The three read modes are readarray, intelligent identifier read, and status registerread. For Program or Erase commands, the CUIinforms the Write State Machine (WSM) that aprogram or erase has been requested. During theexecution of a Program command, the WSM willcontrol the programming sequences and the CUIwillonly respond to status reads. During an erasecycle, the CUI will respond to status reads anderase suspend. After the WSM has completed itstask, it will set the WSM Status bit to a 1 (ready),which indicates that the CUI can respond to its fullcommand set. Note that after the WSM has

returned control to the CUI, the CUI will stay in thecurrent command state until it receives anothercommand.

3.3.1.1 Command Function Description

Device operations are selected by writing specificcommands into the CUI. Tables 6 and7define theavailable commands.


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Table 6. Command Codes and Descriptions

Code Device Mode Description

00 Invalid/ Reserved

Unassigned commands that should not be used. Intel reserves the right to redefinethese codes for future functions.

FF Read Array Places the device in read array mode, so that array data will be output on the datapins.

40 ProgramSet-Up

Sets the CUI into a state such that the next write will latch the Address and Dataregisters on the rising edge and begin the program algorithm. The device thendefaults to the read status mode, where the device outputs status register datawhen OE# is enabled. To read the array, issue a Read Array command.

To cancel a program operation after issuing a Program Set-Up command, write all1s (FFH for x8, FFFFH for x16)to the CUI. This will return to read status registermode after a standard program time without modifying array contents. If a programoperation has already been initiated to the WSM this command cannot cancel thatoperation in progress.

10 AlternateProg Set-Up

(See 40H/Program Set-Up)

20 EraseSet-Up

Prepares the CUI for the Erase Confirm command. If the next command is not anErase Confirm command, then the CUI will set both the Program Status (SR.4) andErase Status (SR.5) bits of the status register to a 1, place the device into the

read status register state, and wait for another command without modifying arraycontents. This can be used to cancel an erase operation after the Erase Set-Upcommand has been issued. If an operation has already been initiated to the WSMthis can not cancel that operation in progress.

D0 EraseResume/

EraseConfirm

If the previous command was an Erase Set-Up command, then the CUI will latchaddress and data, and begin erasing the block indicated on the address pins.During erase, the device will respond only to the Read Status Register and EraseSuspend commands and will output status register data when OE# is toggled low.Status register data is updated by toggling either OE# or CE# low.

B0 EraseSuspend

Valid only while an erase operation is in progress and will be ignored in any othercircumstance. Issuing this command will begin to suspend erase operation. Thestatus register will indicate when the device reaches erase suspend mode. In thismode, the CUI will respond only to the Read Array, Read Status Register, andErase Resume commands and the WSM will also set the WSM Status bit to a 1(ready). The WSM will continue to idle in the SUSPEND state, regardless of thestate of all input control pins except RP#, which will immediately shut down the

WSM and the remainder of the chip, if i t is made active. During a suspendoperation, the data and address latches will remain closed, but the address padsare able to drive the address into the read path. See Section 3.3.4.1.

70 Read StatusRegister

Puts the device into the read status register mode, so that reading the deviceoutputs status register data, regardless of the address presented to the device.The device automatically enters this mode after program or erase has completed.This is one of the two commands that is executable while the WSM is operating.See Section 3.3.2.


19/55


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Table 8. Status Register Bit Definition

WSMS ESS ES DWS VPPS R R R

7 6 5 4 3 2 1 0

NOTES:

SR.7 = WRITE STATE MACHINE STATUS

1 = Ready (WSMS)

0 = Busy

Check Write State Machine bit first to determine

Word/Byte program or Block Erase completion,

before checking Program or Erase Status bits.

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase In Progress/Completed

When Erase Suspend is issued, WSM halts

execution and sets both WSMS and ESS bits to

1. ESS bit remains set to 1 until an Erase

Resume command is issued.

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erasure

0 = Successful Block Erase

When this bit is set to 1, WSM has applied the

max number of erase pulses to the block and is

still unable to verify successful block erasure.

SR.4 = PROGRAM STATUS (DWS)

1 = Error in Byte/Word Program

0 = Successful Byte/Word Program

When this bit is set to 1, WSM has attempted

but failed to program a byte or word.

SR.3 = VPPSTATUS (VPPS)

1 = VPPLow Detect, Operation Abort0 = VPPOK

The VPPStatus bit does not provide continuous

indication of VPPlevel. The WSM interrogates VPPlevel only after the Program or Erase command

sequences have been entered, and informs the

system if VPPhas not been switched on. The VPPStatus bit is not guaranteed to report accurate

feedback between VPPLKand VPPH.

SR.2SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

These bits are reserved for future use and should

be masked out when polling the status register.

3.3.2 STATUS REGISTER

The device status register indicates when aprogram or erase operation is complete, and thesuccess or failure of that operation. To read thestatus register write the Read Status (70H)

command to the CUI. This causes all subsequentread operations to output data from the statusregister until another command is written to theCUI. To return to reading from the array, issue aRead Array (FFH) command.

The status register bits are output on DQ0DQ7, inboth byte-wide (x8) or word-wide (x16) mode. In theword-wide mode the upper byte, DQ8DQ15,outputs 00H during a Read Status command. In thebyte-wide mode, DQ8DQ14 are tri-stated andDQ15/A1retains the low order address function.

Important: The contents of the status registerare latched on the falling edge of OE# or CE#,whichever occurs last in the read cycle. Thisprevents possible bus errors which might occur ifstatus register contents change while being read.

CE# or OE# must be toggled with each subsequentstatus read, or the status register will not indicatecompletion of a program or erase operation.

When the WSM is active, the SR.7 register willindicate the status of the WSM, and will also holdthe bits indicating whether or not the WSM wassuccessful in performing the desired operation.


21/55



3.3.2.1 Clearing the Status Register

The WSM sets status bits 3 through 7 to 1, andclears bits 6 and 7 to 0, but cannot clear statusbits 3 through 5 to 0. Bits 3 through 5 can only becleared by the controlling CPU through the use ofthe Clear Status Register (50H) command, becausethese bits indicate various error conditions. Byallowing the system software to control the resetting

of these bits, several operations may be performed(such as cumulatively programming several bytesor erasing multiple blocks in sequence) beforereading the status register to determine if an erroroccurred during that series. Clear the status registerbefore beginning another command or sequence.Note, again, that a Read Array command must beissued before data can be read from the memory orintelligent identifier.

3.3.3 PROGRAM MODE

Programming is executed using a two-writesequence. The Program Set-Up command is writtento the CUI followed by a second write whichspecifies the address and data to be programmed.The WSM will execute a sequence of internallytimed events to:

1. Program the desired bits of the addressed

memory word or byte.

2. Verify that the desired bits are sufficiently

programmed.

Programming of the memory results in specific bitswithin a byte or word being changed to a 0.

If the user attempts to program 1s, there will be nochange of the memory cell content and no erroroccurs.

The status register indicates programming status:while the program sequence is executing, bit 7 ofthe status register is a 0. The status register canbe polled by toggling either CE# or OE#. Whileprogramming, the only valid command is ReadStatus Register.

When programming is complete, the program statusbits should be checked. If the programmingoperation was unsuccessful, bit 4 of the statusregister is set to a 1 to indicate a Program Failure.If bit 3 is set to a 1, then V PP was not withinacceptable limits, and the WSM did not execute theprogramming sequence.

The status register should be cleared beforeattempting the next operation. Any CUI instructioncan follow after programming is completed;however, reads from the memory array or intelligentidentifier cannot be accomplished until the CUI isgiven the appropriate command.

3.3.4 ERASE MODE

To erase a block, write the Erase Set-Up and EraseConfirm commands to the CUI, along with theaddresses identifying the block to be erased. Theseaddresses are latched internally when the EraseConfirm command is issued. Block erasure resultsin all bits within the block being set to 1. Only oneblock can be erased at a time.

The WSM will execute a sequence of internallytimed events to:

1. Program all bits within the block to 0.

2. Verify that all bits within the block are

sufficiently programmed to 0.

3. Erase all bits within the block to 1.

4. Verify that all bits within the block aresufficiently erased.

While the erase sequence is executing, bit 7 of thestatus register is a 0.

When the status register indicates that erasure iscomplete, check the erase status bit to verify thatthe erase operation was successful. If the eraseoperation was unsuccessful, bit 5 of the statusregister will be set to a 1, indicating an EraseFailure. If VPPwas not within acceptable limits afterthe Erase Confirm command is issued, the WSMwill not execute an erase sequence; instead, bit 5 ofthe status register is set to a 1 to indicate anErase Failure, and bit 3 is set to a 1 to identify thatVPPsupply voltage was not within acceptable limits.

Clear the status register before attempting the nextoperation. Any CUI instruction can follow aftererasure is completed; however, reads from thememory array, status register, or intelligentidentifier cannot be accomplished until the CUI isgiven the Read Array command.


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3.3.4.1 Suspending and Resuming Erase

Since an erase operation requires on the order ofseconds to complete, an Erase Suspend commandis provided to allow erase-sequence interruption inorder to read data from another block of thememory. Once the erase sequence is started,writing the Erase Suspend command to the CUIrequests that the WSM pause the erase sequence

at a predetermined point in the erase algorithm. Thestatus register will indicate if/when the eraseoperation has been suspended.

At this point, a Read Array command can be writtento the CUI in order to read data from blocks otherthan that which is being suspended. The only othervalid command at this time is the Erase Resumecommand or Read Status Register command.

During erase suspend mode, the chip can go into apseudo-standby mode by taking CE# to VIH, whichreduces active current draw.

To resume the erase operation, enable the chip bytaking CE# to VIL, then issuing the Erase Resumecommand, which continues the erase sequence to

completion. As with the end of a standard eraseoperation, the status register must be read, cleared,and the next instruction issued in order to continue.

3.4 Boot Block Locking

The boot block family architecture features ahardware-lockable boot block so that the kernelcode for the system can be kept secure while theparameter and main blocks are programmed anderased independently as necessary. Only the bootblock can be locked independently from the otherblocks. The truth table, Table 9, clearly defines thewrite protection methods.

3.4.1 VPP= VILFOR COMPLETEPROTECTION

For complete write protection of all blocks in theflash device, the VPP programming voltage can beheld low. When VPPis below VPPLK, any program orerase operation will result in a error in the statusregister.

3.4.2 WP# = VILFOR BOOT BLOCKLOCKING

When WP# = VIL, the boot block is locked and anyprogram or erase operation to the boot block willresult in an error in the status register. All otherblocks remain unlocked in this condition and can beprogrammed or erased normally. Note that thisfeature is overridden and the boot block unlocked

when RP# = VHH.

3.4.3 RP# = VHHOR WP# = VIHFOR BOOTBLOCK UNLOCKING

Two methods can be used to unlock the boot block:

1. WP# = VIH

2. RP# = VHH

If both or either of these two conditions are met, theboot block will be unlocked and can beprogrammed or erased.

3.4.4 UPGRADE NOTE FOR 8-MBIT44-PSOP PACKAGE

If upgradability to 8 Mbit is required, note that the8-Mbit in the 44-PSOP does not have a WP#because no pins were available for the 8-Mbitupgrade address. Thus, in this density-packagecombination only, VHH(12 V) on RP# is required tounlock the boot block. Unlocking with a logic-levelsignal is not possible. If this functionality isrequired, and 12 V is not available, consider usingthe 48-TSOP package, which has a WP# pin andcan be unlocked with a logic-level signal. All otherdensity-package combinations have WP# pins.

Table 9. Write Protection Truth Table

VPP RP# WP# Write ProtectionProvided

VIL X X All Blocks Locked

VPPLK VIL X All Blocks Locked(Reset)

VPPLK VHH X All Blocks Unlocked

VPPLK VIH VIL Boot Block Locked

VPPLK VIH VIH All Blocks Unlocked


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SR.7 = 1?

NO

YES

Start

Write 40H,Word/Byte Address

Write Word/ByteData/Address

Full StatusCheck if Desired

Word/Byte Program

Complete

FULL STATUS CHECK PROCEDURE

1

0

Read Status RegisterData (See Above)

1

0

ReadStatus Register

VPPRange Error

BusOperation

Command Comments

Standby

Standby

Check SR.31 = VPPLow Detect

SR.3 MUST be cleared, if set during a program attempt, before furtherattempts are allowed by the Write State Machine.

SR.4 is only cleared by the Clear Status Register Command, in caseswhere multiple bytes are programmed before full status is checked.

If error is detected, clear the Status Register before attempting retry or other error recovery.

BusOperation

Command Comments

Write

Write

SetupProgram

Data = Data to ProgramAddr = Location to Program

Read

Data = 40HAddr = Word/Byte to Program

Check SR.71 = WSM Ready0 = WSM Busy

Repeat for subsequent word/byte program operations.SR Full Status Check can be done after each word/byte program,

or after a sequence of word/byte programs.Write FFH after the last program operation to reset device toread array mode.

Standby

SR.3 =

SR.4 =Word/Byte Program

Error

Word/Byte ProgramSuccessful

Check SR.41 = Word/Byte Program Error

Program

Status Register Data Toggle CE#or OE# to Update SRD

0530_09

Figure 9. Automated Word/Byte Programming Flowchart


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SR.7 =

0

1

Start

Write 20H,Block Address

Write D0H andBlock Address

Full StatusCheck if Desired

Block EraseComplete

FULL STATUS CHECK PROCEDURE

1

0

Read Status RegisterData (See Above)

1

0

Read StatusRegister

VPPRange Error

SuspendErase

Suspend EraseLoop

YES

NO

1

0

Command SequenceError

SR.3 =

SR.5 =

SR.4,5 =

Block Erase Error

BusOperation Command Comments

Standby

Check SR.4,5Both 1 = Command Sequence Error

Standby

Check SR.31 = VPPLow Detect

SR.3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine.

SR.5 is only cleared by the Clear Status Register Command, incases where multiple blocks are erase before full status is checked.

If error is detected, clear the Status Register before attempting retry or other error recovery.

Check SR.51 = Block Erase Error

Standby

BusOperation

Command Comments

Write

Write

Erase Setup

Read

Data = 20HAddr = Within Block to Be Erased


Repeat for subsequent block erasures.Full Status Check can be done after each block erase, or after a

sequence of block erasures.Write FFH after the last operation to reset device to read array mode.

Status Register Data Toggle CE#or OE# to Update Status Register

Standby

Erase

Confirm

Data = D0H

Addr = Within Block to Be Erased

Block Erase Successful

0530_10

Figure 10. Automated Block Erase Flowchart


25/55



Start

Write B0H

Read Status Register

No

Comments

Data = B0HAddr = X

Data = FFHAddr = X

SR.7 =

SR.6 =

1

Write FFH

Read Array Data

Erase Completed

Done

Reading

Yes

Write FFHWrite D0H

Erase Resumed Read Array Data

0

1

Read array data from blockother than the one beingprogrammed.

Status Register Data ToggleCE# or OE# to Update StatusRegister DataAddr = X


Check SR.61 = Erase Suspended0 = Erase Completed

Data = D0HAddr = X

BusOperation

Write

Write

Read

Read

Standby

Standby

Write

Command

ProgramSuspend

Read Array

ProgramResume

0

Write 70H Status Register Data ToggleCE# or OE# to Update StatusRegister DataAddr = X

Write

Write

Write

Read

Read

Standby

Standby

Write

Data=70HAddr=X

Command

ProgramSuspend

Read Array

ProgramResume

Erase Suspend

Read Status

Read Array

Erase Resume

0530_11

Figure 11. Erase Suspend/Resume Flowchart


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3.5 Power Consumption

3.5.1 ACTIVE POWER

With CE# at a logic-low level and RP# at a logic-high level, the device is placed in the active mode.Refer to the DC Characteristics table for ICCcurrentvalues.

3.5.2 AUTOMATIC POWER SAVINGS (APS)

Automatic Power Savings (APS) provides low-power operation during active mode. PowerReduction Control (PRC) circuitry allows the deviceto put itself into a low current state when not beingaccessed. After data is read from the memoryarray, PRC logic controls the devices powerconsumption by entering the APS mode wheretypical ICC current is less than 1 mA. The devicestays in this static state with outputs valid until anew location is read.

3.5.3 STANDBY POWER

With CE# at a logic-high level (VIH), and the CUI inread mode, the memory is placed in standby mode,which disables much of the devices circuitry andsubstantially reduces power consumption. Outputs(DQ0DQ15 or DQ0DQ7) are placed in a high-impedance state independent of the status of theOE# signal. When CE# is at logic-high level duringerase or program operations, the device willcontinue to perform the operation and consumecorresponding active power until the operation iscompleted.

3.5.4 DEEP POWER-DOWN MODE

The SmartVoltage boot block family supports a lowtypical ICC in deep power-down mode, which turns

off all circuits to save power. This mode is activatedby the RP# pin when it is at a logic-low (GND 0.2 V).

NOTE

Note: BYTE# pin must be at CMOS levels tomeet the ICCDspecification.

During read modes, the RP# pin going low de-selects the memory and places the output drivers ina high impedance state. Recovery from the deeppower-down state, requires a minimum access timeof tPHQV(see AC Characteristicstable).

During erase or program modes, RP# low will aborteither erase or program operations, but the memorycontents are no longer valid as the data has beencorrupted by the RP# function. As in the read modeabove, all internal circuitry is turned off to achievethe power savings.

RP# transitions to VIL, or turning power off to thedevice will clear the status register.

3.6 Power-Up/Down Operation

The device is protected against accidental blockerasure or programming during power transitions.Power supply sequencing is not required, since thedevice is indifferent as to which power supply, VPPor VCC, powers-up first. The CUI is reset to the readmode after power-up, but the system must dropCE# low or present a new address to ensure validdata at the outputs.

A system designer must guard against spuriouswrites when VCCvoltages are above VLKOand VPPis active. Since both WE# and CE# must be low fora command write, driving either signal to V IH will

inhibit writes to the device. The CUI architectureprovides additional protection since alteration ofmemory contents can only occur after successfulcompletion of the two-step command sequences.The device is also disabled until RP# is brought toVIH, regardless of the state of its control inputs. Byholding the device in reset (RP# connected tosystem PowerGood) during power-up/down, invalidbus conditions during power-up can be masked,providing yet another level of memory protection.

3.6.1 RP# CONNECTED TO SYSTEMRESET

The use of RP# during system reset is importantwith automated program/erase devices because the

system expects to read from the flash memorywhen it comes out of reset. If a CPU reset occurswithout a flash memory reset, proper CPUinitialization would not occur because the flashmemory may be providing status informationinstead of array data. Intels Flash memories allowproper CPU initialization following a system resetby connecting the RP# pin to the same RESET#signal that resets the system CPU.


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3.6.2 VCC, VPPAND RP# TRANSITIONS

The CUI latches commands as issued by systemsoftware and is not altered by VPP or CE#transitions or WSM actions. Its default state uponpower-up, after exit from deep power-down mode,or after VCC transitions above VLKO (lockoutvoltage), is read array mode.

After any word/byte program or block eraseoperation is complete and even after VPPtransitionsdown to VPPLK, the CUI must be reset to read arraymode via the Read Array command if accesses tothe flash memory are desired.

Please refer to Intels application note AP-617Additional Flash Data Protection Using VPP, RP#,and WP# for a circuit-level description of how toimplement the protection discussed in Section 3.6.

3.7 Power Supply Decoupling

Flash memorys power switching characteristicsrequire careful device decoupling methods. Systemdesigners should consider three supply current

issues:1. Standby current levels (ICCS)

2. Active current levels (ICCR)

3. Transient peaks produced by falling and rising

edges of CE#.

Transient current magnitudes depend on the deviceoutputs capacitive and inductive loading. Two-linecontrol and proper decoupling capacitor selectionwill suppress these transient voltage peaks. Eachflash device should have a 0.1 F ceramiccapacitor connected between each VCCand GND,and between its VPP and GND. These high-frequency, inherently low-inductance capacitorsshould be placed as close as possible to the

package leads.

3.7.1 VPPTRACE ON PRINTED CIRCUITBOARDS

Designing for in-system programming of the flashmemory requires special consideration of the VPPpower supply trace by the printed circuit boarddesigner. The VPP pin supplies the flash memorycells current for programming and erasing. Oneshould use similar trace widths and layoutconsiderations given to the VCCpower supply trace.Adequate VPP supply traces, and decouplingcapacitors placed adjacent to the component, willdecrease spikes and overshoots.

NOTE:

Table headings in the DC and AC characteristics tables (i.e., BV-60, BV-80, BV-120, TBV-80, TBE-120) refer to the specific products listed below. See Section 5.0 for more information on productnaming and line items.

Abbreviation Applicable Product Names

BV-60 E28F002BV-T60, E28F002BV-B60, PA28F200BV-T60, PA28F200BV-B60,E28F200CV-T60, E28F200CV-B60, E28F200BV-T60, E28F200BV-B60

BV-80 E28F002BV-T80, E28F002BV-B80, PA28F200BV-T80, PA28F200BV-B80,E28F200CV-T80, E28F200CV-B80, E28F200BV-T80, E28F200BV-B80

BV-120 E28F002BV-T120, E28F002BV-B120, PA28F200BV-T120, PA28F200BV-B120

TBV-80 TE28F002BV-T80, TE28F002BV-B80, TB28F200BV-T80, TB28F200BV-B80,TE28F200CV-T80, TE28F200CV-B80, TE28F200BV-T80, TE28F200BV-B80


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4.0 ELECTRICAL SPECIFICATIONS

4.1 Absolute Maximum Ratings*

Commercial Operating Temperature

During Read .............................. 0 C to +70 C

During Block Erase

and Word/Byte Program ............ 0 C to +70 C

Temperature Under Bias ....... 10 C to +80 C

Extended Operating Temperature

During Read .......................... 40 C to +85 C

During Block Eraseand Word/Byte Program ........ 40 C to +85 C

Temperature Under Bias ....... 40 C to +85 C

Storage Temperature................. 65 C to +125 C

Voltage on Any Pin

(except VCC, VPP, A9and RP#)with Respect to GND........... 2.0 V to +7.0 V(2)

Voltage on Pin RP# or Pin A9with Respect to GND.......2.0 V to +13.5 V(2,3)

VPPProgram Voltage with Respectto GND during Block Erase

and Word/Byte Program .. 2.0 V to +14.0 V(2,3)

VCCSupply Voltagewith Respect to GND........... 2.0 V to +7.0 V(2)

Output Short Circuit Current....................100 mA (4)

NOTICE: This datasheet contains preliminary information on

new products in production. Do not finalize a design with

this information.Revised information will be published when

the product is available. Verify with your local Intel Sales

office that you have the latest datasheet before finalizing a

design.

* WARNING: Stressing the device beyond the "Absolute

Maximum Ratings" may cause permanent damage. These

are stress ratings only. Operation beyond the "OperatingConditions" is not recommended and extended exposure

beyond the "Operating Conditions" may effect device

reliability.

NOTES:

1. Operating temperature is for commercial productdefined by this specification.

2. Minimum DC voltage is0.5 V on input/output pins.During transitions, this level may undershoot to 2.0 Vfor periods


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4.2.1 APPLYING VCCVOLTAGES

When applying VCC voltage to the device, a delaymay be required before initiating device operation,depending on the VCC ramp rate. If VCC rampsslower than 1V/100 s (0.01 V/s) then no delay is

required. If VCCramps faster than 1V/100 s (0.01V/s), then a delay of 2 s is required beforeinitiating device operation. RP# = GND isrecommended during power-up to protect againstspurious write signals when VCC is between VLKOand VCCMIN.

VCCRamp Rate Required Timing

1V/100 s No delay required.

> 1V/100 s A delay time of 2 s is required before any device operation is initiated, including readoperations, command writes, program operations, and erase operations. This delayismeasured beginning from the time VCCreaches VCCMIN(3.0 V for 3.3 0.3 V operation;and 4.5 V for 5 V operation).

NOTES:

1. These requirements must be strictly followed to guarantee all other read and write specifications.

2. To switch between 3.3 V and 5 V operation, the system should first transition VCCfrom the existing voltage range to GND,and then to the new voltage. Any time the VCCsupply drops below VCCMIN, the chip may be reset, aborting any operationspending or in progress.

3. These guidelines must be followed for any VCC transition from GND.

4.3 Capacitance

TA= 25 C, f = 1 MHz

Symbol Parameter Note Typ Max Unit Conditions

CIN Input Capacitance 1 6 8 pF VIN= 0 V

COUT Output Capacitance 1, 2 10 12 pF VOUT= 0 V

NOTES:

1. Sampled, not 100% tested.

2. For the 28F002B, address pin A10follows the COUTcapacitance numbers.


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4.4 DC CharacteristicsCommercial

ProdBV-60BV-80

BV-120

Sym Parameter VCC 3.3 0.3 V 5 V 10% Unit Test Conditions

Note Typ Max Typ Max

IIL Input Load Current 1 1.0 1.0 A VCC= VCCMaxVIN= VCCor GND

ILO Output Leakage Current 1 10 10 AVCC= VCCMax

VIN= VCCor GND

ICCS VCCStandby Current 1,3 0.4 1.5 0.8 2.0 mAVCC= VCCMax

CE# = RP# = BYTE# =

WP# = VIH

60 110 50 130 A VCC= VCCMax

CE# = RP# = VCC

0.2 V

ICCD VCCDeep Power-Down

Current

1 0.2 8 0.2 8 A VCC= VCCMax

VIN= VCCor GND

RP# = GND 0.2 V

ICCR

VCCRead Current for

Word or Byte1,5,6 15 30 50 60 mA CMOS INPUTS

VCC= VCCMax

CE# = GND, OE# = VCC

f = 10 MHz (5 V),

5 MHz (3.3 V)

IOUT= 0 mA, Inputs =

GND 0.2 V or VCC 0.2 V

15 30 55 65 mA TTL INPUTS

VCC= VCCMax

CE# = VIL, OE# = VIHf = 10 MHz (5 V),

5 MHz (3.3 V)

IOUT= 0 mA, Inputs =

VILor VIH

ICCW VCCProgram Current forWord or Byte

1,4 13 30 30 50 mA VPP= VPPH1 (at 5 V)Program in Progress

10 25 30 45 mA VPP= VPPH2 (at 12 V)

Program in Progress

ICCE VCCErase Current 1,4 13 30 18 35 mAVPP= VPPH1 (at 5 V)

Block Erase in Progress

10 25 18 30 mA VPP = VPPH2 (at 12 V)



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4.4 DC CharacteristicsCommercial (Continued)

ProdBV-60BV-80

BV-120


Note Typ Max Typ Max

ICCES VCCErase SuspendCurrent 1,2 3 8.0 5 10 mA CE# = VIH

Block Erase Suspend

IPPS VPPStandby Current 1 0.5 15 0.5 10 A VPP < VPPH2

IPPDVPPDeep Power-Down

Current1 0.2 5.0 0.2 5.0 A RP# = GND 0.2 V

IPPR VPPRead Current 1 50 200 30 200 A VPPVPPH2

IPPW VPPProgram Current for

Word or Byte

1,4 13 30 13 25 mA VPP= VPPH1 (at 5 V)

Program in Progress

8 25 8 20 VPP= VPPH2 (at 12 V)

Program in Progress

IPPE VPPErase Current 1,4 13 30 10 20 mAVPP= VPPH1 (at 5 V)


8 25 5 15 VPP= VPPH2 (at 12 V)Block Erase in Progress

IPPESVPPErase

Suspend Current1 50 200 30 200 A VPP= VPPH

Block Erase Suspend in

Progress

IRP# RP# Boot Block Unlock

Current

1,4 500 500 A RP# = VHH

IIDA9Intelligent

Identifier Current1,4 500 500 A A9= VID


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4.4 DC CharacteristicsCommercial (Continued)

ProdBV-60BV-80

BV-120


Note Min Max Min Max

VID A9Intelligent IdentifierVoltage

11.4 12.6 11.4 12.6 V

VIL Input Low Voltage 0.5 0.8 0.5 0.8 V

VIH Input High Voltage 2.0VCC+

0.5V2.0 VCC+

0.5VV

VOL Output Low Voltage 0.45 0.45 VVCC= VCCMin

IOL= 5.8 mA

VOH1 Output High Voltage (TTL) 2.4 2.4 VVCC= VCCMin

IOH= 2.5 mA

VOH2 Output High Voltage (CMOS)0.85 VCC

0.85 VCC

V VCC= VCCMin

IOH= 2.5 mA

VCC0.4V

VCC0.4V

V VCC= VCCMin

IOH= 100 A

VPPLK VPPLock-Out Voltage 3 0.0 1.5 0.0 1.5 V Total Write Protect

VPPH1 VPP(Prog/Erase Operations) 4.5 5.5 4.5 5.5 V VPPat 5 V

VPPH2 VPP(Prog/Erase Operations) 11.4 12.6 11.4 12.6 V VPPat 12 V

VLKO VCCErase/Prog Lock Voltage 8 2.0 2.0 V

VHH RP# Unlock Voltage 11.4 12.6 11.4 12.6 V Boot Block Unlock

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC= 5.0 V, T = +25 C. These currents are valid for allproduct versions (packages and speeds).

2. ICCESis specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum ofICCESand ICCR.

3. Block erases and word/byte programs are inhibited when VPP= VPPLK, and not guaranteed in the range between VPPH1 andVPPLK.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces ICCRto less than 1 mA typical, in static operation.

6. CMOS Inputs are either VCC 0.2 V or GND 0.2 V. TTL Inputs are either VILor VIH.

7. For the 28F002B, address pin A10follows the COUTcapacitance numbers.

8. For all BV/CV parts, VLKO= 2.0 V for both 3.3 V and 5 V operations.


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TEST POINTSINPUT OUTPUT1.5

3.0

0.0

1.5

NOTE:

AC test inputs are driven at 3.0 V for a logic 1 and 0.0 V for a logic 0. Input timing begins, and output timing ends, at 1.5 V.

Input rise and fall times (10% to 90%)


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4.5 AC CharacteristicsCommercial

Prod BV-60

Sym Parameter VCC 3.3 0.3 V(5) 5 V 5%(6) 5 V 10%(7) Unit

Load 50 pF 30 pF 100 pF

Note Min Max Min Max Min Max

tAVAV Read Cycle Time 110 60 70 ns

tAVQV Address to Output Delay 110 60 70 ns

tELQV CE# to Output Delay 2 110 60 70 ns

tPHQV RP# to Output Delay 0.8 0.45 0.45 s

tGLQV OE# to Output Delay 2 65 30 35 ns

tELQX CE# to Output in Low Z 3 0 0 0 ns

tEHQZ CE# to Output in High Z 3 45 20 20 ns

tGLQX OE# to Output in Low Z 3 0 0 0 ns

tGHQZ OE# to Output in High Z 3 45 20 20 ns

tOH Output Hold from Address,CE#, or OE# Change,Whichever Occurs First

3 0 0 0 ns

tELFLtELFH

CE# Low to BYTE# High orLow

3 0 0 0 ns

tAVFL Address to BYTE# High orLow

3 5 5 5 ns

tFLQVtFHQV

BYTE# to Output Delay 3,4 110 60 70 ns

tFLQZ BYTE# Low to Output inHigh Z

3 45 20 25 ns

tPLPH Reset Pulse Width Low 8 150 60 60 ns

tPLQZ RP# Low to Output High-Z 150 60 60 ns


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4.5 AC CharacteristicsCommercial (Continued)

Prod BV-80 BV-120

Sym Parameter VCC 3.3 0.3V(5) 5V 10%(7) 3.3 0.3V(5) 5V 10%(7) Unit

Load 50 pF 100 pF 50 pF 100 pF

Notes Min Max Min Max Min Max Min Max

tAVAV Read Cycle Time 150 80 180 120 ns

tAVQV Address to Output Delay 150 80 180 120 ns

tELQV CE# to Output Delay 2 150 80 180 120 ns

tPHQV RP# to Output Delay 0.8 0.45 0.8 0.45 s

tGLQV OE# to Output Delay 2 90 40 90 40 ns

tELQX CE# to Output in Low Z 3 0 0 0 0 ns

tEHQZ CE# to Output in High Z 3 45 20 45 25 ns

tGLQX OE# to Output in Low Z 3 0 0 0 0 ns

tGHQZ OE# to Output in High Z 3 45 20 45 20 ns

tOH Output Hold from Address,CE#, or OE# Change,Whichever Occurs First

3 0 0 0 0 ns

tELFLtELFH

CE# Low to BYTE# High orLow

3 0 0 0 0 ns

tAVFL Address to BYTE# High orLow

3 5 5 5 5 ns

tFLQVtFHQV

BYTE# to Output Delay 3,4 150 80 180 120 ns

tFLQZ BYTE# Low to Output inHigh Z

3 60 30 60 30 ns

tPLPH Reset Pulse Width Low 8 150 60 150 60 ns

tPLQZ RP# Low to Output High-Z 150 60 150 60 ns

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.2. OE# may be delayed up to tCEtOEafter the falling edge of CE# without impact on tCE.

3. Sampled, but not 100% tested.

4. tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ15/A1becomes valid.

5. See Test Configuration(Figure 14), 3.3 V Standard Test component values.

6. See Test Configuration(Figure 14), 5 V High-Speed Test component values.

7. See Test Configuration(Figure 14), 5 V Standard Test component values.

8. The specification tPLPHis the minimum time that RP# must be held low in order to product a valid reset of the device.


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Address Stable

Device andAddress Selection

IHV

ILVADDRESSES (A)

IHV

ILV

IHV

ILV

IHV

ILV

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

IHV

ILV

RP#(P)

OLV

OHV

PHQVt

High ZValid Output

DataValid Standby

AVAVt

EHQZt

GHQZt

OHtGLQVt

GLQXtELQVt

ELQXt

AVQVt

High Z

0530_15

Figure 15. AC Waveforms for Read Operations

Address Stable

Device

Address SelectionIHV

ILVADDRESSES (A)

IHV

ILV

IHV

ILV

IHV

ILV

CE# (E)

OE# (G)

BYTE# (F)

DATA (D/Q)(DQ0-DQ7)

OLV

OHVHigh Z Data Output

on DQ0-DQ7

Data

Valid

Standby

AVAVt

EHQZt

GHQZt

AVQVt

High Z

GLQVtELQVt

AVQVt

OHt

Data Outputon DQ0-DQ7

DATA (D/Q)(DQ8-DQ14)

OLV

OHVHigh Z Data Output

on DQ8-DQ14

High Z

(DQ15/A-1)

OLV

OHVHigh Z High ZData Output

on DQ15Address Input

FLQZt

ELQXt

ELFLt

AVFLt

GLQXt

0530_16

Figure 16. BYTE# Timing Diagram for Read Operations


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4.6 AC CharacteristicsWE#-Controlled Write Operations(1)Commercial

Prod BV-60

Sym Parameter VCC 3.3 0.3 V(9) 5 V 5%(10) 5 V 10%(10) Unit

Load 50 pF 30 pF 100 pF

Note Min Max Min Max Min Max

tAVAV Write Cycle Time 110 60 70 ns

tPHWL RP# Setup to WE# Going Low 0.8 0.45 0.45 s

tELWL CE# Setup to WE# Going Low 0 0 0 ns

tPHHWH Boot Block Lock Setup to WE#Going High

6,8 200 100 100 ns

tVPWHVPPSetup to WE# Going High 5,8 200 100 100 ns

tAVWH Address Setup to WE# GoingHigh

3 90 50 50 ns

tDVWH Data Setup to WE# Going High 4 90 50 50 ns

tWLWH WE# Pulse Width 90 50 50 ns

tWHDX Data Hold Time from WE# High 4 0 0 0 ns

tWHAX Address Hold Time from WE#High

3 0 0 0 ns

tWHEH CE# Hold Time from WE# High 0 0 0 ns

tWHWL WE# Pulse Width High 20 10 20 ns

tWHQV1 Duration of Word/Byte Program 2,5 6 6 6 s

tWHQV2 Duration of Erase (Boot) 2,5,6 0.3 0.3 0.3 s

tWHQV3 Duration of Erase (Parameter) 2,5 0.3 0.3 0.3 s

tWHQV4 Duration of Erase (Main) 2,5 0.6 0.6 0.6 s

tQVVL VPPHold from Valid SRD 5,8 0 0 0 ns

tQVPH RP# VHHHold from Valid SRD 6,8 0 0 0 ns

tPHBR Boot-Block Lock Delay 7,8 200 100 100 ns


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4.6 AC CharacteristicsWE#-Controlled Write Operations(1)Commercial(Continued)

Prod BV-80 BV-120

Sym Parameter VCC 3.3 0.3V(9) 5V10%(11) 3.3 0.3V(9) 5V10%(11) Unit

Load 50 pF 100 pF 50 pF 100 pF

Notes Min Max Min Max Min Max Min Max

tAVAV Write Cycle Time 150 80 180 120 ns

tPHWL RP# Setup to WE# GoingLow

0.8 0.45 0.8 0.45 s

tELWL CE# Setup to WE# GoingLow

0 0 0 0 ns

tPHHWH Boot Block Lock Setup toWE# Going High

6,8 200 100 200 100 ns

tVPWHVPPSetup to WE# GoingHigh

5,8 200 100 200 100 ns

tAVWH Address Setup to WE#Going High

3 120 50 150 50 ns

tDVWH Data Setup to WE# Going

High

4 120 50 150 50 ns

tWLWH WE# Pulse Width 120 50 150 50 ns

tWHDX Data Hold Time fromWE# High

4 0 0 0 0 ns

tWHAX Address Hold Time fromWE# High

3 0 0 0 0 ns

tWHEH CE# Hold Time from WE#High

0 0 0 0 ns

tWHWL WE# Pulse Width High 30 30 30 30 ns

tWHQV1 Word/Byte Program Time 2,5 6 6 6 6 s

tWHQV2 Erase Duration (Boot) 2,5,6 0.3 0.3 0.3 0.3 s

tWHQV3 Erase Duration (Param) 2,5 0.3 0.3 0.3 0.3 s

tWHQV4 Erase Duration (Main) 2,5 0.6 0.6 0.6 0.6 s

tQVVL VPPHold from Valid SRD 5,8 0 0 0 0 ns

tQVPHRP# VHHHold from ValidSRD

6,8 0 0 0 0 ns

tPHBR Boot-Block Lock Delay 7,8 200 100 200 100 ns


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NOTES:

1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to ACCharacteristicsduring read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internallywhich includes verify and margining operations.

3. Refer to command definition table for valid AIN. (Table 7)

4. Refer to command definition table for valid DIN. (Table 7)

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).

6. For boot block program/erase, RP# should be held at VHHor WP# should be held at VIHuntil operation completes

successfully.

7. Time tPHBRis required for successful locking of the boot block.

8. Sampled, but not 100% tested.

9. See Test Configuration(Figure 14), 3.3 V Standard Test component values.

10. See Test Configuration(Figure 14), 5 V High-Speed Test component values.

11. See Test Configuration(Figure 14), 5 V Standard Test component values.

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

IHV

ILV

IHV

ILV

IHV

ILV

IHV

ILV

HHV6.5V

ILV

ILV

IND

INA INA

WHEHt

WHWLt

Valid

SRDIND

WHQV1,2,3,4t

PHHWHt

IHV

PHWLt

High ZWHDXt

IHV

ILV

V (V)PP

1 2 3 4 65

PPHV

PPLKVPPH

V 1

2

WP#ILV

IHV

AVAVt AVWHt WHAXt

DVWHtWLWHt

QVPHt

QVVLtVPWHt

IND

ELWLt

NOTES:

1. VCC Power-Up and Standby.

2. Write program or Erase Set-Up Command.

3. Write Valid Address and Data (Program) or Erase Confirm Command.

4. Automated Program or Erase Delay.

5. Read Status Register Data.

6. Write Read Array Command.

0530_17

Figure 17. AC Waveforms for Write Oper

intel 2-mbit smart voltage device guide

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