introduction - itfind role of wet... · introduction: thin wafers have become a basic need for a...

Introduction:

Thin wafers have become a basic need for a wide variety of new microelectronic products. These include power devices, discrete semiconductors, opto-electronic components and integrated circuits for RFID systems. In addition the move to stacked-die assemblies, vertical system integration and new concepts in MEMS devices require wafers to be thinned to < 150µm in thickness.

Mechanical grinding is the most common technique for wafer thinning due to its high thinning rate.1 Commercially available grinding systems typically use a 2-step process that starts with a coarse grinding at very high rates (5 µm/sec) and then a subsequent fine grinding process at a reduced rate ( ≤ 1µm/sec) to remove most of the damage layer that is created by the coarse grinding step. However, there still remains a defect band near the wafer surface. The thickness of this defect zone is dependent upon the grinding conditions. These residual defects can cause stress in the thinned wafer that leads to additional bow and can result in wafer breakage.

Due to the remaining defect layer and surface roughness, an additional thinning process post mechanical grinding is required to provide a reliable thin wafer. This final etch and surface conditioning can be done by CMP, dry etching or wet chemical etching. The most cost effective process is wet etching. Wafers that have been thinned using a final wet etch process on the backside will have less stress compared with mechanical grinding. Wafer breakage will be reduced and after dicing the chips will have fewer cracks and chip-outs.

Depending upon the subsequent processes on the wafer backside, the optimum roughness or smoothness of the surface may vary. For metal deposition, a slight roughness will improve adhesion.2 For wafer bonding, a very smooth surface is required.3

The chemistry most commonly used for isotropic wet etching of silicon is a combination of nitric acid and hydrofluoric acid. The nitric acid acts as an oxidizer to convert the surface into silicon oxide and then the HF etches the oxide. A single wafer spin processor provides the capability to etch one side of the wafer while protecting the other side. For use in a single wafer spin processor, the addition of chemicals with higher viscosities is needed to provide a more uniform etch over the wafer surface. In addition, the ratios of the chemicals can also affect the surface roughness. At high HF and low nitric concentrations the process is very temperature dependent and reaction rate controlled resulting in unstable silicon surfaces. At low HF and high nitric content, smooth polished surfaces result due to the more diffusion limited reaction. The rate of chemical reaction along with the spin process parameters have significant effect on the overall uniformity and surface finish that results from the process.

This paper presents an investigation of some of the key process parameters for providing a very uniform etch and controllable surface finish along with a demonstration of these processes.

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the role of wet etching in silicon wafer thinningLaura Mauer, John Taddei, Ramey Youssef Solid State Equipment Corporation

1 M. Reiche and G. Wagner “Wafer Thinning: Techniques for Ultra-thin Wafers” Advanced Packaging, March 2003 2 S. Drews “Eliminating micro-cracks, crystal dislocations with single-wafer surface conditioning” SST, January 2008 3 P. Garrou, C. Bower, and P. Ramm “Handbook of 3D Integration” Wiley, 2008

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the role of wet etching in silicon wafer thinning

Experimental:

The experiments were conducted on an SSEC 3300 system. There are many process parameters that can be varied during the etching process. For the purpose of this study, a single etch chemistry was utilized. Temperature, flow rate, dispensing profile, spin speed and chamber exhaust are parameters that can be programmed by process step. We wanted to focus on tool parameters that would have the greatest impact on the process and therefore selected temperature, spin speed and flow rate.

The chemistry employed was a mixture of hydrofluoric, nitric, sulfuric and phosphoric acids and is commercially available as Spinetch® D. Recirculation of the chemistry was done using SSEC’s Open or Closed Collection Ring technology.

Figure 1: SSEC Collection Ring and Stream Dispense during etch

A 3-factor, 3-level Box-Behnken response surface design of experiment was employed using JMP software. The factors and levels are shown in Table 1.

Table 1 Low Middle High

Temperature (˚C) 25 30 35

Spin Speed (rpm) 300 525 750

Flow rate (ml/min) 1000 1375 1750

The responses measured were Etch Rate, TTV and Surface Roughness.

Silicon wafer thickness and TTV measurements were done on the MTI Proforma 300SA using MTI’s exclusive Push/Pull™ capacitance technology. Automated scans across the complete wafer surface provided complete mapping of the wafer thickness before and after etching. The spacing on the scan pattern was 8mm.

Surface roughness measurements (Ra) were obtained using a KLA P16+ Stylus Profilometer. The calculation done by the instrument for Average Ra is the arithmetic average deviation of the absolute values of the roughness profile from the mean line or centerline. The parameters of the scan (speed and length) can affect the measurement results. For the purpose of this study, the scan parameters were held constant for comparative purposes.

Results:

Etch Rate

Within the range of parameters studied, the Silicon etch rate is dependent upon the spin speed, with temperature as secondary. The response surface plot is shown below along with the parameter estimates.

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Figure 2: a) MTI Proforma 300SA; b) scan pattern for measurements; c) example of thickness

measurement

Figure 2a Figure 2b Figure 2c

The low p-values for Spin Speed and Temperature are small enough to indicate very convincing significance.


Higher etch rates are obtained at higher spin speeds. The etch rate also increases with increasing temperature, as would be expected. The flow rate has little affect on the etch rate.

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Figure 3: Response surface graph of Etch Rate as a function of

Temperature and Spin Speed.

Figure 4: Response surface graph of Etch Rate as a function of

Temperature and Flow Rate.

TTV (Total Thickness Variation)

According to ASTM F657 TTV is defined as the difference between the maximum and minimum values of thickness encountered during a scan pattern or series of point measurements. The MTI Proforma 300SA calculates this value automatically during its analysis of Pre and Post scans.

The TTV was found to be dependent upon spin speed as shown in the parameter estimates and response surface plot.


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Surface Roughness (Ra)

Surface roughness of the incoming wafers is dependent upon the backgrinding process. For these experiments we were using wafers with a coarse grind (325 grit wheel) which showed an Ra value of approximately 2000Å according to the scan parameters we used. For these experiments we decided to quantify the surface roughness by measuring the percent change in roughness before and after the etch.

Surface roughness results were not as predictable. Parameter estimates indicate temperature as the main effect with flow rate next. However the p-values are rather high indicating a poor fit with the data.

Figure 5: Response Surface graph of TTV as function of

temperature and spin speed.

TTV was improved as the spin speed decreased. Temperature and flow rate had negligible effect. In general, the TTV remains very similar to the incoming wafer and is very dependent upon the uniformity of the wafer prior to etch.


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Figure 6: Response surface graph for Surface Roughness as

a function of flow rate and temperature.

In general we are seeing a “smoothing” of the surface after etching. The response surface graph shows the percent reduction in surface roughness post etch. There appears to be more smoothing at lower temperatures.

Figure 7: Surface roughness as a

function of temperature

and spin speed.


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Figure 8: Reduction and Bow and Warp after etching 10 µm silicon

Stress reduction occurs with the etch as shown in the Bow and Warp reduction plots below.

Process Performance

After obtaining the results of the screening design we proceeded to process several wafers using optimized conditions of low temperature (25˚C) and high spin speed (750 rpm) to obtain a fast etch with a smooth surface. Results are shown in the figures below for the etching of 10 µm silicon.

Figure 9: Etch rate reproducibility Figure 10: TTV remains similar to wafer prior

to etch


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The uniformity of etch across a wafer is shown below.

Figure 11: Etch uniformity across wafer

Smoothing of surfaces can be seen in optical photographs and the profilometer scans. In general, we have found that a reduction in surface roughness of approximately 50% is obtained with the etch conditions we are using. Therefore the 2000Å roughness is reduced to 1000Å by the etch. For a smoother starting surface, we see a similar reduction. A wafer polished with a 2000 grit wheel exhibits an initial surface roughness Ra of ~400Å as received and can be reduced to less than 200Å after etching. Below are some optical micrographs of pre and post etched surfaces.

Figure 12: Optical micrographs of surface roughness of “as received” wafer

before etch. Top, center, bottom, left and right areas of wafer.


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Figure 13: Optical micrographs of surface roughness after etch.

Top, center, bottom, left and right areas of wafer.

Figure 14: 3D profilometer scans of surface roughness (a) as received (b) post etch


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Figure 15: Reduction in wafer stress after 10 µm silicon etch

as shown in measurement of (a) Bow (b) Warp

Figure 15a

Figure 15b

Summary:

Wet chemical etching of silicon in a single wafer spin processor provides a uniform removal of silicon and reduces the surface roughness. Spin speed and temperature were found to be the key parameters for controlling the etch rate. Surface roughness was improved at lower temperatures. An optimum process of higher spin speed and lower temperature provided excellent results.


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Laura Mauer joined SSEC in 2008 as the Director of Process Technology. Laura brings more than 35 years of industry experience with her 30 year tenure at IBM as Program Manager for the Strategic Packaging Program, Program Manager of Contamination Control and Technical controller for the DRAM Development Alliance providing her with a wealth of knowledge and industry expertise.

Laura works with all functional areas of the organization to ensure that processes and machines are delivering the intended results at the leading edge of processing requirements, and enabling customer to achieve high, profit-building yeilds with the flexibility to adapt to current conditions.

John Taddei is the Applications Lab Manager at SSEC. Since joining the company 10 years ago, he has developed bevel etch, 65nm wafer cleaning and most recently 450mm wafer cleaning technologies. Prior to joining SSEC he spent 15 years as a project manager in the Industrial Gas industry working in cryogenics and specialty gas applications, many related to the semiconductor industry. John has a B.S. in Chemical Engineering from the University of Pennsylvania and a B.S. in Physics from Lebanon Valley College.

Ramey Youssef is an Applications Development Engineer at SSEC and currently specializes in wet processing applications. Prior to joining the Applications Lab last year, Ramey was the Worldwide Services Manager at SSEC and has been with the company for 5 years. Previous semiconductor industry experiences include fab design and device fabrication in technical and management roles. Ramey has a B.S. in Chemical Engineering from Lehigh University.


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