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Introduction to LPDDR3
LPDDR3 Symposium 2012
Sangeun Lee
SK hynix Inc.
LPDDR3 Market Introduction
LPDDR3: Perfect Solution for Mobile Applications
Commodity DRAM
LPSDR/DDR
LPDDR2
LPDDR3
Mobile Market Transition
55%
30%
5%
45%
70%
70%
37%
25%
63%
2011 2012 2013 2014
LPDDR LPDDR2 LPDDR3
4% 0% 0%
96% 100%
66%
20%
34%
80%
2011 2012 2013 2014
(Source: iSuppli, SK hynix Marketing)
Mobile DRAM transition for Smartphone Mobile DRAM transition for Tablet
Introduction of Key Features
LPDDR2 & LPDDR3 Feature Comparisons
LPDDR2-S4B LPDDR3
Data Rate (per pin) 333~1066 Mbps 800~1600 Mbps
(up to 1866/2133 with LPDDR3E)
Density 64~8Gb 4Gb~32Gb
I/O Pin CK_t/c, CKE, CS_n, CA0~9, DQ0~31,
DQS0~3_t/c, DM0~3
CK_t/c, CKE, CS_n, CA0~9, DQ0~31,
DQS0~3_t/c, DM0~3,
ODT
Interface HSUL_12 HSUL_12
w/ optional ODT
Command/Address Bus DDR DDR
Data Bus DDR DDR
Voltage
(VDD1/2/CA/Q) 1.8V/1.2V/1.2V/1.2V 1.8V/1.2V/1.2V/1.2V
I/O organization x16 / x32 x16 / x32
Number of Banks 4/8 8
Prefetch 4 8
Burst Length 4/8/16 8
Termination - Supported (Optional)
Package Types MCP/PoP MCP/PoP
LPDDR3 Address Definitions
Address
Compatibility
w/ LPDDR2
LPDDR3 Command Definitions
LPDDR2-S4B LPDDR3
Activate Activate
Burst Read
- Reads interrupted by a read
Burst Read
- (Interrupt function is not required.)
Burst Write
- Writes interrupted by a write
Burst Write
- (Interrupt function is not required.)
Burst Terminate (Burst Terminate function is not required.)
Write Data Mask Write Data Mask
Precharge Precharge
Refresh Refresh
Mode Register Read
- Temperature Sensor
- DQ Calibration
Mode Register Read
- Temperature Sensor
- DQ Calibration
Mode Register Write
- MRW Reset
- ZQ Calibration
Mode Register Write
- MRW Reset
- ZQ Calibration
- CA Training - Write Leveling
- ODT
Power Down Power Down
Deep Power Down Deep Power Down
Input Clock Stop and Frequency Change Input Clock Stop and Frequency Change
No Operation Command No Operation Command
Key Functional Changes
Key Changes 1. Interrupt / Burst Terminate
LPDDR2 LPDDR3
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5
Interrupt is occurred.
1) LPDDR2 has 4 bit prefetch architecture.
2) It means minimum 4 bit wide data input/output is
required at minimum. (A0~A3 in the diagram.)
3) With the BL8 configuration, if data input/output length
meet 4 bit, then it can be interrupted by following data
input/output.
4) In case of BL16, the length can be interrupted are 4 /
8 / 12 bit.
Interrupt can not be occurred.
1) LPDDR3 has 8 bit prefetch architecture.
2) It means minimum 8 bit wide data input/output is
required. (A0~A7 in the diagram.)
3) With the BL8 configuration, interrupt can not be
occurred, because all the data input/output is already
completed.
A0 A1 A2 A3 A4 A5 A6 A7
Key Changes 2. Write Preamble
tWPRE = 0.35tCK tWPRE = 0.8tCK
TG minute 2012_10_18
With ODT on condition,
DQS/DQ is changed from VTT to VDDQ.
Then, write preamble also should be started
from VDDQ level.
tWPRE = 0.8tCK
LPDDR2 LPDDR3
New Features: 1. CA Training
Controllers can use CA training mode to improve timing margins of CA bus.
New Features: 2. Write Leveling (1/2)
To compensate Clock to DQS_c/DQS_t timing, Write Leveling can be used.
tDQSSmax
tDQSSm`in
tCK Min Max Max-Min Unit
Spec. 0.75 * tCK 1.25 * tCK 0.50 * tCK
800Mbps 2.5 1.875 3.125 1.25 ns
1600Mbps 1.25 0.9375 1.5625 0.625 ns
2133Mbps 0.938 0.7035 1.1725 0.469 ns
New Features: 2. Write Leveling (2/2)
Reference: DDR3 Specification - JESD 79-3E
By adjusting tDQSS timing, proper write operation can be done.
In write leveling mode,
“0” on DQ means tDQSS timing is not correct.
When controller properly adjusts tDQSS timing,
then DQ signals will be changed as “1”.
Clock’s delay
DQS’s delay
DQS signal
Is delayed by controller
to compensate
timing difference
New Features: 3. ODT (1/5)
<Functional Representation of ODT> <Mode Register setting>
LPDDR3’s ODT pin controls
turning on/off RTT.
New Features: 3. ODT (2/5)
<Write Operation with ODT on> <Read Operation with ODT off>
Turn on ODT pin for Write Operation
ODT enable
Turn off ODT pin for Read Operation
ODT Disable
ODT is supported for Write Operation with MR setting & ODT pin.
New Features: 3. ODT (3/5)
<Usage cases of ODT function>
Function Description
ODT mode enabling By setting MR11 OP<1:0>, ODT mode can be enabled.
Then, ODT function is available through ODT pin control.
Write operation
with ODT on Users need to control ODT pin to turn on RTT.
Read Operation
with ODT off
i) Users can control ODT pin to turn off RTT.
ii) LPDDR3 can automatically turn off RTT during Read operation.
Power down
with ODT on/off
Users can define whether ODT can be on/off during PD with MR11 OP<2>. It
is intended to offer easy ODT control with 2 rank configuration.
Self Refresh, Deep Power Down,
CA Calibration, ZQ Calibration,
Write Leveling
Mostly ODT is turned-off automatically, but refer to the specification for the
description of each cases.
ODT is supported for Write Operation with MR setting & ODT pin.
New Features: 3. ODT (4/5)
With the 2 Rank Configuration, 1 ODT pin is enough to control 2 DRAMs.
LPDDR3 LPDDR3
Rank 0
LPDDR3
Rank 1
<1 Rank Configuration> <2 Rank Configuration> To enable Rank 0’s ODT during PD, MR setting is required.
Command
/ Address ODT
DQ
CA ODT
DQ
DQ
DQ DQ
Command
/ Address ODT
CA ODT
Command
/ Address GND
CA ODT
PAD name
External Pin
New Features: 3. ODT (5/5)
With ODT, better signal integrity is expected.
LPDDR3 Package Solutions
LPDDR3 Package Solutions
LPDDR2 LPDDR3
PoP
1ch.
(x32)
168 (12x12mm2, 0.5p)
136 (10x10mm2, 0.5p)
216-a ch. (12x12mm2, 0.4p)
216-b ch. (12x12mm2, 0.4p)
2ch.
(x32 x 2)
216 (12x12mm2, 0.4p)
220 (14x14mm2, 0.5p)
240 (14x14mm2, 0.5p)
216 (12x12mm2, 0.4p)
256 (14x14mm2, 0.4p)
Discrete
/ MCP
1ch.
(x16)
79 (Discrete, 0.5p)
121 (MCP, 0.5p) N/A
1ch.
(x32)
134 (Discrete, 0.65p)
162 (MCP, 0.65p)
180 (MCP, 0.65p)
186 (MCP, 0.65p)
178 (Discrete, 0.80/0.65p)
221 (MCP, 0.5p)
2ch.
(x32 x 2) N/A
253 (Discrete, 0.5p)
346 (MCP, 0.5p)
The various solutions will allow flexibility of mobile device’s form factor.
Thank you. - 감사합니다.