iwlpc october 13-15, 2015 dr.kai liu stats chippac

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IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

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Page 1: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

IWLPC October 13-15, 2015

Dr.Kai LiuSTATS ChipPAC

Page 2: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Comparison of flip chip packaging and fan-out eWLB packaging.

Similar to fc-package. But more

straightforward, and more integrated process.

No bumps and substrate involved-low profile possible.

Page 3: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Similar to FIWLP after Recon wafers. Recon wafer process involves:

◦ Incoming wafer back-grinding, dicing, chip-placement and compress molding, and carrier de-bonding.

Page 4: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

eWLB with two dies. One is power amplifier die and another is IPD die.

Different Silicon-node IC dies with different die-thicknesses can be used.

Finer design rules allow smaller form-factors.

Excellent electrical performance.

Equivalent or slightly better thermal performance compared to fc-BGA.

CMOS DieIPD Die

Page 5: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Illustration of eWLB approach (top) and fcBGA approach (bottom) for SiP.

Finer design rules. Less layers needed. Low-profile. Excellent electrical

performance. Equivalent thermal

performance compared to fc-BGA.

Page 6: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Exposed-die eWLB with two dies. 

150um310um

Thin profile for IoT and Wearable application. eWLB body side can be 150-17-um with package

size up to 16x16mm. Acceptable warpage performance.

Page 7: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Package size: 6.0 x 7.0 x 0.2 mm (including micro ball height of 80um)- eWLB body size: 120um.

Used as interposer to translate very fine pitch (<100um) to 150-200um with micro balls).

Warpage about 90um for such very thin eWLB (120um).

Page 8: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

  eWLB as bottom package. Laminate interposer as top package. Vertical interconnections are made available

through PCB-bar structures. Interposer can have LC components. C to

be implemented in periphery and L to be implemented in the middle if possible.

PCB Bar

Page 9: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Cu trace in laminate substrate is rough. TRMS of surface roughness can be as high as 3um.

Cu TRL in WLP process is very smooth. RMS of surface roughness can be as low as 0.3um.

Surface roughness has big impact on insertion loss for very high-frequency applications (>30GHz).

Laminate Substrate eWLB with 3 RDL Layers

Page 10: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Antenna package stacked on to an eWLB

For >30 GHz applications, antenna size can be less than 10x10mm, which can be implemented in common packages.

EMI shielding is critical for antenna-in-package applications.

Page 11: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Double-side RDL allows implementing antenna and transceiver in one package.

PCB-bars are used for vertical interconnections.

PCB-bars can be used effectively for EMI shielding.

PoP with double side RDL

PCB Bar

Page 12: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Antenna pattern is made in bottom RDL.

Antenna ground is made in to RDL.

Separation is realized by properly selecting the PCB-bar height.

Shielding between antenna and transceiver is achieved PCB-bars.

Package including antenna and transceiver for mmWave applications.

Page 13: IWLPC October 13-15, 2015 Dr.Kai Liu STATS ChipPAC

Fan-out process is a more straightforward and more integrated process, than other packaging approaches.

Low profile and small form-factor can be achieved. Excellent electrical performance, and equivalent

thermal performance to fc-BGA. eWLB suitable for very high frequency (mmWave)

packaging with less metal insertion-loss and tighter process tolerance.

eWLB approach using double-side RDL with PCB-bars is attractive for mmWave antenna-in-package applications.