jakub matyas - m-labs

Institute of of Electronic Systems

in the field of study Electronics

and specialisation Electronics and Computer Engineering

Precise PID controller for quantum applications

Jakub Matyasstudent record book number 277464

thesis supervisor

Krzysztof Pozniak, Ph.D., D.Sc.

WARSAW 2020

Precise PID controller for quantum applications

Abstract. Realization of the world’s first Bose–Einstein Condensate in 1995 has opened

a door for conducting research in the field of quantum physics on the atomic or even

sub–atomic scales. Since then, a number of scientific laboratories around the world

have started performing quantum physics experiments. Running this kind of experi-

ment, however, requires advanced hardware and software to control its various aspects

such as driving laser sources used to trap atoms or ions. In this thesis, a design of a

PID (proportional–integral–derivative) controller for such applications is described. It

aims to be compatible with the ARTIQ (Advanced Real–Time Infrastructure for Quantum

physics) control system and Sinara hardware, both of which are open–source projects.

The developed PID controller provides an input and output voltage range of ±10 V. Its

measured bandwidth and latency are no worse than 1 kHz and 1 ms, respectively.

Keywords: PID controller, ARTIQ, Sinara, frequency lock loop, real–time control system

3

Precyzyjny kontroler PID do zastosowan kwantowych

Streszczenie. Zaobserwowanie w 1995 r. po raz pierwszy kondensatu Bosego–Einsteina

umozliwiło przeprowadzanie badan z dziedziny fizyki kwantowej w skali subatomowej.

Od tego momentu, wiele laboratoriów naukowych na całym swiecie rozpoczeło realizacje

eksperymentów kwantowych. Jednakze przeprowadzanie tego typu badan wymaga uzycia

zaawansowanego sprzetu i oprogramowania, które umozliwiałyby sprawowanie kon-

troli nad roznymi aspektami eksperymentów. Za przykład moze posłuzyc kontrolowanie

laserów, które sa uzywane do oswietlania chmury atomów i jonów w celu złapania ich w

pułapki magnetyczno–optyczne. W niniejszej pracy opisany został proces realizacji regula-

tora PID (proporcjonalno–całkujaco–rózniczkujacego, ang. proportional–integral–derivative)

stworzonego miedzy innymi do wspomnianych wyzej zastosowan. Został zaprojektowany

z załozeniem kompatybilnosci z systemem ARTIQ (Advanced Real-Time Infrastructure

for Quantum physics, pol. Zaawansowana Infrastruktura Czasu Rzeczywistego dla Fizyki

Kwantowej) i sprzetem z rodziny Sinara. Zrealizowany regulator PID zapewnia poprawna

prace i regulacje przy zakresie napiec wejsciowych i wyjsciowych ±10 V. Zmierzone pasmo

i latencja sa nie gorsze niz, odpowiednio, 1 kHz i 1 ms. Petla synchronizacji czestotliwos-

ciowej

Słowa kluczowe: regulator PID, ARTIQ, Sinara, petla synchronizacji czestotliwosciowej,

system sterujacy czasu rzeczywistego

4

załącznik nr 10 do zarządzenia

nr 46 /2016 Rektora PW

Politechnika Warszawska

Warsaw University of Technology

1 / 2

………........................ miejscowość i data

place and date

…………………………….. imię i nazwisko studenta name and surname of the student

…………………………….. numer albumu student record book number

…………………….………. kierunek studiów field of study

OŚWIADCZENIE

DECLARATION

Świadomy/-a odpowiedzialności karnej za składanie fałszywych zeznań oświadczam,

że niniejsza praca dyplomowa została napisana przeze mnie samodzielnie, pod opieką

kierującego pracą dyplomową. Under the penalty of perjury, I hereby certify that I wrote my diploma thesis on my own, under the

guidance of the thesis supervisor.

Jednocześnie oświadczam, że: I also declare that:

niniejsza praca dyplomowa nie narusza praw autorskich w rozumieniu ustawy z dnia

4 lutego 1994 roku o prawie autorskim i prawach pokrewnych (Dz.U. z 2006 r. Nr 90,

poz. 631 z późn. zm.) oraz dóbr osobistych chronionych prawem cywilnym,

this diploma thesis does not constitute infringement of copyright following the act of 4

February 1994 on copyright and related rights (Journal of Acts of 2006 no. 90, item 631 with

further amendments) or personal rights protected under the civil law,

niniejsza praca dyplomowa nie zawiera danych i informacji, które uzyskałem/-am

w sposób niedozwolony,

the diploma thesis does not contain data or information acquired in an illegal way,

niniejsza praca dyplomowa nie była wcześniej podstawą żadnej innej urzędowej

procedury związanej z nadawaniem dyplomów lub tytułów zawodowych,

the diploma thesis has never been the basis of any other official proceedings leading to the

award of diplomas or professional degrees,

wszystkie informacje umieszczone w niniejszej pracy, uzyskane ze źródeł pisanych

i elektronicznych, zostały udokumentowane w wykazie literatury odpowiednimi

odnośnikami,

all information included in the diploma thesis, derived from printed and electronic sources,

has been documented with relevant references in the literature section,

znam regulacje prawne Politechniki Warszawskiej w sprawie zarządzania prawami

autorskimi i prawami pokrewnymi, prawami własności przemysłowej oraz zasadami

komercjalizacji.

I am aware of the regulations at Warsaw University of Technology on management of

copyright and related rights, industrial property rights and commercialisation.

5

załącznik nr 10 do zarządzenia

Politechnika Warszawska nr /2016 Rektora PW

Warsaw University of Technology

Oświadczam, że treść pracy dyplomowej w wersji drukowanej, treść pracy dyplomowej

zawartej na nośniku elektronicznym (płycie kompaktowej) oraz treść pracy dyplomowej

w module APD systemu USOS są identyczne. I certify that the content of the printed version of the diploma thesis, the content of the electronic

version of the diploma thesis (on a CD) and the content of the diploma thesis in the Archive of

Diploma Theses (APD module) of the USOS system are identical.

............................................... czytelny podpis studenta

legible signature of the student

6

Contents

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1. Magneto-optical trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2. Frequency locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2.1. Servo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3. Existing control systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.3.1. PXI Systems and LabVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.3.2. NQontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.3.3. Quantum Computing Control System . . . . . . . . . . . . . . . . . . . . . . . 16

1.3.4. ARTIQ and Sinara . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.3.5. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2. Thesis genesis, goal and technical assumptions . . . . . . . . . . . . . . . . . . . . . . . . 20

2.1. Genesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2. Goal and assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3. Conception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1. Hardware setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2. Stages of the implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3. Two approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3.1. ARTIQ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3.2. Bare–metal implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4. Controller development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1. ARTIQ implemetation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.1. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.2. Communication with Zotino . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.3. Communication with Sampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.4. Integration and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2. Bare–metal implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.1. Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.2. Setting PGIAs’ gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.3. Infinite Impulse Response filter . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.4. Control over digital to analog converter . . . . . . . . . . . . . . . . . . . . . . 32

4.2.5. Pin assignment and signals conversion . . . . . . . . . . . . . . . . . . . . . . 35

4.2.6. Servo module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5. Tests and measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1. Testing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.2. Tests of the ARTIQ–based implementations . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2.1. Implementation with immediate conversion to volts . . . . . . . . . . . . . . 42

5.2.2. Implementation without conversion to volts . . . . . . . . . . . . . . . . . . . 46

5.3. Tests of the bare–metal implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.4. Tests and measurements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7

0. Contents

6. Conclusion and thesis summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.1. Further work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

List of Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8

1. Introduction

The introduction of the quantum theory in the early 20th century and its extensive

confirmation within the next few decades have been a major step towards understanding

the principles of the quantum world and, what is probably even more exciting, the Uni-

verse itself. When a gaseous Bose–Einstein Condensate (BEC) was realized in 1995 for the

first time [1], a door to study particle’s world not only theoretically, but also experimentally,

was opened as wide as never before. After over 70 years of research, Einstein’s prediction

regarding condensation of atoms has been finally confirmed. The team led by Eric Cornell

and Carl Wiemann at the JILA laboratory in Boulder, Colorado, having achieved world first

gaseous condensate in a gas of rubidium-87, laid the foundation for the field of cold atoms

and a new branch of atomic physics. Since then, over 50 research groups across the globe

have made BECs [2] and until 2009 a BEC has been achieved for 12 atomic species [3].

Bose–Einstein Condensate may be in principle described as a state of matter in which a

large number of identical particles occupy a single [3]. This means that when a BEC occurs,

multiple atoms behave as a single entity which allows scientists to study the complicated

world of quantum physics by observing and conducting research on a ‘superatom’, instead

of extremely small single atoms [4]. Being able to explore the behaviour of systems

at atomic and subatomic length scales is essential to make significant discoveries and

advancements in modern science and technology. Even though the filed of cold atom

research is still in its early years of development, studies conducted on BEC have already

made an impact on today’s industry and science. In particular, Bose–Einstein Condensates

are used in quantum experiments aiming to achieve the next generation of improved

atomic clocks with better accuracy, based on optical transitions instead of microwaves

ones [5]. Furthermore, due to BEC being a coherent wave, an atomic laser may be produced

soon and used, e.g. in the process of nanolithography or applied to any application that

requires well–controlled beams of atoms [6]. Atomic interferometry based on BEC has

also proved itself a versatile tool for measuring inertial forces or physical constants [5].

Even though these applications are already extremely useful, Bose–Einstein Condensate

may be applied in the field that has gained the exceptional popularity throughout the last

few years, and which is believed to be a breakthrough in the field of computational power:

quantum information. On one hand, following Richard Feynman’s suggestion that neither

the world nor quantum mechanical effect should be simulated by a classical computer

because they are not classical [7], a quantum simulation is developed [8]. On the other

hand, BEC is used as a platform for processing qubits with the aim to build a quantum

computer [5].

It is clear that even though the first Bose–Einstein Condensate was realized 25 years

ago, there is a lot yet to be discovered in the field of quantum mechanics Thanks to

achievements of previous generations of scientists, the world is on the verge of the ’Second

Quantum Revolution’. The timing is perfect, as science is facing the challenge of the end

9

1. Introduction

of Moore’s law, while the world is in desperate need for constant advancement in terms of

processing power [9].

1.1. Magneto-optical trap

At the foundation of achieving Bose–Einstein Condensate lays ion or neutral atom

cooling and trapping. Although trapping may be performed using for example Ioffe-

-Pritchard trap or Paul trap (the latter of which works for charged particles [10]), usually

the magneto–optical trap ( MOT) is used, because of its simplicity of construction and its

depth [11]. The concept seems to be straightforward, as William D. Phillips and Harold J.

Metcalf once stated [12]:

’Atoms are slowed and cooled by radiation pressure from laser light and then

trapped in a bottle whose "walls" are magnetic fields. Cooled atoms are ideal for

exploring basic questions of physics’

However, the idea of temperature in the sentence above might be misleading and should

be taken into careful consideration. Thermodynamics connects temperature to a state’s

parameter of a closed system in thermal equilibrium and its potential to exchange heat,

which is not applicable to laser cooling, because atoms constantly absorb and scatter light.

Additionally, light cannot be treated as heat. In this case, temperature is recognized as an

atom sample’s average kinetic energy, which is reduced by laser light [13]. Therefore, in

principle, the first step to achieve cold atoms is to slow down atomic beams. It can be done

with the use of momentum transfer that happens when an atom absorbs a photon. Each

act of absorption reduces atom’s velocity by ħkm (single photon’s velocity) [14]. Due to the

Doppler effect, the photon’s frequency is up-shifted when atoms are propagating towards

the laser source. Therefore, to ensure that photons are absorbed only by those atoms, the

laser frequency is tuned slightly below the atomic resonant frequency. In order to achieve

cooling across all dimensions, it is necessary to illuminate gas of atoms with three pairs

of circularly polarized orthogonal laser beams of the proper frequency. Furthermore, to

successfully trap atoms, application of a magnetic field is necessary. Laser beams are

responsible not only for slowing down atoms, but also, thanks to radiation pressure that

converges on the centre of the gas chamber, for creating a force that traps atoms inside.

Applying a magnetic field of quadruple distribution acts as a control on this force [11].

Having achieved enough densities after cooling and trapping, certain atoms undergo a

transition — one sought after by physicists for decades Bose–Einstein Condensation.

Cooling down and trapping atoms is a process that needs applying a particular fre-

quency of laser beams that is slightly detuned from the atomic resonant frequency. If

a laser beam of longer or shorter wavelength was used, fewer atoms would be trapped

and achieving BEC would become even more problematic. Therefore, a precise reference

laser source is used, with which other lasers are synchronised. To ensure that each laser

10

1. Introduction

beam that illuminates a gas of atoms is of the desired wavelength, a frequency locking

mechanism is needed.

1.2. Frequency locking

When clouds of atoms are to be cooled down and trapped, a need for a control

system that adjusts laser source frequency to the set value arises. Fortunately, even

though cooling lasers need to be set to precise values, for many applications phase coher-

ence is not required [15], and simple frequency offset lock is sufficient. Since frequency

offset locking is based on a feedback loop, commonly used control systems are based

on proportional—integral–derivative (PID) controller. One of the common controlling

schemes is to modulate laser light directly with electric current. On the upside, it is simple

and robust. On the downside, its non–linearity and heating limits the practical band-

width [16], while laser output wavelength drifts with modulating current. However, when

higher bandwidth and stability is needed, acousto-optic modulation (AOM) is commonly

used. A simplified frequency offset locking scheme, used for example in [17], is shown in

figure 1.1.

Figure 1.1: Simplified frequency offset locking scheme

Since optical frequencies are usually too high to measure them directly, scaling down

is required. It can be done by combining beams from a reference laser source and the

controlled one. Achieved optical beat note is then mixed with stable frequency from

radio frequency (RF) local oscillator (LO), and their difference is fed into phase-frequency

detector (PFD). Based on PFD output, servo, which is a workhorse of the control system,

drives the controlled laser appropriately.

11

1. Introduction

1.2.1. Servo

Thanks to its flexibility, ease of implementation and robustness, the PID controller

is among the most popular regulators used in electronics. A generic PID controller’s

application, with its particular parts specified, is shown in figure 1.2.

The PID regulator’s mathematical model is well–developed and described in numerous

papers. Despite its many advantages, one has to bear in mind that a feedback loop control-

ling scheme has drawbacks as well. Probably the most noticeable one is its susceptibility

to becoming unstable when not designed properly [18]. This property requires a designer

to carefully study plant’s impulse response and adjust the controller gains (proportional,

integral and derivative) in order to avoid positive feedback, which may result in uncon-

trolled behaviour or even the system being damaged. The controller’s output signal can

be described with the following equation [19]:

u(t ) = Kp e(t )+Ki

t∫0

e(τ)dτ+Kdde(t )

d t, (1.1)

where u is a control variable (CV), e is the error signal and equals to r − y , with r being the

setpoint (SP) — value to which y is desired to converge — and y being the process variable

(PV) measured from the plant’s response to the control signal.

Figure 1.2: A generic closed feedback control loop

The control signal consists of three terms: proportional, integral and derivative. As Hes-

heng Wang shows in [20], each of them is responsible for a different closed–feedback–loop–system

behaviour:

• proportional gain (Kp ) makes controller’s output proportionally big to error signal,

however, does not eliminate steady–state error and easily makes the controller prone

to becoming unstable;

• integral action (Ki ) allows to eliminate steady–state error, but is likely to cause

12

1. Introduction

overshooting — it accumulates past values of error signal and based on them acts

proportionally to Ki ;

• derivative action (Kd ) counteracts overshooting and improves the system’s stability.

According to Murray and Aström [19], most PID controllers’ implementation lacks a

derivative part. Therefore, they point out, term PI controller is more appropriate in that

case. Murray and Aström, however, argue that term PID controller may be used as well, as

a more general one for this class of regulators. The same convention is followed in this

thesis.

1.2.1.1. Implementation of PID controller in FPGA

With coming of the digital era, cheap integrated circuits and high–speed controllers

have become available on an unprecedented scale. It was only a matter of time when the

industry started using digital control systems (for example field–programmable gate array

(FPGA) based). What makes digital control so appealing is mostly its efficiency and ease of

implementation.

System analysis and design may be a daunting task when done in the continuous–time

domain only, especially when it includes some sort of digital control. To ease that task,

system’s behaviour is often represented in various domains — each of them aims to

provide information about the system’s nature or characteristics and is used for different

applications and purposes.

While every system exists in the time domain, it is often convenient to consider its

response in the complex frequency domain (S–plane) [21]. The mathematical tool that

allows to transit a signal from continuous–time to continuous–frequency domain is the

Laplace transform, which is defined as

L { f (t )} = F (s) =∫ ∞

0f (t )e−st d t , (1.2)

where s is a complex frequency variable.

When it comes to discrete–time signals, the ones used in digital systems, the Z–transform

is of great importance — it is a counterpart of the Laplace transform for continuous–time

signal that transits a signal to Z–plane, instead of S–plane. The Z–transform of sequence

x[n] is defined as

Z {x[n]} = X (z) =∞∑

n=0x[n]z−n , (1.3)

where z is a complex continuous variable [22].

Both transforms are presented in unilateral versions, which means that they become

non–zero at either t = 0 or n = 0, and this convention is commonly used in digital signal

processing literature — since the system does not recognize values of a signal before the

time t = 0.

13

1. Introduction

Every control system action is based on the modification of the signal’s wave shape,

and therefore, can be considered and described as a digital filter. A system response can

be either infinite, which happens when the filter’s output is computed by using current

and previous input samples and previous output sample, or finite, when its response is

dependent only on input samples. This means that the finite impulse response (FIR) filter

is a special case of the infinite impulse response (IIR) filter [23]. Filters, in general, are

often described with the following difference equation:

y[n] =N∑

i=0bi x[n − i ]−

N∑i=1

ai y[n − i ]. (1.4)

As a result of performing the Z–transform on equation 1.4, the filter’s transfer function in

the discrete zero–pole domain, which is defined as a ratio of the Z–transform of the output

signal to the Z–transform of the input signal, is obtained:

H(z) = Y (z)

X (z)= b0 +b1z−1 +b2z−2 + ...+bN z−N

a0 +a1z−1 +a2z−2 + ...+aN z−N. (1.5)

As mentioned in the previous section, the PID controller is a closed feedback loop

system; therefore its output depends linearly on both input and output values. This

property allows one to treat a PID controller as an infinite impulse response filter and its

transfer function may be described in continuous–frequency domain as [19]:

H(s) = Kp +Ki1

s+Kd s. (1.6)

To improve timing and processing performance, many FPGA manufacturers in their

design include modules, that are dedicated specifically to performing calculations on

binary vectors in digital signal processing (DSP). As an example of a such DSP block, Xilinx

DSP48E2 may be used [24]. Implementation of a digital filter in FPGA is a task DSP modules

have been designed for, and are included in FPGA integrated circuits. Thus a common

way of implementing digital PID regulators in FPGAs involves usage of those DSP blocks.

However, PID controller coefficients used in continuous–time domain equations have to

be converted to the domain in which the digital control circuit exists for the control system

to do its job. A general way to calculate the digital biquad filter coefficients is transforming

the controller’s transfer function from S–plane to Z–plane representation, which can be

achieved using e.g. bilinear transformation, and comparing the result with equation 1.5.

In order to perform the bilinear transformation, one has to substitute s in equation 1.6

with 2T · 1−z−1

1+z−1 [21], where T is a sampling period. Having transformed equation 1.6 after

the substitution, the PID controller’s transfer function in a canonical form is obtained:

H(z) = (Kp + Ki T2 + 2Kd

T )+ (Ki T −Kd T )z−1 + (−Kp + Ki T2 + 2Kd

T )z−2

1− z−2. (1.7)

14

1. Introduction

To find PI controller’s transfer function, all coefficients from derivative term have to be

removed:

H(z) = (Kp + Ki T2 )+ (−Kp + Ki T

2 )z−1

1− z−1. (1.8)

Comparing equations 1.7 and 1.8 with IIR filter transfer function (equation 1.5) allows

the extraction of coefficients that make the IIR filter play the role of either a PID or PI

controller. Calculated filter coefficients are presented in table 1.

Table 1: Dependency of IIR filter’s coefficients on PID conroller’s coefficients

IIR coefficient PID PI

b0 Kp + Ki T2 + 2Kd

T Kp + Ki T2

b1 Ki T −Kd T −Kp + Ki T2

b2 −Kp + Ki T2 + 2Kd

T 0

a0 1 1

a1 0 −1

a2 −1 0

1.3. Existing control systems

The vast variety of tasks and the increasing number of applications in which Bose–Einstein

Condensate is used requires enormous sets of often incompatible hardware (often from

different electronic eras). Since almost no quantum information experiment is the same,

connecting, controlling and integrating various equipment becomes challenging. More-

over, quantum gas experiments usually consist of not only creating BEC but also con-

trolling other external equipment and basing the system’s feedback on the outcome of

certain algorithms. The new wave of quantum experiments in microgravity or even in

space [25]–[27], poses a challenging demand for miniaturization of control systems.

Issues mentioned above are not the only ones that a modern control system for quan-

tum information experiments has to overcome. In order to obtain good control of the

experiment’s flow, the system should be as close to real–time as possible.

A few full-stack solutions exist and are under development, like IBM Q, Google or

D–Wave. However, their main concern is to build a quantum computer and run quantum

algorithms aiming to solve real–world problems, and are not to run custom physical

quantum experiments.

15

1. Introduction

There are few off the shelf solutions for controlling quantum experiments. As stated in

[28], systems available until recently suffered either from poor timing control in exchange

for ease of use, or from difficulties in programming in favour of tight timing thanks to

implementation on programmable chips. Vlad Negnevitsky in [29] states that the majority

of research groups performing atom or ion trapping construct their own custom–built

control system out of a combination of commercially available components.

There are, however, a few solutions used in quantum information experiments, i.e.

National Instruments PXI Systems and LabVIEW [30], NQontrol based on ADwin digital

control platform [31], Zurich Instruments Quantum Computing Control System [32] or

ARTIQ software with Sinara hardware [33]. Each is described briefly below.

1.3.1. PXI Systems and LabVIEW

National Instruments offer a system for high performance measurement and pro-

cessing applications with a wide range of modular input and output (I/O) instruments

(more than 600) [34]. It provides two different synchronization schemes: time–based and

signal–based, and the NI–TClk delivers modular synchronization of up to a few hundred

ps [35]. In the platform that incorporates the Peripheral Component Interconnect Express

(PCIe) bus into the PXI system, the achievable latency is of hundreds nanoseconds order

of magnitude [36]. The system is not flawless, though. The fastest modules are meant to

be used only sequentially and performing concurrent tasks is not allowed. Surprisingly,

the main disadvantage of the system is probably the software. Although LabVIEW is a

well–known programming environment, being proprietary software makes it impossible

to review even old source codes without purchasing a paid license.

1.3.2. NQontrol

The problem with proprietary software does not occur when NQontrol is used. It

is a control system developed specifically to provide loop control of hardware, that is

obtainable with the use of a software package written in Python. It is capable of handling

up to 8 control loops running simultaneously at the sample rate of 200 kHz. The achievable

control bandwidth, however, is limited to several kHz due to phase delay [31]. NQontrol

is limited only to control loops and cannot be used as an off the shelf solution to control

various quantum information experiments because of its inability to perform tasks other

than just the control loop itself.

1.3.3. Quantum Computing Control System

Zurich Instruments offers precise, ready to use equipment for performing quantum

physics experiments. The Quantum Computing Control System (QCCS) consists of four

components, three of which are shown in figure 1.3 and listed below:

• HDAWG Arbitrary Waveform Generator, with bandwidth up to the 750 MHz [37];

• UHFQA Quantum Analyzer;

16

1. Introduction

• PQSC Programmable Quantum System Controller — allows to synchronize the whole

setup [38].

Figure 1.3: QCCS modules; image taken from [32]

QCCS’s fourth component is the LabOne control software. One of its key features is that it

is fully compatible with the other three devices. Furthermore, it supports many of popular

programming languages used by physicists, including i.a. Python, C or MATLAB [39]. On

the downside, QCCS is a fully proprietary system. Therefore scalability and modifying

possibilities that could provide better system’s adjustment to laboratory equipment and

specific quantum experiment are limited.

1.3.4. ARTIQ and Sinara

ARTIQ

ARTIQ (Advanced Real–Time Infrastructure for Quantum physics) is a software created

with the aim to provide real–time control over the quantum physics experiments. Although

it was firstly developed in collaboration with National Institute of Standards and Technol-

ogy (NIST), it is supported by a growing number of researchers and scientific institutions

across the globe [33] thanks to being an open–source project. ARTIQ is based on Python

and tries to join the expressivity of an interpreted language with timing performance of

custom FPGA design. Thanks to its time–critical part being compiled (called kernel) and

executed on FPGA (called core device), it is able to achieve nanosecond resolution and

sub-microsecond latency [40]. A non–time–critical task may be easily interfaced with

Python remote procedure call (RPC) from a host computer. ARTIQ uses hybrid architecture

with a central processing unit (CPU) implemented in FPGA logic [29]. Due to its goal of

fulfilling modern physics laboratories’ demands for a versatile quantum information con-

trol system, ARTIQ provides a graphical user interface (GUI) and supports i.a. controlling

digital inputs and outputs (DIO), RF generation hardware, digital–to–analog (DAC) and

analog–to–digital (ADC) converters [41].

In order to control hardware for quantum physics experiments with a high–level pro-

gramming language, low–level drivers are needed. In ARTIQ, these are created using Migen

— a Python–based tool that aims to ease very large-scale integration (VLSI) system design

and introduces synchronous and combinatorial orientated programming. It allows to

17

1. Introduction

design gateware with Python and takes advantage of various notions available in high-level

programming languages, such as object–orientated programming etc. [42].

Sinara

Sinara is a product family that has been designed for ARTIQ–based quantum exper-

iments. Thanks to being constructed under the CERN Open Hardware License (CERN

OHL), scalabilty can be achieved and laboratories may adapt the hardware to their needs,

as long as they publicly announce their changes and designs.

Figure 1.4: Example of Sinara family devices’ setup in a crate; image taken from [43]

The family consists of a core device (at first it was KC705 board, but now usually either

Kasli board with Xilinx Artix-7 FPGA [44] or Metlino board with Xilinx Kintex UltraScale

KU040 FPGA is used), that controls slave devices using ARTIQ’s distributed real-time

input/output (DRTIO) protocol, and a number of extension modules of choice [43]. A

large amount of hardware design was done at the Warsaw University of Technology at the

Institute of Electronic Systems. A list of available extension modules (i.a. DAC board, ADC

board or direct digital synthesizer (DDS) board) can be found on the Sinara’s main wiki

page: [43]. The motivation behind the Sinara project was to produce open–source devices

that would allow physics research groups from across the globe to reproduce and reuse

hardware needed to perform quantum information experiments. Furthermore, it is meant

to reduce the amount of duplicated designs and work in different physics labs, because, as

mentioned in [29], many research groups conducting quantum information experiments

develop their own control system optimized for their specific use case.

18

1. Introduction

1.3.5. Summary

A brief summary of existing control systems presented above is shown in table 2.

Even though NI control system provides a great number of modules with wide range

of application and one of the best timing resolution and latency in its class, the ARTIQ

software and the Sinara hardware family are chosen by the group that supports this thesis

project. The necessity to use the LabVIEW software and the PXI being the proprietary

hardware were too big disadvantages to choose this system. Latency and resolution offered

by the ARTIQ and the Sinara are of the similar order of magnitude as those in NI system,

therefore the timing cost of using an open–source system in this case is almost negligible.

Table 2: Summary of existing control systems features

NI PXI andLabVIEW

NQontrol QCCSARTIQ and

Sinara

Open–source no yes no yes

Multi–purpose yes no yes yes

Modular yes N/A yes yes

Amount ofmodules

over 600 13 + LabOne

software18 and

increasing

Resolution10–100

picoseconds forsome modules

N/A N/A nanosecond

Latencyhundreds of

nanosecondsN/A

< 100nanoseconds

sub--microsecond

19

2. Thesis genesis, goal and technical assumptions

2.1. Genesis

This thesis project has been developed in collaboration with Optical Metrology Group

(QOM) of Humboldt University of Berlin (HUB), where several pieces of research regarding

quantum physics (i.a. creating rubidium Bose–Einstein Condensate) and atoms’ behaviour

in the state of microgravity are currently being conducted (for example: [45], [46]). Their

needs to reduce weight, dimensions and to be able to control quantum experiments with

one simple interface were met by ARTIQ and Sinara hardware. Even though modular

nature of the Sinara project allowed to design and run quantum physics experiments of

various kind with a wide range of laboratory equipment, there was no easily interfaced,

ready–to–use servo to modulate connected laser sources directly (with electric current),

which was imposed by laboratory equipment.

A simplified diagram of the process the QOM needed to control and connections

between its particular components is shown in figure 2.1.

Figure 2.1: Block schematics of the controlled process

Optical frequency signal emitted by controlled laser source was mixed with optical

frequency signal from a stabilized on an atomic rubidium transition reference laser source

in order to obtain the difference of the two (both of them were of the hundreds of THz

order of magnitude). The frequency difference (GHz order of magnitude) — a beat note

— was then detected by a fast photodiode and immediately converted to a voltage signal.

The resulting frequency was scaled down and mixed with the radio frequency (RF) from

a local oscillator — a process setpoint. During this project the Urukul module (which is

guaranteed to be able to output frequency correctly up to 400 MHz [47]) played this role.

As a result, further frequency scaling down and an error signal were achieved, and after

20

2. Thesis genesis, goal and technical assumptions

the filtration with low–pass filter signal reached phase–frequency detector. PFD’s output

voltage was dependent on the lock type the system operated in — when the frequency

lock was in use, the signal oscillated between −1 and 1 volt, whereas when the loop was

phase–coherent it took the form of a ramp signal. From the controller’s point of view, the

PFD’s output signal can be treated as an error signal.

2.2. Goal and assumptions

The need described above defined the goal of this thesis project, which was to design

a PID controller that would be useful in QOM’s quantum experiments and would be

accessible through a PC connected to the Sinara hardware. The phase coherence had not

been required from the control loop, therefore designed regulator was needed only to be

able to lock to the desired reference frequency.

The fundamental rule that had to be abided by was for the controller to be run on

the Sinara core and be built with the ARTIQ software and its auxiliary tools (for example

Migen). What is more, implementation of an anti–windup protection in the integral part

of the controller in order to allow it to react instantly on the change of the input signal,

even when the controller output signal remained at the rail for a longer period of time,

was compulsory. Implementation of the derivative part was not required. The laser source

should be modulated directly (this can be achieved by applying varying voltage to the laser

driver module) and the controller output should be able to set the control variable voltage

within a range of at least ±1 V. The input voltages to the controller should be supported in

a range of at least ±1 V as well. Furthermore, the regulator’s bandwidth, often defined as a

cut–off frequency where the closed–loop gain reaches the point of 3 dB difference from

the reference value [48], was required to be of at least hundreds of Hz order of magnitude.

Last but not least, the controller average latency should be not worse than 1 ms (with

accuracy of the half its sampling period).

21

3. Conception

3.1. Hardware setup

Hardware used in this thesis project to attain goals presented in section 2.2 consisted

of:

• the Kasli board, which is the FPGA–based controller;

• the Sampler board, which includes 8–channel, 16–bit ADC1;

• the Zotino board, that includes 32–channel, 16–bit DAC2;

• PC that provides user with the controlling interface to the whole Sinara hardware

via Kasli’s Ethernet or USB–JTAG (Universal Serial Bus – Joint Test Access Group)

connection.

The Kasli board was the only controller from the Sinara family that was available in

the laboratory at the time. Therefore, its usage was necessary to meet the requirement of

using the Sinara hardware and ARTIQ with its auxiliary tools. Although the whole ARTIQ

environment allows to port programs and solutions to new boards, doing so was outside

of this thesis scope.

Sampler is equipped with 8 integrated circuits that perform analog–to–digital conver-

sion with 16–bit resolution [49]. Moreover, thanks to the programmable–gain instrumen-

tation amplifiers that are mounted on the board, its input voltage ranges from ±10 mV up

to ±10 V [49]. As the Sinara project page states [49], the board’s sample rate reaches up to

1.5 MHz when the device is in a fast mode.

To meet the requirement set for the laser source to be modulated directly, the Zotino

board was chosen. It is a digital–to–analog converting module that allows setting its output

to the voltages in range of ±10 V [50] and provides a designer with the analogue bandwidth

of 75 kHz and the update rate of 1 MSPS (Mega–Samples Per Second).

To access and communicate with the designed control system and the Kasli board, a

PC was connected to the Kasli controller via either Ethernet (to interface the hardware

with ARTIQ software) or USB–JTAG cable (to access the FPGA directly.)

The Sinara modules’ connections to themselves and to the controlled process are

shown in figure 3.1. The PFD’s output voltage (the error signal) was sampled by the

Sampler board and forwarded to the Kasli controller. That is where the PID algorithm

was implemented and all the control over both connected modules was done. Based on

the error signal’s values and coefficients implemented by the user, the Kasli controller

performed calculations and sent their results to the DAC on the Zotino board. As a result,

the control variable that drove the laser source was set to the appropriate voltage value.

1See Appendix 1.1 for details on the Sampler board and its schematics.2See Appendix 1.2 for details on the Zotino board and its schematics.

22

3. Conception

Figure 3.1: Block schematic of the system used in the thesis project and their connections

3.2. Stages of the implementation

In the controller’s construction four main parts may be distinguished:

• initialization of both Sampler and Zotino;

• communicating with the Zotino board and setting desired values on its output;

• communicating with Sampler and accessing sampled values;

• actual control and integration of the other three parts.

3.3. Two approaches

Two different approaches of servo implementation were tested during the work on this

thesis project: implementing PID controller with ARTIQ (software implementation with

the time–critical part being compiled and run on the FPGA) and with Migen (bare–metal

implementation, which means that the whole program had to be compiled and then

flashed into the FPGA’s memory).

3.3.1. ARTIQ implementation

Sinara hardware is created with the goal to be compatible with ARTIQ control system;

therefore drivers that allow controlling the number of boards, including Zotino and Sam-

pler, had been already well–developed and incorporated into ARTIQ at the time of the

implementation. Thanks to the above and to the fact that ARTIQ is a subset of a high–level

programming language — Python — employment of each stage and designing the whole

script was easy to obtain, took little time and required almost no prior knowledge of the

protocols used by integrated circuits mounted on module boards. There are, however,

23

3. Conception

drawbacks to this solution — ARTIQ does not support concurrency, only parallelism (this

means, that two different events can occur at the same time, e.g. two independent DIO can

be set to take place at the same time, but nothing else can be processed until the parallel

block’s longest action has already ended). Therefore, implementing a closed feedback

loop controller with ARTIQ, prevents a user from further usage of the control system,

and thus from using all the Sinara family boards, alongside the regulator. What is more,

implementation in the software does not allow to fully exploit hardware’s possibilities

and significantly limits the controller’s available bandwidth, especially when it comes to

driving more DAC channels than one at the time.

3.3.2. Bare–metal implementation

The standard approach to bare–metal implementation in an FPGA would be to choose

either Verilog or VHDL as a hardware description language. Although it is possible to

incorporate Verilog code into the ARTIQ control system or to implement it directly in Kasli

FPGA’s logic, Migen was chosen for this task to meet the requirements described in section

2 and to keep better compatibility with the whole control environment. It is supposed

to be easier and more powerful than both of hardware description languages mentioned

above.

Due to the fact, that this approach lacks direct access from the ARTIQ level and is

implemented in FPGA logic, it overcomes the available bandwidth limit imposed by the

software controlling Sinara modules, but in result, no control over the regulator’s behaviour

is possible with ARTIQ. Having introduced synchronous and combinatorial blocks in

Migen, it’s creators made it support both sequential and parallel programming, following

the scheme present in modern FPGA programming paradigms. Available bandwidth,

therefore, is mainly dependent on the hardware constraints and on the implementation

itself. However, the bare–metal approach’s biggest flaw is that it has to be flashed into the

FPGA memory (either volatile or non–volatile), which means that it cannot be used in

parallel to the ARTIQ software. As a result the user cannot exploit full potential of ARTIQ

and Sinara to conduct experiments.

Moreover, contrary to the ARTIQ implementation, the bare–metal approach requires

the designer to carefully scrutinize data sheets of integrated circuits mounted on boards,

in order to get familiar with protocols they use to communicate with the master device —

the software drivers are accessible only from the ARTIQ level.

24

4. Controller development

4.1. ARTIQ implemetation

ARTIQ implementation was performed in two ways: one with the immediate conver-

sion of sampled values from machine units to volts, and one with only adjustment of

sampled values to the binary representation required by DAC integrated circuit instead.

The structure of both implementations is almost identical and the differences are limited

only to use of different functions to obtain or to produce value either in volts or machine

units.

Time–critical parts of the code are marked with a @kernel flag. In order for the compiled

function to return a value that may be used outside the compiled part of the code, some

kind of container (i.e. list or variable) for it has to be provided as a function’s argument. In

other case, the value may be returned with the Python return statement.

4.1.1. Initialization

Initialization of both Zotino and Sampler boards is done by invoking a function initial-

ize_devs. It clears all real–time input/output first–in, first–out queues (FIFOs) and moves

the time cursor to the current value of hardware clock with a margin. Moreover, it sets

each channel’s gain of programmable–gain instrumentation amplifier (PGIA) to the given

value — input signal’s maximum amplitude that the module is able to sample correctly

depends on that — and initializes the Zotino board. Each operation has to be followed by

a delay by the appropriate amount of time — it sets the core device’s time cursor after the

operation is already done.

4.1.2. Communication with Zotino

Communication with the Zotino board is done by calling a function named write_-

output, which takes as arguments channel ‘number’ and ‘value’: ‘number’ parameter sets

the number of DAC channel the data is written into, and the ‘value’ is the DAC’s output

value in volts. What is more, this function drives the ldac (load data) line low, in order for

the DAC to know that the data sent is valid, and prevents the output value from being out

of Zotino’s operating range.

4.1.3. Communication with Sampler

In order to acquire sampled values of the error signal, a function sample has to be

invoked. Since sampling is a time–critical operation, a Python list object — values — is

passed to the function as an argument. Values is a list of variables in which sampled data

from ADC channels is stored. In case of the implementation with conversion to volts,

variables inside the list are floating–point numbers, whereas in the other case, integers.

The length of the argument passed to sample is imposed by the functions controlling ADC

implementation — to deliver high transmission speeds of sampled data, Quad SPI mode

25


to communicate with ADC is used. Therefore, only an even number of samples may be

acquired each time sampling takes place. The channel values are read sequentially.

4.1.4. Integration and control

According to the ARTIQ style of designing experiments, each part of the program is

implemented as a method of the class that inherits from the EnvExperiment module. In

case of this thesis project, the experiment controlling class is named PID_controller.

In order to run an ARTIQ experiment, two essential methods should be implemented

by the user: run, which may interact with the hardware and is the heart of the control flow

of the experiment, and build, which should be used to request for devices. What is more,

there is a prepare method overloaded, which is executed before the start of run function

and which asks the user to enter coefficients for the PID controller.

In addition, there are three independent methods implemented, that are responsible

for proportional multiplication, integral and derivative action, and are named propor-

tional_multiply, integral_part and derivative_part respectively.

4.1.4.1. Proportional part

Method responsible for the proportional part, takes K_p coefficient and sampled value

of signal — error — as arguments, performs multiplication of them and returns the result.

4.1.4.2. Integral part

The integral part requires three arguments: error, the same value as in the proportional

part, integral_in, which is the integrator output from the previous iteration, and coefficient

K_i. What is more, the anti–windup protection is implemented, which prevents the

integrator from adding next values, in case the sum of previous samples has exceeded

the operating values of DAC. Therefore, PID controller is able to react immediately when

the error signal changes and does not have to wait until the sum falls again into the range

of the DAC operating voltages. The method returns two variables: the updated value of

integral_in as the sum of all samples of error and integrated_out, which is the integrator’s

reaction on the current error value.

4.1.4.3. Derivative part

The method responsible for the PID controller’s derivative action requires, similarly

to the integral part, three arguments: error, which is the same value — corresponding to

the error signal — as in the both parts described above, last_error, which equals to the

previous value of error, and the coefficient — K_d. This method returns two variables:

last_error and derivative_out, which is the method’s reaction on the incoming signal.

4.1.4.4. Run method

The actual integration of all PID controller’s components and control of the loop takes

place inside this method. In an infinite loop, ADC channels are sampled using the method

26


sample, each controller part’s contribution to the output value is calculated either in

parallel. Eventually, all contributing values are summed up and written to the DAC with

the write_output method. Listing 4.1 shows the example of the infinite loop where the

sampling, calculating and writing to Zotino is done.

Listing 4.1: ARTIQ main loop

while True:

self .sample(values)

delay(400*us)

with parallel:

prop_out = self.proportional_multiply (values[6], self.Kp)

integral_in, integrated_out = self.integral_part (values[6], integral_in, self .Ki)

last_error, derivative_out = self.derivative_part (values[6], last_error, self .Kd)

result = prop_out + integrated_out + derivative_out

self .write_output(self.DAC_channel, result)

4.2. Bare–metal implementation

PID controller (actually the PI controller, but, as mentioned in section 1, term PID in

this paper is used, as a more general one to describe this class of controllers) had already

been implemented with Migen, but its usage was limited to only acousto–optic modulation

with the Urukul board used to control external devices. Since it made use of the ADC driver,

it performed control with the module that had been implemented in FPGA’s dedicated

circuit for digital signal processing and was proven to be working correctly, a decision to

base implementation described in this thesis on already existing solution has been made.

Therefore what was needed to be done was the implementation of the DAC driver, careful

and thorough examination of the existing controller’s implementation and adjustment of

the module that is managing, controlling and integrating all parts.

4.2.1. Architecture

Overview of the controller’s architecture implemented with Migen is presented in

figure 4.1. Each of the modules inherits from the Migen’s Module class, which defines

special attributes that are used to describe classes’ logic, in particular, synchronous and

combinatorial statements. The top class is Servo, which integrates all components neces-

sary for the implementation of a control loop, and is in charge of the control over each

device.

Migen, similarly to VHDL or Verilog, interprets signals as single–ended ones, whereas

the Sinara boards require from the Kasli controller usage of the low–voltage differential

signalling (LVDS) standard; therefore conversion of signals that were to be used outside of

the FPGA was needed. Due to the fact, that Migen creators had already developed classes

for that purpose, the conversion could be obtained with little coding, and thus placed in

the same file a component had been described in. However, in order to keep the code

27


as transparent as possible, a decision to separate the module’s description and signals’

conversion into independent files was made. Hence, separate ’Pads’ classes for modules

that need to communicate with components outside the Kasli board were created. Also,

they serve the purpose of assigning data lines used by modules to the Eurocard Extension

Module (EEM) connectors’ pins.

Figure 4.1: Block diagram of Servo and its submodules

The bare–metal implementation of PID controller follows the construction scheme

presented in section 3.2. In this solution, contrary to the ARTIQ implementation, particular

functionalities were divided into separate modules, instead of functions. This way, each

module is responsible for one functionality or operation of one class of integrated circuits

only:

• PGIA allows to set each of the Sampler’s programmable–gain instrumentation ampli-

fiers’ gains to the desired value;

28


• ADC implements control over sampling process;

• DAC with SPI are used to manage data framing and communication with the Zotino

board;

• in IIR module the infinite impulse response filter, that plays the role of the PI con-

troller, is implemented;

• in each of Pads modules, assignment of data lines and signals’ conversion is done;

• Servo module’s internal logic controls other four modules.

4.2.2. Setting PGIAs’ gains

Application of PGIA for each ADC channel, allows the Sampler to operate on a wide

range of input voltages (from ±10 mV up to ±10 V) without loss to the measurement’s

accuracy. Their initialization is performed by setting amplifiers’ pins corresponding to

the desired gain in accordance with table 5. in [51]. On the Sinara’s Sampler board PGIAs

are controlled by shift registers, whose output pins are set by the controller over Serial

Peripheral (SPI) lines. PGIA module’s block diagram is presented in figure 4.2.

Figure 4.2: PGIA module’s block diagram with input and output ports

Although shift register’s timing requirements would be satisfied, if Kasli’s internal clock

had been used to feed data into the register, a decision was made to slow output clock by

the factor of two, to ensure that data is recognized by the receiver correctly.

PGIA module communicates with the controller module inside the FPGA using three

pins: start, ready and initialized. Lines labelled as pads are connected to the lines used by

serial peripheral protocol and serve the communication with integrated circuits mounted

on Sampler board. Control over data transmission is done using the finite state machine

(FSM) that has five states: IDLE, SETUP, HOLD, RCLK and END. When the module is in

the IDLE state, it lets the master controller know that it is ready to transmit data by driving

the ready pin high. To begin a data transmission, the start pin has to be driven high by the

master device — a sequence that sets gains is latched and the state is changed to SETUP.

After beginning its operation, FSM alternates its state between SETUP and HOLD, as long

as there are still bits left to be sent; during the HOLD state both pads.srclk (shift register

clock) and pads.rclk (storage register clock) are driven high. If all 16 bits have been already

29


transmitted, FSM switches to the RCLK state, which only purpose is to provide one storage

register clock cycle more, in order for the data in the shift register to propagate to their

desired positions. The FSM’s last state is END, during which initialized pin is driven high.

Listing 4.2 shows how the control over the module’s bit shifting with Migen is per-

formed. When the FSM is in the IDLE state, none of the 16 bits has been transmitted and

the bits_left signal keeps that value. Each time the FSM leaves the HOLD state, number of

bits left is decreased and the content of the sr_data signal is shifted by one position.

Listing 4.2: Example of control over the bit shifting

If (fsm.ongoing("IDLE"),

bits_left .eq(params.data_width)

) ,

If (fsm.before_leaving("HOLD"),

bits_left .eq(bits_left − 1),

sr_data.eq(Cat(sr_data[1:], 0))

) ,

Gain setting sequence is passed to the PGIA module as a constructor’s argument and

equals to the concatenation of eight 2–bits–wide vectors — each value sets the gain of one

of the PGIAs. Those vectors can be of the following values:

• "00" — results in PGIA’s gain of 1;



• "11" — results in PGIA’s gain of 1000.

One has to bear in mind that with the increasing of the PGIA’s gain, Sampler’s input voltage

range decreases proportionally.

4.2.3. Infinite Impulse Response filter

IIR module is the heart of the control system — it describes, as stated in its name, the

infinite impulse response filter. The majority of work regarding the implementation of

this module has been already done at the time of doing this thesis project. However, a few

modifications were needed for the filter to perform its task, when applied to this project.

The module implementation’s thorough examination has shown that IIR uses two

random–access memory (RAM) blocks. One is used for storing filter’s coefficients and

the second one, for current and previous input and output values. However, the existing

solution lacked the tool, that would allow to write into the module’s memory IIR filter’s

coefficients directly from the controller module in Migen. Values that are kept inside the

coefficient memory are the following:

• FTW0 and FTW1 — two parts of the frequency tuning word;

• POW — phase offset word;

• OFFSET — value added to the sampled word in order to reduce Sampler’s offset

error;

30


• CFG — information about target ADC channel that is connected to the particular

DAC channel;

• B1, B0 and A1 — IIR filter’s coefficients.

The coefficient’s memory layout for one Servo’s channel is shown in figure 4.3 — the

pattern is repeated for every DAC channel used by the PI controller. Since two different

Figure 4.3: Module’s coefficient memory layout

values occupy the same memory address, it was essential for the access to one value not

to overwrite the second one. Therefore, masks, addresses and information, whether the

accessed coefficient is located in the higher or lower half of the address field, are calculated

inside the Servo module, and then passed as arguments to the IIR’s constructor. Coeffi-

cient’s writing process begins with accessing memory’s particular address and checking

the value that is already stored there. Then, the word’s half width is substituted with the

coefficient’s value and written back to the corresponding address’s memory field. The

scheme is repeated until there are not any coefficients left to be written into the memory.

Each coefficient needs at least the duration of the three clock cycles to complete the

task. When all the words are already inside the memory, IIR module signalizes it to the

Servo, by driving pin done_writing high. The whole operation is performed in parallel to

initialization of the PGIAs and the Zotino board, and is necessary to be completed before

servo begins controlling operation.

The module was created with the purpose of driving Urukul integrated circuit (IC) that

accepts amplitude scale factor (ASF) which is 14 bits wide. Since the DAC IC mounted

on the Zotino board is a 16–bit one, what was needed to be done here, was to ensure that

output data delivered to the DAC module was 2 bits wider than ASF. The filter’s output

value changes accordingly to the output vector’s widening, since its construction allows

the data to be even 25 bits wide. Widening of the vector was achieved by enabling the

filter to output signed values and by changing the number of bits, by which data was

shifted on its way out. The structure of the IIR filter, after changes described above being

applied, is presented in figure 4.4. Clipping, to either maximum or minimum value the

31


two’s complement representation, plays the role of anti–windup protection and, what is

more, prevents the output signal from overflowing.

Figure 4.4: Structure of the IIR filter described inside the IIR module

The filter’s output signal for each channel (profile) is 64 bits wide and consists of ASF,

POW, FTW1 and FTW0 values— from the most significant to the least significant bits.

4.2.4. Control over digital to analog converter

The control over the digital to analog conversion takes place on two levels of abstrac-

tion. To the higher layer belongs the DAC module, which extracts information about the

target voltage, frames it with additional data and sends it to the lower–level controller —

SPI module. It, on the other hand, provides the PID regulator with transmission over data

lines adjusted to the Zotino’s IC requirements.

4.2.4.1. SPI module

SPI module is responsible for low–level communication with an integrated circuit that

performs digital to analog conversion (IC used on Zotino board is AD5372BCPZ [52] from

Analog Devices). Although the protocol used by the IC is described as a Serial Peripheral

Interface (hence the module’s name SPI) protocol, there are a few additional signal lines

used. However, it is the controller of the higher level — DAC module — that makes use of

those extra lines and from the SPI module’s perspective, it may be considered as a standard

SPI protocol. SPI module block schematic is shown in figure 4.5.

The module’s input ports consist of spi_start and dataSPI bus; width of the latter is

parameterized and equal to the data_width field of params tuple, that is passed as an

argument to the module’s constructor.

The module’s output ports fall into two categories: the ones that are used to com-

municate with other components inside the FPGA, and the ones used to drive data lines

connected to external devices. To the former category belongs spi_ready, which indicates

that the module is ready to accept new data and send them to the IC, whereas to the latter

belong ports labelled as pads. During ongoing data transmission, serial clock signal —

which is required to be slower than 50 MHz [52] — is sent to slave device over pads.sclk

line. When data transmission is over, pads.sclk line is kept low. Data received over dataSPI

32


Figure 4.5: SPI component’s block diagram with input and output ports

line is latched and stored as a vector, and when start event is issued, vector’s content is

serialized and sent over pads.sdi line, most significant bit first. Pads.syncr line is used to

frame the data sequence — when driven low, pads.sdi and values are valid and should be

checked by the DAC on pads.sclk’s every falling edge. After every 24th bit sent, pads.syncr

has to be driven high for at least 20 ns, for the transmission to be accepted. Otherwise,

data would be recognized as corrupted and transmission would not be accomplished.

The SPI’s control over the transmission is implemented using a finite state machine

that has three states: IDLE, SETUP and HOLD.

When in the IDLE state, the SPI module drives both pads.syncr and spi_ready pins

constantly high. Whenever spi_start pin is issued, data from dataSPI is latched into the

shift register and the FSM’s state is changed to SETUP. Moreover, the counter responsible

for the clock_enable signal is launched. Its highest value is parameterized and equal to the

params.clk_width field. Each FSM state is entered on the rising edge of the FPGA’s clock,

but only if clock_enable condition is satisfied. It allows manipulating state’s duration and

the frequency of the clock sent to the IC. In addition, during the IDLE state, bits signal,

which is another counter that provides with information of how many bits are still to be

sent, keeps the value of data_width-1. During the SETUP state, pads.syncr is driven low

and the module enables the output clock. When the clock_enable signal is active, FSM

changes state to HOLD. Each time FSM enters the HOLD state, the number of bits inside

the shift register is checked, and if there are no bits left to be transmitted, the module

switches back to the IDLE state. Otherwise, the SPI module shifts data inside the shift

register by one position, decreases the bits counter by one and then, having launched

clock_enable counter, it switches back to SETUP state. Disabling the pads.sclk output takes

place in that state as well. This means that data on pads.sdi line is currently valid, because

IC collects data on each falling edge of the clock line. Because the DAC requires at least 10

ns of a delay between the 24th bit’s falling edge and the pads.syncr rising edge for data not

to be corrupted, going back to IDLE state is possible only when clock_enable is asserted.

When using the SPI module, one has to bear in mind that pads.syncr line has to be

33


driven high for at least 20 ns. Therefore, the spi_start cannot be constantly tied high,

because the FSM would leave the IDLE state too soon and the IC would not recognize

data correctly. The control over that timing is not done inside this module — it is the DAC

module that takes care of it.

Listing 4.3 shows how to define the FSM in Migen and how the signals in the SPI

module’s IDLE state are driven. Each finite state machine has to be assigned as one of the

object’s submodules. In the first combinatorial statement the clock_enable signal is added

to the FSM, so this condition is checked in each state automatically.

Listing 4.3: Example of definition and one state of FSM

self .submodules.fsm = fsm = CEInserter()(FSM("IDLE"))

self .comb += fsm.ce.eq(clk_cnt_done)

self .comb += pads.sdi.eq(sr_data[−1])

fsm.act("IDLE",

self .spi_ready.eq(1),

pads.syncr.eq(1),

If ( self .spi_start,

NextState("SETUP"),

data_load.eq(1),

cnt_load.eq(1)

)

)

4.2.4.2. DAC module

DAC module performs three, equally significant, tasks: it derives information about

the voltage to be set from profile signal, wraps it in additional information regarding target

channels, and controls the SPI component. What is more, it coverts derived information

about the output voltage from the two’s complementary to the binary representation. If

it was not for this action, voltages on the Zotino’s output pins would not be set correctly.

DAC’s block diagram with input and output ports is shown in the figure 4.6.

Figure 4.6: Block diagram of DAC module

34


Dac_start and dac_init ports are used by the master controller — in this case Servo

module — either to begin the DAC’s operation and data transmission to the Zotino board

or to perform initialization of the DAC’s IC. As soon as the controller drives the dac_init

signal high and the device has not yet been initialized, the SPI module sends a data

sequence that calibrates the DAC’s OFS0 register and sets dac_initialized high to let the

controller know that initialization is not needed any more. DAC begins its operation when

dac_start pin is driven high, and after transmission to all used channels has ended, it

drives dac_ready pin high. DAC component adds to the SPI output ports pads.ldac signal

— it has to be driven high only during initialization and is permanently tied low afterwards.

Similarly to the SPI module, DAC driver is implemented using FSM. What is more,

it only has three states as well: IDLE, INIT and DATA. When in IDLE state, dac_ready

pin is constantly asserted and module’s next state depends on dac_start and dac_init

pins. To ensure that SPI module’s pads.syncr pin is driven high long enough for the DAC

to recognize framing, timing control is implemented using a counter. It counts down

the clock cycles needed for a valid transmission — the number of bits to send times

params.clk_width times 2, plus 4 clock cycles. The additional four cycles are required for

the SPI to remain in IDLE state and drive pads.syncr line. When the dac_start is set, the

counter is launched and the FSM’s sate is changed to DATA. During ongoing IDLE state,

data from the profile bus is latched in a shift register, information about target channels is

added to it, and the word counter, that indicates how many words remain inside the shift

register, is set to the number of used channels. When in DATA, every time the number of

the clock cycles needed for one SPI transmission has elapsed, the number of words in the

shift register is checked. If there are still words to be sent, the counter is launched and the

words inside the shift register are shifted by the width of a single word. If all the data has

been sent and the shift register is empty, FSM switches back to the IDLE state. Every time

cycle counter is launched, the DAC module sets spi_start pin on the next clock’s rising

edge for the duration of one clock cycle.

Shifting data received from the IIR module, however, is needed. The ADC IC delivers

data in two’s complement 16–bit–wide representation. Even though the DSP block used by

FPGA handles two’s complementary operations smoothly, DAC IC requires data to be in

the binary representation. Thus, adding half of the range achievable on signal’s width was

done — thanks to overflow occurring when adding to the signed values, a shifted values

are obtained.

4.2.5. Pin assignment and signals conversion

Each pads module’s constructor takes two values as arguments: eem and platform.

The former one indicates the name of the board used by the module and the number of

EEM connector the board is connected to; the latter one marks the target platform on

which the program is to be executed. Passing them as arguments allows for the design to

be portable across different hardware setups and controller boards. Each of the platforms

35


supported by Migen has a request method, that takes the name of the requested I/O tuple

as an argument and allows to gain access to its peripheral signals and pins used by the

FPGA. To illustrate how the board’s connectors and pins assignment are structured in

Migen, Zotino’s connector tuple is shown in listing 4.4

Listing 4.4: Example of Zotino’s I/O tuple structure

("zotino{}_spi_p".format(eem), 0,

Subsignal("clk", Pins(_eem_pin(eem, 0, "p"))),

Subsignal("mosi", Pins(_eem_pin(eem, 1, "p"))),

Subsignal("miso", Pins(_eem_pin(eem, 2, "p"))),

Subsignal("cs_n", Pins(_eem_pin(eem, 3, "p"))),

IOStandard(iostandard),

) ,

("zotino{}_spi_n".format(eem), 0,

Subsignal("clk", Pins(_eem_pin(eem, 0, "n"))),

Subsignal("mosi", Pins(_eem_pin(eem, 1, "n"))),

Subsignal("miso", Pins(_eem_pin(eem, 2, "n"))),

Subsignal("cs_n", Pins(_eem_pin(eem, 3, "n"))),


) ,

I/O tuple consists of the peripheral’s name, identity number, set of Subsignals and IOStan-

dard. Identity number allows to distinguish different instances of the same peripheral

— for example, different light–emitting diodes (LEDs). Thanks to the Subsignal helper

class, resources that use FPGA’s pins may be arranged in an easy to read way. What is

more Subsignal’s constructor structure is identical to I/O tuple, with the identity number

omitted. It allows to gain access to the FPGA’s specific pin to by using signals name. Finally,

IOStandard indicates the logic standard used by FPGA to drive those pins. A method of

requesting access to peripheral’s pins is presented in listing 4.5.

Listing 4.5: Example of the request method usage

spip = platform.request("{}_spi_p".format(eem))

spin = platform.request("{}_spi_n".format(eem))

ldacn = platform.request("{}_ldac_n".format(eem))

busy = platform.request("{}_busy".format(eem))

clrn = platform.request("{}_clr_n".format(eem))

As shown in listing 4.5, there are two I/O tuple instances of the close resemblance. This

is because each of the tuples corresponds to the polarity of the FPGA pins they drive. Thus,

there are four SPI lines connected to negative–polarity pins and four lines connected to

positive–polarity pins.

After pins are requested and accessed, a conversion from single–ended signals to

differential signalling is done. As mentioned in section 4.2.1, Migen creators developed

classes that aim to perform that task easily: DifferentialInput, DifferentialOutput and

DDROutput. Each of their constructor’s argument list consists of single–ended signal and

36


two pins that are to be driven by the signal. Access to these pins by their name has to be

gained prior to the conversion with the request method.

Exemplary usage of conversion classes is shown in listing 4.6.

Listing 4.6: Conversion of single–ended signals to differential signalling

self .specials += [

DifferentialOutput(self.ldac, ldacn.p, ldacn.n),

DifferentialOutput(self.sdi, spip.mosi, spin.mosi),

DifferentialOutput(self.sclk, spip.clk, spin.clk),

DifferentialOutput(self.syncr, spip.cs_n, spin.cs_n),

DifferentialOutput(self.clr, clrn.p, clrn.n),

DifferentialInput(busy.p, busy.n, self.busy),

]

4.2.6. Servo module

The module that integrates all of the parts described above and is in charge of launch-

ing its every submodule is the Servo module. It has two pins to communicate with a

potential controller of higher level: start, which, when driven high, begins Servo single

iteration — reading the ADC channels’ values, processing them and then setting DAC

outputs accordingly, and done, which signals that Servo’s iteration has been completed.

The overall control of the data flow and four submodules, that communicate with

external Sinara boards, and connection of ADC, IIR and DAC channels to each other is

done by Servo’s logic. What was needed to be taken into consideration when having

planned assignments, was the fact, that the order of the channels had been reversed on

the Sampler board. To restrain latency introduced by the Servo’s components, sampling

of the ADC channels begins a precise amount of time before the processing and sending

data to DAC finishes. It allows the ADC to convey samples just in time the IIR and DAC

modules are ready for the next transmission.

The data flow and behaviour of components are defined inside Servo’s synchronous

and combinatorial statements: events that trigger components are combinatorial, whereas

asserting components’ readiness and the current state is done synchronously. Therefore,

components’ states are checked every time a rising edge of the Kasli’s internal clock

happens and action that results from those states occurs on the next rising slope. To

illustrate the difference between combinatorial and synchronous assignments, a simple

assignment of two variables was done — their timing dependencies are presented in figure

4.7 (both signals’ values are assigned when the condition signal is asserted).

The components’ states are stored inside the three–bits–wide Signal named active —

each bit corresponds to the current status of each device: third bit to DAC module, second

to the IIR module and the first bit to the ADC module. Whenever a component finishes

its task, Servo changes active bit in accordance with the action performed, provided the

37


Figure 4.7: Example of synchronous and combinatorial assignments

Servo iteration has been issued. Each device is dependent on particular conditions that

have to be satisfied in order for it to operate:

• ADC begins sampling and data transfer to the Kasli, only if both Sampler’s PGIAs and

DAC are already initialized, the Servo iteration has been issued, filter coefficients

have been already written to the IIR’s memory and the amount of time for the IIR

and DAC modules to finish their current operation is sufficient;

• IIR module begins operation only if ADC is ready (it either has already sampled

signals or it did not start any action at all) and when the ADC start event has been

issued;

• DAC module starts transmission to the Zotino board only if IIR start event has been

issued and the IIR module either is currently in shifting phase or has already finished

operation.

Because initialization of DAC and PGIAs as well as writing the filter coefficients into

the IIR module’s memory is mandatory before the control loop starts, it is the first thing

the Servo module does when launched.

In addition to the logic described above, a function coeff_to_mu, that allow to convert

PID coefficients from the form used in equation 1.1 to the digital IIR filter coefficients

from equation 1.5, was implemented. The number of channels used by the PID controller

determines how many times the coeff_to_mu function is invoked. After invoking the

function, its results are passed as arguments to the IIR module’s constructor, where it is

written into the coefficient memory.

To ensure that all values and signals are settled after the FPGA’s initialization, the

beginning of the Servo’s operation has to be delayed. Therefore, a counter that counts

down the clock cycles from the specified in the Servo module amount. When it reaches

zero, the start_done line is asserted which is necessary for any other action, such as

initializing PGIAs or writing coefficients to the IIR module’s memory.

38

5. Tests and measurements

After the design process was finished, tests and measurements were conducted to

find out whether the implemented PID controller works properly. To ensure that each

of the controller’s terms — proportional, integral (and in case of ARTIQ implementation,

derivative as well) — functions as planned, they were tested separately, at first. If their

assessment result was positive, they were combined to form the whole PI controller, which

was then examined.

Since PID controller tuning is outside of this thesis scope, each of the coefficients, that

were used during tests of individual controller’s terms, was chosen arbitrarily — just to

illustrate that the regulator works as designed and demonstrate its features. However,

to conduct tests of the controller as a whole, a method proposed by Karl Johan Åström

in [53] to calculate the controller’s coefficients was followed. It is a modified version

of an open–loop Ziegler-–Nichols tuning method [54] with a few adjustments for use

with digital implementations, in which delay introduced by sampling period has to be

taken into account. Even though the Ziegler–Nichols method provides only moderately

good tuning [53], it allows to calculate regulator’s coefficients easily by taking only a few

measurements. The PID coefficients used during the controller’s testing can be found in

table 3.

Table 3: PID controller’s coefficients used during device testing

ARTIQBare–metal Test type

With conversion Without conversion

KP 2 2 2

P–T

ER

M

K I 0 0 0

KD 0 0 —

KP 0 0 0

I–T

ER

M

K I 2 2 2000

KD 0 0 —

KP 0 0 0

D–T

ER

M

K I 0 0 0

KD 5 5 —

KP 0.0048 0.0072 0.1007

PIK I 1.8415 4.3617 839.19

KD — — —

39


5.1. Testing procedure

In order to conduct each term’s unit test, the devices used during this thesis project

— the Kasli controller, the Zotino and the Sampler boards — and measuring equipment

were set up as shown in figures 5.1 and 5.2. It is essential to emphasize that each test and

measurement was performed with the control loop being open and the oscilloscope being

connected as a plant. The stimulus signal from the function generator played the role of

the process setpoint. However, since the loop was open and the error could not decrease

due to the controller’s action, the error signal was equal to the setpoint. Therefore, these

two terms are used interchangeably from now on.

Figure 5.1: Block schematic of the test setup

To ensure that the setpoint was within the regulator’s bandwidth and to prevent the

controller from saturating, sample rate for each controller’s implementation was estimated.

As a result, the signal fed to the Sampler board was set to the frequency of 100 Hz and

the amplitude (peak–to–peak) of 2 volts. The function generator, connected to the tested

hardware with a BNC cable, was set to produce sinusoidal wave (tests of the proportional

term), square wave (tests of the integral and the derivative actions) and a step change

(to calculate controller’s coefficients using the method suggested by Karl Johan Åström).

40


The oscilloscope and the test probe were used to observe the regulator’s response to the

stimulus signal and to take measurements.

Figure 5.2: Photograph of the test setup

Having established that all the terms worked as designed, the examination proceeded

to the phase of testing the PI controller as a whole. The test setup was identical to the one

presented in figures 5.1 and 5.2. However, during this phase, the regulator responses to

setpoint’s rapid changes were studied, instead of its waveform’s shape.

To examine the controller’s response to a sudden change of the setpoint, a voltage step

change was applied to the Sampler’s input. In the similar way the controller’s response to

the voltage spike on its input was studied. Because controller tuning has a great impact on

the system’s response, to avoid its influence the latency measurements were performed

with the integral term set to 0. Moreover, control system’s bandwidth heavily depends on

the controller coefficients as well. Thus measuring the implemented regulator’s frequency

response with precise instruments such as a vector network analyzer would not be a

sensible thing to do. Instead, the controller’s bandwidth was estimated from its multiple

responses to the step change.

In each of the figures presented below, the first trace shows the setpoint waveform,

whereas the second trace presents the control variable at the output of the Zotino board.

41


5.2. Tests of the ARTIQ–based implementations

ARTIQ–based implementations sample rates were estimated using the ARTIQ core’s

real–time input/output (RTIO) counter which counts the FPGA’s clock cycles. It allowed

retrieving absolute timestamps of the events associated with the beginning and the end

of the control cycle and computing their difference, which was the sample rate. Having

applied the sampling theorem [55], the system’s bandwidth was obtained and estimated.

5.2.1. Implementation with immediate conversion to volts

Proportional term

As shown in figure 5.3, the control variable’s amplitude is almost twice as big as the error

signal’s. This indicates that the proportional term works properly, as the ratio of output

and input signals stays in accordance with the gain coefficient specified in table 3. What

is worth noticing, is the fact that even though the wave’s frequency is relatively low —

only 100 Hz — the phase shift introduced by the controller to the controlled signal is not

negligible and visible with the bare eye..

Figure 5.3: Setpoint and control variable — test of the proportional term

Integral term

Since integral part of the PID regulator eliminates steady–state error by adding error

signal’s values from the past to the current sample, it may cause the CV to drift with

time due to the additional offset introduced by either the Sampler or the Kasli controller.

Therefore, to see the full CV’s waveform on the oscilloscope screen, the coupling was set

to AC (alternating current) when the regulator’s integral term was term was undergoing

testing.

42


In figure 5.4 the CV waveform is shown. It takes the form of a ramp signal, which is

the expected result of adding previous sampled values to each other. The flat parts of the

output waveform are the effect of anti–windup protection. If it had not been implemented,

the controller would not stop integrating and would try to set its output voltage to the

value that is beyond the hardware limits. Only two examples of this effect are indicated

with arrows in figure 5.4 to keep the its clarity.

Figure 5.4: Setpoint and control variable — test of the integral term

Derivative term

The controller’s derivative action is shown in figure 5.5. Similarly to its mathematical

model, it is a measure of how fast the function values change in a response to the function’s

arguments. Thus it forms a spike every time the setpoint is rapidly changed and stays at

the steady–state position in case no SP’s change occurred within the last sampling period.

Similarly to figure 5.3, the influence of the sampling period can be observed — the voltage

spikes lag a certain amount of time behind the setpoint’s change. However, it does not

prevent the controller’s derivative term from setting control variable properly.

43


Figure 5.5: Setpoint and control variable — test of the derivative term

PI controller

Figures 5.6, 5.7 and 5.8 present the PI controller responses to the impulse (100 µs

duration) and the step stimulation and measurements of the average latency, respectively.

What the testing revealed was that the regulator did not recognized the impulse and did

not respond to it at all. It is most likely the result of the controller’s bandwidth being too

small.

Figure 5.6: The controller impulse response

44


Figure 5.7: The controller step response

However, as shown in figure 5.7, a step change caused the PI controller’s reaction. Hav-

ing detected the voltage step, the regulator started integration. After it reached the point

of maximum voltage output, further integration was stopped thanks to the anti–windup

protection.

Figure 5.8: The controller average latency

The controller overall latency consists of not only the delay introduced by sampling,

processing data and communication with the DAC, but also of the delay caused by the

different moments of sampling the error signal. To include the latter’s influence, the

latency was measured from the moment when the setpoint changed to the average point

of time when the regulator responded. What is more, the deviation of the signal from

45


this point of time is equal to the controller’s sampling period. Having obtained this

parameter allowed calculating the regulator’s bandwidth. As a result, the average latency of

approximately 600 µs was measured and the bandwidth of around 1.2 kHz was calculated.

5.2.2. Implementation without conversion to volts

Giving up the conversion from machine units to volts allowed to spare some time

when it comes to the controllers sampling period. However, the results of each term’s

measurements are similar to those obtained during testing the implementation with the

immediate conversion to volts, and therefore are not extensively discussed. As presented

in figures 5.9–5.11 every part of the controller performs its tasks properly. What is worth

mentioning is that thanks to the improved bandwidth, the controller’s dead time — the

amount of time that has to elapse before the controller responds to the setpoint’s change

— decreased. Moreover, phase shift decreased as well. It is easily seen in figure 5.9, though.

The measurements of the controller’s step response resulted in calculating the con-

troller’s bandwidth: approximately 2.4 kHz, and its average latency: around 340 µs. In-

creased bandwidth and decreased latency can be observed in figure 5.11 as well — the

spikes caused by the derivative term are thinner and closer to the setpoint changes.


Although the regulator’s bandwidth increased, the change that was not big enough

for the PI controller to respond to the generated impulse signal and its impulse respone

matches the one presented in figure 5.6. The PI controller, similarly to the one from the

previous subsection, reacted on the step change of the input signal. Here as well, the

anti–windup protection worked and the regulator reacted almost instantly in spite of being

at rail for some time. It is illustrated by the waveform in figure 5.12.

46



Figure 5.11: Setpoint and control variable — test of the derivative term

47




48


5.3. Tests of the bare–metal implementation

Estimating the bare–metal implementation’s bandwidth required other approach than

the previous two. Control over the PI regulator from the ARTIQ level was not possible and

integration with the ARTIQ core’s RTIO had not been implemented either. Therefore, a

time of one servo cycle, which was calculated during the Servo module implementation

(see section 4.2.6) was used.

To compile and run the implementation, main and eem2 files were created. These

files served the purpose of the Servo module declaration and gaining access to the EEM

connectors associated with Zotino and Sampler. Listing 5.1 shows how the FPGA’s clock

buffer was accessed and assigned to the module’s clock signal. It presents how to build

the design as well. The code used for the bare–metal implementation testing is placed in

Appendix 2.1 and Appendix 2.2.

Listing 5.1: Example of clock signal assignment and build command

clk125 = plat.request("clk125_gtp")

m.specials += [

Instance("IBUFDS_GTE2", i_I = clk125.p, i_IB = clk125.n, o_O = clk_signal),

Instance("BUFG", i_I = clk_signal, o_O = servo.cd_sys.clk)

]

plat.build(servo, run=True, build_dir = "building/pid/{}ch/pgia{:0>4x}/Kp_{}_Ki_{}".format(

channels_no, pgia_init_val, Kps[0], Kis[0]), build_name = "top")

Proportional term

The improvement of controller’s action can be realized immediately — the waveform

generated by the proportional term is shown in figure 5.14. In this case, the controller

did not introduced any significant phase shift, while being fed with the error signal of the

frequency of 100 Hz. What is more, the amplification of the input signal by the factor of 2

was preserved.

Integral term

The integral action’s test result was positive, as well. As shown in figure 5.15, its response

to the square–shaped error signal was, however, much smoother than the responses of

the previous two implementations. It was achieved thanks to the controller’s much higher

sample rate.

49




PI controller

Contrary to the both ARTIQ–based implementations, the bare–metal one successfully

detects the short impulse and generates a response based on that input. This, however,

may be of ambivalent significance. On one hand, it demonstrates that the bare–metal

implementation has the higher bandwidth than the ARTIQ–based ones. On the other hand

it may be sensitive to undesirable external disturbances. Application of filters on the input

50


of the PID controller should solve this problem when it occurs. The controller’s response

to the impulse is presented in figure 5.16, while its response to the step change in figure

5.17. What is of the extreme importance is the fact, that the controller reacts to the error

signal’s change almost immediately.

Figure 5.16: The controller impulse response


As a result of the measurements shown in figure 5.18, the controller’s bandwidth of

approximately 15.6 kHz and its average latency of around 31 µs were calculated. It is more

than tenfold improvement in terms of the latency in comparison with the best of two

ARTIQ implementations, and about fivefold in terms of the available bandwidth.

51



5.4. Tests and measurements summary

Tests conducted on different PID controller implementations have shown that they

are able to provide at least the proportional–intergral type of control. The most important

parameters of each regulator, such as its bandwidth or latency, were measured and are

presented in table 4. What was realized is that the best control should be provided by

the PI regulator implemented as a bare–metal controller — its measured results were

significantly better than the other two’s. Since all the implementations are using the same

hardware and the same connections, this difference is a result of the ARTIQ software

working above the Kasli controller — it does not allow to fully exploit advantages of ADC

and DAC integrated circuits at the moment.

Table 4: Comparison of implementations’ parameters

ARTIQBare–metal

With conversion Without conversion

Bandwidth ≈1.2 kHz ≈2.4 kHz ≈15.6 kHz

Sampling period ≈400 µ s ≈200 µ s ≈32 µ s

Latency ≈600 µs ≈340 µs ≈31 µs

52

6. Conclusion and thesis summary

During this thesis project a new PID controller was developed. The first two stages

involved a pure software implementation of the regulator. This way of implementing

the proportional–integral–derivative controller’s functionality, in both cases resulted in

regulator’s small bandwidth. The second approach involved developing a PID controller,

as well, but rather directly in FPGA’s logic than in software. Its outcome should be seen

as a successful end of a project, since the controller’s bandwidth is of 15 kHz order of

magnitude. This implementation, however, could have been even more promising, if

some other DAC integrated circuit had been installed on the Zotino board. As stated in

IC data sheet [52], it needs more than 30 µs to settle its output before new data may be

processed, which makes it the main limiting factor to the regulator’s bandwidth.

What has to be taken into account is, however, the fact that the achieved bandwidth

does not guarantee the closed–loop control to operate at such high sample rates. The phase

shift, which was clearly visible with the bare eye in both ARTIQ–based implementations,

would probalby limit the system’s bandwidth.

From the three implementations, the last one — the bare–metal implementation

— has been shown to offer the best performance for a control loop. What is more, its

only disadvantage in comparison to the previous to, is the lack of the derivative part,

which, however, had not been required by the technical assumptions and is an acceptable

trade–off for the higher bandwidth and much smaller average latency.

All of the requirements set in section 2 has been fulfilled: the PID controller is run on

the Sinara hardware and has been developed using either ARTIQ or Migen; anti–windup

protection has been implemented and proved to perform its task properly in every im-

plementation. The process is driven directly with voltage using the Zotino board, which

allows setting the control variable in the range of ±10 V. The error signal is sampled by

the Sampler board, which is capable of accepting data in the voltage range of ±10 V as

well. Achieved bandwidth and latency are better than required — even in the worst case

scenario.

The devices used during this thesis projet can be put inside the rack for user’s conve-

nience, as shown in figure 6.1.

6.1. Further work

Although the controller is proved to be working and can be used to control laser sources

already, the most effective implementation’s application can cause some troubles for many

inexperienced users because its usage requires the knowledge on how to flash binaries

into the FPGA’s memory. What is more, the usage of the implemented PID controller

prevents the user from performing anything else on Sinara core. Therefore, the next step

of development should be to incorporate the bare–metal implementation into the ARTIQ.

53


Figure 6.1: Photograph of the hardware setup used in thesis project

It would allow using all of the hardware available, with the PID control loop running in

background. The development could go even further and the bare–metal implementation

could be adjusted to perform control loop on eight channels independently with little

effort.

In figure 6.2 the hardware setup used at Humboldt University of Berlin for performing

quantum physics experiments is presented. The connections are made with a laser source

to drive it with the control loop and with the PFD to sample the error signal. With the

dashed line the Sinara hardware family is marked.

54


Figure 6.2: Photograph of the hardware setup at HUB

55

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List of Symbols and Abbreviations

ADC – Analog–to–Digital Converter

AOM – Acousto–Optic Modulation

ARTIQ – Advanced Real–Time Infrastructure for Quantum physics

ASF – Amplitude Scale Factor

BS – Beam Splitter

BEC – Bose–Einstein Condensate

CERN OHL – CERN Open Hardware License

CFG – Configuration register

CPU – Central Processing Unit

CV – Control Variable

DAC – Digital–to–Analog Converter

DDS – Direct Digital Synthesizer

DIO – Digital Input/Output

DRTIO – Distributed Real Time Input/Output

DSP – Digital Signal Processing

EEM – Eurocard Extension Module

FIFO – First In, First Out

FIR – Finite Impulse Response

FPGA – Field–Programmable Gate Array

FSM – Finite State Machine

FTW – Frequency Tuning Word

GUI – Graphical User Interface

HUB – Humboldt University of Berlin

IC – Integrated Circuit

IIR – Infinite Impulse Response

I/O – Input/Output

JILA – Joint Institute for Laboratory Astrophysics

JTAG – Joint Test Access Group

LED – Light–Emitting Diode

LO – Local Oscillator

LP filter – Low–Pass filter

LVDS – Low-Voltage Differential Signalling

MOT – Magneto–Optical Trap

NIST – National Institute of Standards and Technology

PFD – Phase–Frequency Detector

PGIA – Programmable–Gaine Instrumentation Amplifier

PI – Propotional–Integral

PID – Propotional–Integral–Derivative

61

POW – Phase Offset Word

PV – Process Variable

QCCS – Quantum Computing Control System

QOM – Optical Metrology Group

QSPI – Quad SPI

RAM – Random–Access Memory

RF – Radio Frequency

RPC – Remote Procedure Call

SPI – Serial Peripheral Interface

USB – Universal Serial Bus

VHDL – Very High Speed Integrated Circuit Hardware Description Language

VLSI – Very Large–Scale Integration

List of Figures

1.1. Simplified frequency offset locking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2. A generic closed feedback control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3. QCCS modules; image taken from [32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.4. Example of Sinara family devices’ setup in a crate; image taken from [43] . . . . . . . . . 18

2.1. Block schematics of the controlled process . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1. Block schematic of the system used in the thesis project and their connections . . . . . . 23

4.1. Block diagram of Servo and its submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2. PGIA module’s block diagram with input and output ports . . . . . . . . . . . . . . . . . . 29

4.3. Module’s coefficient memory layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.4. Structure of the IIR filter described inside the IIR module . . . . . . . . . . . . . . . . . . . 32

4.5. SPI component’s block diagram with input and output ports . . . . . . . . . . . . . . . . . 33

4.6. Block diagram of DAC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.7. Example of synchronous and combinatorial assignments . . . . . . . . . . . . . . . . . . . 38

5.1. Block schematic of the test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.2. Photograph of the test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.3. Setpoint and control variable — test of the proportional term . . . . . . . . . . . . . . . . 42

5.4. Setpoint and control variable — test of the integral term . . . . . . . . . . . . . . . . . . . 43

5.5. Setpoint and control variable — test of the derivative term . . . . . . . . . . . . . . . . . . 44

5.6. The controller impulse response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.7. The controller step response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.8. The controller average latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.9. Setpoint and control variable — test of the proportional term . . . . . . . . . . . . . . . . 46


5.11. Setpoint and control variable — test of the derivative term . . . . . . . . . . . . . . . . . 47

5.12. The controller step response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.13. The controller average latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.14. Setpoint and control variable — test of the proportional term . . . . . . . . . . . . . . . 50

62


5.16. The controller impulse response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.17. The controller step response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.18. The controller average latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1. Photograph of the hardware setup used in thesis project . . . . . . . . . . . . . . . . . . . 54

6.2. Photograph of the hardware setup at HUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

List of Tables

1. Dependency of IIR filter’s coefficients on PID conroller’s coefficients . . . . . . . . . . . . . 15

2. Summary of existing control systems features . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3. PID controller’s coefficients used during device testing . . . . . . . . . . . . . . . . . . . . . 39

4. Comparison of implementations’ parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

List of Appendices

1. Details on the used boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2. Code used for tests and measurements . . . . . . . . . . . . . . . . . . . . . . . . . 77

63

Appendix 1. Details on the used boards

Appendix 1.1. Details on Sampler

According to the Sampler project page [49], the board itself ‘is an 8-channel, 16-bit

ADC EEM with an update rate of up to 1.5MSPS (all channels simultaneously). It has

low-noise differential front end with a digitally programmable gain, providing full-scale

input ranges between +-10mV (G=1000) and +-10V (G=1).’

What is more, the Sampler’s key features are [49]:

• ‘Current hardware revision: v2.2

• Width: 8HP

• Channel count: 8

• Resolution: 16-bit

• Sample rate: up to 1.5 MHz

• Sustained aggregate data rate in single-EEM mode (8 channel readout): 700 kHz

• Sustained per-channel data rate in dual-EEM mode (SU-Servo): 1 MHz

• Note that the bandwidth specifications on this page are for the hardware only; ARTIQ

kernel and RTIO overhead often make the effective sample rate lower.

• Bandwidth: 200kHz -6dB bandwidth for G=1, 10, 100, 90kHz for G=1000

• Input ranges: +-10V (G=1), +-1V (G=10), +-100mV (G=100), +-10mV (G=1000)

• DC input impedance:

— Termination off: 100k from input signal and ground connections to PCB ground

— Termination on: signal 50Ohm terminated to PCB ground, input ground shorted

to PCB ground

• ADC: LTC2320-16

• PGIA: AD8253

• EEM connectors: power and digital communication supplied by one or two EEM

connectors.’

Furthermore, the Sampler can operate in one of the two modes: as a standard SPI

device, or in a fast mode via a source–synchronous LVDS interface [49]. According

to the Sampler wiki page, the Sampler’s channels can be read out at 1.5 MHz via the

source–synchronous interface.

64

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IN_1

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IN_0

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IN_3

_P

IN_4

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IN_5

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IN_6

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REF

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OE

13R

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12

SER

14

SRC

LR10

SRC

LK11

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15Q

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2Q

D3

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4Q

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7

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LV59

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PGIA

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PGIA

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15

QB

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T

P3V

3

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D

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PGIA

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PGIA

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P3V

3

P3V

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1

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0_A

0C

H0_

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CH

2_A

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H2_

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3_A

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H3_

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CH

4_A

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H4_

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CH

5_A

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H5_

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H6_

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CH

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TER

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]

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D

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C57

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D

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3

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CLI

P2

GN

D

1

CLI

P3

GN

D

1

CLI

P4

GN

D

1

CLI

P5

GN

D

1

CLI

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GN

D

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LIP7

GN

D

1

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P9

GN

D

1

CLI

P10

GN

D

1

CLI

P11

GN

D

1

CLI

P12

GN

D

1

CLI

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4

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CLI

P15

GN

D

1

CLI

P16

GN

D

1

CLI

P17

GN

D

1

CLI

P18

GN

D

1

CLI

P19

GN

D

1C

LIP2

0

GN

D

1

CLI

P8

GN

D

1

CLI

P21

GN

D

1

CLI

P22

GN

D

1

CLI

P23

GN

D

1

CLI

P24

GN

D

1

CLI

P25

GN

D

1

CLI

P26

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

J1

P13V

0N

13V

0

R3U

ndefined

R6

Undefined

shie

ld c

lips

PGIA

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TER

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TER

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TER

M_S

TAT2

TER

M_S

TAT3

TER

M_S

TAT4

TER

M_S

TAT5

TER

M_S

TAT6

TER

M_S

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AD

C_I

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1

AD

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2

AD

C_I

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3

AD

C_I

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4

AD

C_I

N_P

5

AD

C_I

N_P

6

AD

C_I

N_P

7

AD

C_I

N_N

1

AD

C_I

N_N

2

AD

C_I

N_N

3

AD

C_I

N_N

4

AD

C_I

N_N

5

AD

C_I

N_N

6

AD

C_I

N_N

7

AD

C_I

N_P

0A

DC

_IN

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41

BO

T

J3A

BN

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TOP

J3B

BN

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T

J4A

BN

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TOP

J4B

BN

C 41

BO

T

J5A

BN

C 23

TOP

J5B

BN

C 41

BO

T

J6A

BN

C 23

TOP

J6B

BN

C

CH

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H0_

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H1_

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CH

2_A

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H2_

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CH

3_A

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H3_

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CH

4_A

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H4_

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CH

5_A

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H5_

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CH

6_A

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H6_

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CH

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VD

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LVD

S_IF

CB

.Sch

Doc

PGIA

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IA-M

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PGIA

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KPG

IA-C

S

REF

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048

REF

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7066

P3V

3

P3V

31%R58 220 1%R59 220

P3V

3

P3V

31%R60 220

1%R61 220

P3V

3

P3V

31%R62 220

1%R63 220

P3V

3

P3V

31%R64 220

1%R65 220

TER

M_S

TAT0

TER

M_S

TAT1

TER

M_S

TAT2

TER

M_S

TAT3

TER

M_S

TAT4

TER

M_S

TAT5

TER

M_S

TAT6

TER

M_S

TAT7

D

S

G

T1B

SS138LT1G

GN

D

D

S

G

T2B

SS138LT1G

GN

D

D

S

G

T3B

SS138LT1G

GN

D

D

S

G

T4B

SS138LT1G

GN

D

D

S

G

T5B

SS138LT1G

GN

D

D

S

G

T6B

SS138LT1G

GN

D

D

S

G

T7B

SS138LT1G

GN

D

D

S

G

T8B

SS138LT1G

GN

D

Gre

en

BO

TLD

1A

Gre

en

TOP

LD1B G

reen

BO

TLD

2A

Gre

en

TOP

LD2B G

reen

BO

TLD

3A

Gre

en

TOP

LD3B G

reen

BO

TLD

4A

Gre

en

TOP

LD4B

IN_N

A0

A1

IN_P

TER

M_I

ND

AD

C_I

N_N

AD

C_I

N_P

REF

_P2V

048

REF

_P1V

7066

U_I

nput

_cha

nnel

Inpu

t_ch

anne

l.Sch

Doc

IN_N

A0

A1

IN_P

TER

M_I

ND

AD

C_I

N_N

AD

C_I

N_P

REF

_P2V

048

REF

_P1V

7066

U_I

nput

_cha

nnel

Inpu

t_ch

anne

l.Sch

Doc

IN_N

A0

A1

IN_P

TER

M_I

ND

AD

C_I

N_N

AD

C_I

N_P

REF

_P2V

048

REF

_P1V

7066

U_I

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_cha

nnel

Inpu

t_ch

anne

l.Sch

Doc

IN_N

A0

A1

IN_P

TER

M_I

ND

AD

C_I

N_N

AD

C_I

N_P

REF

_P2V

048

REF

_P1V

7066

U_I

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nnel

Inpu

t_ch

anne

l.Sch

Doc

IN_N

A0

A1

IN_P

TER

M_I

ND

AD

C_I

N_N

AD

C_I

N_P

REF

_P2V

048

REF

_P1V

7066

U_I

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nnel

Inpu

t_ch

anne

l.Sch

Doc

IN_N

A0

A1

IN_P

TER

M_I

ND

AD

C_I

N_N

AD

C_I

N_P

REF

_P2V

048

REF

_P1V

7066

U_I

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_cha

nnel

Inpu

t_ch

anne

l.Sch

Doc

IN_N

A0

A1

IN_P

TER

M_I

ND

AD

C_I

N_N

AD

C_I

N_P

REF

_P2V

048

REF

_P1V

7066

U_I

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_cha

nnel

Inpu

t_ch

anne

l.Sch

Doc

IN_N

A0

A1

IN_P

TER

M_I

ND

AD

C_I

N_N

AD

C_I

N_P

REF

_P2V

048

REF

_P1V

7066

U_I

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_cha

nnel

Inpu

t_ch

anne

l.Sch

Doc

AD

C_I

N_P

1

AD

C_I

N_P

2

AD

C_I

N_P

3

AD

C_I

N_P

4

AD

C_I

N_P

5

AD

C_I

N_P

6

AD

C_I

N_P

7

AD

C_I

N_N

1

AD

C_I

N_N

2

AD

C_I

N_N

3

AD

C_I

N_N

4

AD

C_I

N_N

5

AD

C_I

N_N

6

AD

C_I

N_N

7

AD

C_I

N_P

0A

DC

_IN

_N0

P3V

3_M

P11%R66 220

Gre

en

TOPLD

5B

GN

D

1%R67 220

Gre

en

BO

TLD

5AP3

V3

GN

D

P3V

3

1%

R5

10k

P3V

3

1%

R12

10k

P3V

3

1%

R13

10k

P3V

3

1%

R49

10k

P3V

3

1%

R68

10k

P3V

3

1%

R69

10k

P3V

3

1%

R70

10k

P3V

3

1%

R71

10k

P3V

3

R74U

ndefined

P12V

0

B1

R75U

ndefined

R76

Undefined

GN

D

GN

DB

2

Fron

t pan

el g

roun

ding

Test

conn

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r com

patib

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with

3U

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an a

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be u

sed

for i

nput

ada

pter

s

Dua

l EEM

mod

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AD

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con

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s to

BN

C 7

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Pow

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ith

term

inat

ion

PIB101 COB

1 PIB201

COB2

PIC5701 PIC5702 COC5

7 PIC9401 PIC9402

COC94

PICLIP101 COCLIP1

PICLIP201 COCLIP2

PICLIP301 COCLIP3

PICLIP401 COCLIP4

PICLIP501 COCLIP5

PICLIP601 COCLIP6

PICLIP701 COCLIP7

PICLIP801 COCLIP8

PICLIP901 COCLIP9

PICLIP1001 CO

CLIP

10

PICLIP1101 CO

CLIP

11

PICLIP1201 CO

CLIP

12

PICLIP1301 CO

CLIP

13

PICLIP1401 CO

CLIP

14

PICLIP1501 CO

CLIP

15

PICLIP1601 CO

CLIP

16

PICLIP1701 CO

CLIP

17

PICLIP1801 CO

CLIP

18

PICLIP1901 CO

CLIP

19

PICLIP2001 CO

CLIP

20

PICLIP2101 CO

CLIP

21

PICLIP2201 CO

CLIP

22

PICLIP2301 CO

CLIP

23

PICLIP2401 CO

CLIP

24

PICLIP2501 CO

CLIP

25

PICLIP2601 CO

CLIP

26

COFT

G17

COFT

G18

COFT

G19

COFT

G20

PIIC

1001

PI

IC10

02

PIIC

1003

PIIC

1004

PIIC

1005

PIIC1006

PIIC

1007

PIIC

1008

PIIC

1009

PIIC10010

PIIC10011

PIIC10012

PIIC10013

PIIC10014

PIIC10015

PIIC10016

COIC

10

PIIC

1101

PIIC

1102

PIIC

1103

PIIC

1104

PIIC

1105

PIIC

1106

PIIC

1107

PIIC

1108

PIIC

1109

PIIC11010

PIIC11011

PIIC11012

PIIC11013

PIIC11014

PIIC11015

PIIC11016

COIC11

PIJ101

PIJ102

PIJ103

PIJ104

PIJ105

PIJ106

PIJ107

PIJ108

PIJ109

PIJ1010

PIJ1011

PIJ1012

PIJ1013

PIJ1014

PIJ1015

PIJ1016

PIJ1017

PIJ1018

PIJ1019

PIJ1020

PIJ1021

PIJ1022

PIJ1023

PIJ1024

PIJ1025

PIJ1026

COJ1

PIJ301

PIJ304

COJ3

A

PIJ302

PIJ303

COJ3

B

PIJ401

PIJ404

COJ4

A

PIJ402

PIJ403

COJ4

B

PIJ501

PIJ504

COJ5

A

PIJ5

02

PIJ503

COJ5

B

PIJ601

PIJ6

04

COJ6

A

PIJ602

PIJ603

COJ6

B

PILD

101

PILD

102

COLD1A

PILD

103

PILD

104

COLD1B

PILD

201

PILD

202

COLD

2A

PILD

203

PILD

204

COLD

2B

PILD

301

PILD

302

COLD

3A

PILD

303

PILD

304

COLD

3B

PILD

401

PILD

402

COLD

4A

PILD

403

PILD

404

COLD

4B

PILD

501

PILD

502

COLD

5A

PILD

503

PILD

504

COLD

5B

PIR301

PIR302

COR3

PIR501

PIR502 COR

5

PIR601

PIR602

COR6

PIR120

1 PIR

1202 COR1

2

PIR130

1 PIR

1302 COR1

3

PIR490

1 PIR

4902 COR4

9

PIR580

1 PIR

5802

COR5

8

PIR590

1 PIR

5902

COR5

9

PIR600

1 PIR

6002

COR6

0

PIR610

1 PIR

6102

COR6

1

PIR620

1 PIR

6202

COR6

2

PIR630

1 PIR

6302

COR6

3

PIR640

1 PIR

6402

COR6

4

PIR650

1 PIR

6502

COR6

5

PIR660

1 PIR

6602

COR6

6

PIR670

1 PIR

6702

COR6

7

PIR680

1 PIR

6802 COR6

8

PIR690

1 PIR

6902 COR6

9

PIR700

1 PIR

7002 COR7

0 PIR710

1 PIR

7102 COR7

1

PIR740

1 PIR

7402

COR7

4

PIR750

1 PIR

7502 CO

R75 PI

R7601

PIR7602 CO

R76

PIT101 PIT102

PIT1

03

COT1

PIT201 PIT202

PIT203

COT2

PIT301 PIT302

PIT303

COT3

PIT401 PIT402

PIT403

COT4

PIT501 PIT502

PIT503

COT5

PIT601 PIT602

PIT603

COT6

PIT701 PIT702

PIT703

COT7

PIT801 PIT802

PIT803

COT8

PIJ1023

PIJ301

NLADC0IN0N0

PIJ1020

PIJ303

NLAD

C0IN

0N1

PIJ1017

PIJ401

NLADC0IN0N2

PIJ1014

PIJ403

NLADC0IN0N3

PIJ1011

PIJ501

NLADC0IN0N4

PIJ108

PIJ503

NLADC0IN0N5

PIJ105

PIJ601

NLADC0IN0N6

PIJ102

PIJ603

NLADC0IN0N7

PIJ1022

PIJ304

NLAD

C0IN

0P0

PIJ1019

PIJ302

NLAD

C0IN

0P1

PIJ1016

PIJ404

NLAD

C0IN

0P2

PIJ1013

PIJ402

NLAD

C0IN

0P3

PIJ1010

PIJ504

NLAD

C0IN

0P4

PIJ107

PIJ5

02

NLAD

C0IN

0P5

PIJ104

PIJ6

04

NLAD

C0IN

0P6

PIJ101

PIJ602

NLAD

C0IN

0P7

PIIC10015

NLCH

00A0

PIIC

1001

NLCH

00A1

PIIC

1002

NLCH

10A0

PIIC

1003

NLCH

10A1

PIIC

1004

NLCH

20A0

PIIC

1005

NLCH

20A1

PIIC1006

NLCH

30A0

PIIC

1007

NLCH

30A1

PIIC11015

NLCH

40A0

PIIC

1101

NLCH

40A1

PIIC

1102

NLCH

50A0

PIIC

1103

NLCH

50A1

PIIC

1104

NLCH

60A0

PIIC

1105

NLCH

60A1

PIIC

1106

NLCH

70A0

PIIC

1107

NLCH

70A1

PIC5701 PIC9401

PICLIP101 PICLIP201

PICLIP301 PICLIP401

PICLIP501

PICLIP601 PICLIP701

PICLIP801 PICLIP901

PICLIP1001

PICLIP1101 PICLIP1201


PICLIP1501



PICLIP2001




PIIC

1008

PIIC

1108

PIJ103

PIJ106

PIJ109

PIJ1012

PIJ1015

PIJ1018

PIJ1021

PIJ1024

PIR660

2

PIR670

2

PIR750

1

PIR7601

PIT102

PIT202

PIT302

PIT402

PIT502

PIT602

PIT702

PIT802

PIR602

PIB101 PIR

7502

PIB201

PIR7602

PIIC

1009

PIIC11014

PIIC10013

PIIC11013

PIJ1025

PIR301

PIR740

1

PIJ1026

PIR601

PILD

101 PIR

5801

PILD

103 PIR590

1

PILD

201 PIR600

1

PILD

203 PIR610

1

PILD

301 PIR620

1

PILD

303 PIR630

1

PILD

401 PIR640

1

PILD

403 PIR650

1

PILD

501 PIR670

1

PILD

503 PIR660

1

PIR580

2 PI

T103

PIR590

2 PIT203

PIR600

2 PIT303

PIR610

2 PIT403

PIR620

2 PIT503

PIR630

2 PIT603

PIR640

2 PIT703

PIR650

2 PIT803

PIC5702 PIC9402

PIIC10010

PIIC10016

PIIC11010

PIIC11016

PILD

102

PILD

104

PILD

202

PILD

204

PILD

302

PILD

304

PILD

402

PILD

404

PILD

502

PIR501

PIR120

1

PIR130

1

PIR490

1

PIR680

1

PIR690

1

PIR700

1

PIR710

1

PILD

504

PIR740

2

PIR302

PIIC10012

PIIC11012

NLPG

IA0C

S

PIIC

1109

NLPGIA0MISO

PIIC10014

NLPG

IA0M

OSI

PIIC10011

PIIC11011

NLPG

IA0S

CK

PIR502

PIT101

NLTERM0STAT070000

NLTERM0STAT0

PIR120

2 PIT201

NLTERM0STAT070000

NLTERM0STAT1

PIR130

2 PIT301

NLTERM0STAT070000

NLTERM0STAT2

PIR490

2 PIT401

NLTERM0STAT070000

NLTERM0STAT3

PIR680

2 PIT501

NLTERM0STAT070000

NLTERM0STAT4

PIR690

2 PIT601

NLTERM0STAT070000

NLTERM0STAT5

PIR700

2 PIT701

NLTERM0STAT070000

NLTERM0STAT6

PIR710

2 PIT801

NLTERM0STAT070000

NLTERM0STAT7

11

22

33

44

55

EE

DD

CC

BB

AA

2W

arsa

w U

nive

risty

of T

echn

olog

yN

owow

iejsk

a 15

/19

5

ADC

+ re

fere

nce

-28

.01.

2020

03:3

4:21

AD

C_8

CH

.Sch

Doc

Size

File

Rev

Shee

tof A3

Sam

pler

Proj

ect/E

quip

men

t

ART

IQ

G.K

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esig

ner

G.K

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Che

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v2.2

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od.

Doc

umen

t

Prin

t Dat

e

27.0

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18C

anno

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en fi

le

D:\D

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DES

IGN

S\M

TCA

_pr

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ts\SI

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P5V

0A

C5

100nF

GN

D

C2

2.2uF

GN

DG

ND

C1

1uF

GN

D

R1 0

REF

_VC

CR

15 0

C54

100nF

GN

D

Cop

yrig

ht W

UT

2017

This

doc

umen

tatio

n de

scrib

es O

pen

Har

dwar

e an

d is

lice

nsed

un

der t

he C

ERN

OH

L v.

1.1.

You

may

redi

strib

ute

and

mod

ify th

is

docu

men

tatio

n un

der t

he te

rms

of th

e CE

RN

OH

L v.

1.1.

(h

ttp://

ohw

r.org

/CER

NO

HL)

. Thi

s do

cum

enta

tion

is d

istri

bute

d W

ITH

OU

T A

NY

EX

PRES

S O

R IM

PLIE

D W

AR

RA

NTY

, IN

CLU

DIN

G O

F M

ERC

HA

NTA

BILI

TY, S

ATIS

FACT

ORY

Q

UA

LITY

AN

D F

ITN

ESS

FOR

A P

ART

ICU

LAR

PU

RPO

SE.

Plea

se s

ee th

e CE

RN

OH

L v.

1.1

for a

pplic

able

con

ditio

ns.

GN

D

AD

C_S

DO

A_P

AD

C_S

DO

A_N

AD

C_S

DO

B_N

AD

C_S

DO

B_P

AD

C_S

DO

C_P

AD

C_S

DO

C_N

AD

C_S

DO

D_N

AD

C_S

DO

D_P

AD

C_C

LKO

UT_

PA

DC

_CLK

OU

T_N

AD

C_S

CK

_PA

DC

_SC

K_N

AD

C_C

NV

C16

10uF

GN

D

C15

10uF

GN

D

C14

10uF

GN

D

C13

10uF

GN

D

C1210uF

C3

100nFGN

D

C4

100nFGN

D

R100

C8

100nF

C7

100nF

GN

DG

ND

P2V

5A

C610uF

GN

D

C910uF

GN

D

1%

R21k

D

S

GT9

BSS138LT1G

GN

D

SDR

_MO

DE

1%R9

100

REF

_P2V

048

2 31

V+ V-8 4

IC5A

OPA

2197

IDG

KR

567

V+ V-8 4

IC5B

OPA

2197

IDG

KR

N12

V0A

N12

V0A

P12V

0A

P12V

0A

27

0.1% 5k R

N4B

18 0.1%

10k

RN4A 45 0.1%

10k

RN4D

REF

_P4V

096

REF

_P4V

096

GN

D

C22

100nF

C20

100nF

GN

DG

ND

P12V

0AN

12V

0A

REF

_SH

DN

AD

C_S

DO

A_P

AD

C_S

DO

A_N

AD

C_S

DO

B_P

AD

C_S

DO

B_N

AD

C_S

DO

C_P

AD

C_S

DO

C_N

AD

C_S

DO

D_P

AD

C_S

DO

D_N

AD

C_C

LKO

UT_

PA

DC

_CLK

OU

T_N

AD

C_S

CK

_PA

DC

_SC

K_N

OVDD31

OGND 32

AIN

1-19

AIN

1+20

VDD21

~SDR/DDR23

OVDD37

REF

OU

T122

VDD44

~CMOS/LVDS25

SDO

1/SD

OA

+27

SDO

2/SD

OA

-28

SCK

+/SC

K41

REF

8

OGND 38

VDD52

REFBUFEN43

REF

OU

T29

GND 3

GND 7

CLK

OU

T+/C

LKO

UT

33

~CN

V24

REF

OU

T36

VDD15

AIN

2+17

AIN

2-16

AIN

3+14

AIN

3-13

AIN

4+11

AIN

4-10

AIN

5+5

AIN

5-4

AIN

6+2

AIN

6-1

AIN

7+51

AIN

7-50

AIN

8+48

AIN

8-47

SDO

3/SD

OB

+29

SDO

4/SD

OB

-30

SDO

5/SD

OC

+35

SDO

6/SD

OC

-36

SDO

7/SD

OD

+39

SDO

8/SD

OD

-40

REF

OU

T445

GND 12GND 18

GND 46

CLK

OU

T-/D

IS34

SCK

-/NC

42

GND 26

GND 49

GND 53

IC2

LTC

2320

HU

KG

-16#

PBF

IN_0

_P

IN_1

_P

IN_2

_P

IN_3

_P

IN_4

_P

IN_5

_P

IN_6

_P

IN_7

_P

IN_0

_N

IN_1

_N

IN_2

_N

IN_3

_N

IN_4

_N

IN_5

_N

IN_6

_N

IN_7

_N

IN_0

_NIN

_0_P

IN_1

_PIN

_1_N

IN_2

_PIN

_2_N

IN_3

_PIN

_3_N

IN_4

_PIN

_4_N

IN_5

_PIN

_5_N

IN_6

_PIN

_6_N

IN_7

_PIN

_7_N

REF

_P1V

7066

REF

_P2V

048

GN

D18 0.1%

10k

RN3A45 0.1%

10k

RN3D36 0.1%

5k

RN3C

C75

47nF

GN

D

C76

47nF

GN

D

2 70.1%

5k

RN3B

36

0.1%

5k

RN

4C

P2V

5A

1%R

1182k

P2V

5A

1%R72 24k

VIN

2

SHD

N1

VO

UTS

6V

OU

TF7

GN

D3

GN

D8

GN

D4

GN

D5

IC1

LTC

6655

BH

MS8

-4.0

96#P

BF

SWA

PPED

AD

C C

HA

NN

ELS!

!

PIC101 PIC102 CO

C1

PIC201 PIC202 COC

2

PIC301 PIC302 COC

3 PIC401 PIC402

COC4

PIC501 PIC502 COC

5 PIC601 PIC602

COC6

PIC701 PIC702 COC

7 PIC801 PIC802

COC8

PIC901 PIC902

COC9

PIC1201 PIC1202 CO

C12

PIC1

301

PIC1

302

COC1

3

PIC1

401

PIC1

402

COC1

4

PIC1

501

PIC1

502

COC15

PIC1

601

PIC1

602

COC1

6


0 PIC2201 PIC2202

COC22


4


5 PIC7601 PIC7602 COC7

6

PIIC101

PIIC102

PIIC103

PIIC104

PIIC105

PIIC106

PIIC107

PIIC108

COIC

1

PIIC

201

PIIC

202

PIIC203

PIIC

204

PIIC

205

PIIC

206

PIIC207

PIIC

208

PIIC

209

PIIC

2010

PIIC

2011

PIIC2012

PIIC

2013

PIIC

2014

PIIC2015

PIIC

2016

PIIC

2017

PIIC2018

PIIC

2019

PIIC

2020

PIIC2021

PIIC

2022

PIIC2023

PIIC

2024

PIIC2025

PIIC2026

PIIC

2027

PIIC

2028

PIIC

2029

PIIC

2030

PIIC2031

PIIC2032

PIIC

2033

PIIC

2034

PIIC

2035

PIIC

2036

PIIC2037

PIIC2038

PIIC

2039

PIIC

2040

PIIC

2041

PIIC

2042

PIIC2043 PIIC2044

PIIC

2045

PIIC2046

PIIC

2047

PIIC

2048

PIIC2049

PIIC

2050

PIIC

2051

PIIC2052

PIIC2053

COIC

2

PIIC501

PIIC502

PIIC503

PIIC504 PIIC508 COIC5A

PIIC504 PIIC505

PIIC506

PIIC507

PIIC508

COIC5B

PIR101

PIR102

COR1

PIR201

PIR202 COR

2

PIR901

PIR902

COR9

PIR1001

PIR1002

COR10

PIR1

101

PIR1

102 COR

11

PIR150

1 PIR

1502

COR1

5

PIR720

1 PIR

7202

COR7

2

PIRN301 PIRN308

CORN3A

PIRN302 PIRN307

CORN3B

PIRN303 PIRN306

CORN3C

PIRN304 PIRN305

CORN3D

PIRN401 PIRN408 CORN4A

PIRN40

2 PIR

N407

CORN4B

PIRN40

3 PI

RN40

6

CORN4C PIRN404 PIRN405 CORN4D

PIT901 PIT902

PIT903

COT9

PIIC

2034

NL

ADC0

CLKO

UT0N

POADC0CLKOUT0N

PIIC

2033

NL

ADC0

CLKO

UT0P

POADC0CLKOUT0P

PIIC

2042

PIR901

NLADC0SCK0N

POADC0SCK0N

PIIC

2041

PIR902

NLADC0SCK0P

POADC0SCK0P

PIIC

2028

NL

ADC0

SDOA

0N

POADC0SDOA0N

PIIC

2027

NLADC0SDOA0P

POADC0SDOA0P

PIIC

2030

NLADC0SDOB0N

POADC0SDOB0N

PIIC

2029

NLADC0SDOB0P

POADC0SDOB0P

PIIC

2036

NLADC0SDOC0N

POADC0SDOC0N

PIIC

2035

NLADC0SDOC0P

POADC0SDOC0P

PIIC

2040

NL

ADC0

SDOD

0N

POADC0SDOD0N

PIIC

2039

NLADC0SDOD0P

POADC0SDOD0P

PIC101 PIC201

PIC301 PIC401

PIC501 PIC601

PIC701 PIC801

PIC901

PIC1201

PIC1

301

PIC1

401

PIC1

501

PIC1

601

PIC2001 PIC2201

PIC5401

PIC7501 PIC7601

PIIC103

PIIC104

PIIC105

PIIC108

PIIC203 PIIC207

PIIC2012 PIIC2018

PIIC2026 PIIC2032

PIIC2038 PIIC2046

PIIC2049 PIIC2053

PIRN307

PIRN404

PIT902

PIIC

2047

NL

IN00

0N

POIN000N

PIIC

2048

NL

IN00

0P

POIN000P

PIIC

2050

NL

IN01

0N

POIN010N

PIIC

2051

NL

IN01

0P

POIN010P

PIIC

201

NLIN

020N

POIN020N

PIIC

202

NLIN

020P

POIN020P

PIIC

204

NLIN

030N

POIN030N

PIIC

205

NLIN

030P

POIN030P

PIIC

2010

NL

IN04

0N

POIN040N

PIIC

2011

NL

IN04

0P

POIN040P

PIIC

2013

NL

IN05

0N

POIN050N

PIIC

2014

NL

IN05

0P

POIN050P

PIIC

2016

NL

IN06

0N

POIN060N

PIIC

2017

NL

IN06

0P

POIN060P

PIIC

2019

NL

IN07

0N

POIN070N

PIIC

2020

NL

IN07

0P

POIN070P

PIC2202

PIIC504

PIC102 PIIC102

PIR150

2

PIC1202 PI

IC20

8 PIR102

PIC1

302 PIIC

2022

PIC1

402 PIIC

209

PIC1

502 PIIC

206

PIC1

602 PIIC

2045

PIC7502 PIIC503

PIRN401 PIRN405

PIC7602 PIIC505

PIRN303 PIRN305

PIIC101

POREF0S\H\D\N\

PIIC2023

PIR202

PIT903

PIIC

2024

POADC0CNV

PIIC2025 PIR1

102

PIIC2043 PIR1001

PIIC502

PIRN

406

PIIC506

PIR720

1

PIRN40

2

PIRN301 PIRN302 PIRN304 PIRN308

PIT901

POSDR0MODE

PIC702 PIC802

PIC902

PIIC2031 PIIC2037

PIR201

PIR1

101

PIC302 PIC402

PIC502 PIC602

PIC5402

PIIC2015 PIIC2021

PIIC2044 PIIC2052

PIR1002

PIC2002

PIIC508

PIIC507

PIR720

2

PIRN40

7

PIIC501

PIRN306

PIRN40

3

PIC202 PIIC106

PIIC107

PIR101

PIRN408

PIR150

1

POADC0CLKOUT0N

POADC0CLKOUT0P

POADC0CNV

POADC0SCK0N

POADC0SCK0P

POADC0SDOA0N

POADC0SDOA0P

POADC0SDOB0N

POADC0SDOB0P

POADC0SDOC0N

POADC0SDOC0P

POADC0SDOD0N

POADC0SDOD0P

POIN000N

POIN000P

POIN010N

POIN010P

POIN020N

POIN020P

POIN030N

POIN030P

POIN040N

POIN040P

POIN050N

POIN050P

POIN060N

POIN060P

POIN070N

POIN070P

POREF0S\H\D\N\

POSDR0MODE

11

22

33

44

55

EE

DD

CC

BB

AA

3W

arsa

w U

nive

risty

of T

echn

olog

yN

owow

iejsk

a 15

/19

5

Inpu

t chn

anne

l

-28

.01.

2020

03:3

4:22

Inpu

t_ch

anne

l.Sch

Doc

Size

File

Rev

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tof A3

Sam

pler

Proj

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IN_N

1

2

3

456

7

8

9

10

A1WR

-Vs +Vs

REFA0

DGND

IC6

AD

8253

AR

MZ

32D1B

BAV199

13D1A

BAV199

32D3B

BAV199

13D3A

BAV199

GN

DG

ND

GN

DG

ND

P12V

0A

N12

V0A

GN

D

A0

A1

C35

100nF

C41

100nF

GN

DG

ND

GN

DG

ND

RFI F

ilter

IN_P

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R4

49R9

1 24 3

SW1

GN

DTE

RM

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DP1

2V0A

N12

V0A

P12V

0A

N12

V0A

P12V

0AN

12V

0A

+C11

10uF

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10uF

13

24

L2

2x6.

5mH

R33

0 R41

0

1% R35100k

1% R43100k

C85

18pF

C88

18pF

1%

R42

1k8

1%

R34

1k8

R86

Und

efin

ed

R37

Und

efin

ed

Cop

yrig

ht W

UT

2017

This

doc

umen

tatio

n de

scrib

es O

pen

Har

dwar

e an

d is

lice

nsed

un

der t

he C

ERN

OH

L v.

1.1.

You

may

redi

strib

ute

and

mod

ify th

is

docu

men

tatio

n un

der t

he te

rms

of th

e CE

RN

OH

L v.

1.1.

(h

ttp://

ohw

r.org

/CER

NO

HL)

. Thi

s do

cum

enta

tion

is d

istri

bute

d W

ITH

OU

T A

NY

EX

PRES

S O

R IM

PLIE

D W

AR

RA

NTY

, IN

CLU

DIN

G O

F M

ERC

HA

NTA

BILI

TY, S

ATIS

FACT

ORY

Q

UA

LITY

AN

D F

ITN

ESS

FOR

A P

ART

ICU

LAR

PU

RPO

SE.

Plea

se s

ee th

e CE

RN

OH

L v.

1.1

for a

pplic

able

con

ditio

ns.

2 31

V+ V-8 4

IC12

A

OPA

2197

IDG

KR

567

V+ V-8 4

IC12

B

OPA

2197

IDG

KR

C17

2.2nF

GN

D

N12

V0A

N12

V0A

P12V

0A

P12V

0A

18

0.1%

10kR

N1A

36

0.1%

5k

RN

1C

27 0.1%

5k

RN2B

36

0.1% 5kR

N2C

1%R50 2k4

45

0.1% 10

kRN

1D

27

0.1% 5k

RN

1B

GN

D

1%R14 51 1%R16 51

C23

2.2nF

C25

2.2nF

AD

C_I

N_P

AD

C_I

N_N

C70

100nF

C71

100nF

GN

DG

ND

P12V

0AN

12V

0A

C72

82pF

18

0.1%

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2A4

5

0.1%

10k

RN

2D

REF

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0V1.

7066

V2.

048V

C73

47nF

GN

D

C74

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GN

D

REF

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1%R73 24k

GA

IN=5

Fc=1

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Hz

BW

diff

=1M

Hz

BW

com

m =

465

kH

zLe

akag

e in

duct

ance

: 28

0nH

+-5V

(0.5

W) m

axim

um w

ith

term

inat

ion


0 PIC1101 PIC1102

COC11


7 PIC2301 PIC2302

COC23 PIC2501 PIC2502

COC25


PIC4101 PIC4102

COC41


0 PIC7101 PIC7102

COC71

PIC7201 PIC7202

COC72



4



8

PID101

PID103

COD1A PID102

PID103

COD1B PID301

PID303

COD3A PID302

PID303

COD3B

PIIC601

PIIC602 PIIC603

PIIC604 PIIC605 PIIC606

PIIC607

PIIC608

PIIC609 PI

IC60

10

COIC

6

PIIC1201

PIIC

1202

PIIC1203

PIIC1204 PIIC1208 CO

IC12

A

PIIC1204 PI

IC12

05

PIIC

1206

PIIC

1207

PIIC1208

COIC

12B

PIL2

01

PIL2

02

PIL2

03

PIL2

04

COL2

PIR401

PIR402 COR

4

PIR1401

PIR1

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COR1

4

PIR160

1 PI

R160

2 CO

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PIR330

1 PIR

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3 PIR

3401

PIR340

2

COR3

4

PIR3501

PIR3502

COR35

PIR370

1 PIR

3702

COR3

7 PIR

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PIR410

2

COR4

1 PIR

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PIR420

2

COR4

2

PIR4301

PIR4302

COR43

PIR500

1 PIR

5002

COR5

0

PIR7301

PIR7302

COR7

3

PIR860

1 PIR

8602

COR8

6

PIRN

101

PIRN

108

CORN

1A

PIRN10

2 PIR

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CORN

1B

PIRN10

3 PIR

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CORN

1C

PIRN10

4 PIR

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CORN

1D

PIRN20

1 PIR

N208 CORN2A

PIRN202

PIRN207

CORN2B

PIRN20

3 PIR

N206

CORN2C

PIRN20

4 PIR

N205 CORN2D

PISW101

PISW102

PISW103

PISW104

COSW

1

PIC1002 PIC1101

PIC2301 PIC2502

PIC3501 PIC4101

PIC7001 PIC7101

PIC7301 PIC7401

PIC8501 PIC8801

PIIC602 PIIC609

PIR3501

PIR4301

PISW103

PIC1102 PIC4102

PIC7102

PID101

PID301

PIIC603

PIIC606 PIIC1204

PIC1701

PIC2501

PIR1

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PIC1702

PIC2302

PIR1

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PIC7201

PIC8802 PID303

PIIC601

PIR420

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PIC7202

PIC8502 PID103

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PIRN20

4

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PIR500

2

PIIC604

POA0

PIIC605

POA1

PIIC607

PIRN

101

PIIC1201

PIR1401

PIRN10

7

PIRN207

PIIC

1202

PIRN10

2

PIRN10

3

PIIC

1206

PIRN202

PIRN20

3

PIIC

1207

PIR

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PIRN20

6

PIL2

01

PIR402

PIR860

1 POIN0P

PIL2

02 PIR370

1

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03 PIR

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PIR410

1

PIL2

04

PIR330

1 PIR

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PIR330

2 PIR

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PIR3502

PIR410

2 PIR

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PIR4302

PIR500

1 POREF0P2V048 PI

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PIRN20

5

PIRN20

8

POREF0P1V7066

PIRN10

4 PI

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8 PIR

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6

PISW102

POTERM0IND

PIC1001 PIC3502

PIC7002

PID102

PID302

PIIC608

PIIC1208

POA0

POA1

POADC0IN0N

POADC0IN0P

POIN0N

POIN0P

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11

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2020

03:3

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GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

I2C

1_SD

AI2

C1_

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GN

D1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

J2

P12V

0

EEM

1_1_

PEE

M1_

1_N

EEM

1_3_

PEE

M1_

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EEM

1_4_

NEE

M1_

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I2C

1_SD

AI2

C1_

SCL

1%R17 100

C38

100nF

C37

100nF

C33

100nF

C31

100nF

C24

100nF

C21

100nF

GN

D

P3V

3

GN

D

SCL

1

VSS

2

SDA

3

VC

C4

NC

5IC

9

24A

A02

E48T

-I/O

T

P3V

3_M

P1

P3V

3_M

P1

C43

100nF

GN

D

EEM

con

nect

or: I

O a

re L

VD

S, I2

C is

3V

3 LV

CM

OS,

P3V

3_M

P up

to

20m

A, P

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up

to 1

A

Cop

yrig

ht W

UT

2017

This

doc

umen

tatio

n de

scrib

es O

pen

Har

dwar

e an

d is

lice

nsed

un

der t

he C

ERN

OH

L v.

1.1.

You

may

redi

strib

ute

and

mod

ify th

is

docu

men

tatio

n un

der t

he te

rms

of th

e CE

RN

OH

L v.

1.1.

(h

ttp://

ohw

r.org

/CER

NO

HL)

. Thi

s do

cum

enta

tion

is d

istri

bute

d W

ITH

OU

T A

NY

EX

PRES

S O

R IM

PLIE

D W

AR

RA

NTY

, IN

CLU

DIN

G O

F M

ERC

HA

NTA

BILI

TY, S

ATIS

FACT

ORY

Q

UA

LITY

AN

D F

ITN

ESS

FOR

A P

ART

ICU

LAR

PU

RPO

SE.

Plea

se s

ee th

e CE

RN

OH

L v.

1.1

for a

pplic

able

con

ditio

ns.

AD

C_S

DO

B_P

AD

C_S

DO

B_N

AD

C_S

DO

C_P

AD

C_S

DO

C_N

AD

C_S

DO

D_P

AD

C_S

DO

D_N

AD

C_C

LKO

UT_

PA

DC

_CLK

OU

T_N

AD

C_S

DO

A_N

AD

C_S

DO

A_P

EEM

1_0_

NEE

M1_

0_P

EEM

1_1_

PEE

M1_

1_N

EEM

1_2_

NEE

M1_

2_P

EEM

1_3_

PEE

M1_

3_N

EEM

1_4_

NEE

M1_

4_P

EEM

1_5_

PEE

M1_

5_N

EEM

1_6_

NEE

M1_

6_P

EEM

1_7_

PEE

M1_

7_N

GN

DP3

V3

GN

D

1%R45 100

GN

DP3

V3

GN

D

1%R44 100

GN

DP3

V3

EEM

1_0_

PEE

M1_

0_N

GN

D

1%R46 100

GN

DP3

V3

GN

D

1%R47 100

GN

DP3

V3

GN

D

TP3

TP4

TP6

P3V

3_M

P1

TP5

EEM

1_2_

NEE

M1_

2_P

EEM

1

1

GN

D2

EN3

GN

D456

VC

C78

IC25

FIN

1101

K8X

1

GN

D2

EN3

GN

D456

VC

C78

IC27

FIN

1101

K8X

1

GN

D2

EN3

GN

D456

VC

C78

IC28

FIN

1101

K8X

1

GN

D2

EN3

GN

D456

VC

C78

IC29

FIN

1101

K8X

1

GN

D2

EN3

GN

D456

VC

C78

IC30

FIN

1101

K8X


1 PIC2401 PIC2402

COC24


1 PIC3301 PIC3302

COC33


7 PIC3801 PIC3802

COC38


3 PIIC901

PIIC902

PIIC903

PIIC904

PIIC905

COIC

9

PIIC

2501

PIIC2502

PIIC

2503

PIIC2504

PIIC2505

PIIC2506

PIIC

2507

PIIC

2508

COIC

25

PIIC

2701

PIIC2702

PIIC

2703

PIIC2704

PIIC2705

PIIC2706

PIIC

2707

PIIC

2708

COIC

27

PIIC

2801

PIIC2802

PIIC

2803

PIIC2804

PIIC2805

PIIC2806

PIIC

2807

PIIC

2808

COIC

28

PIIC

2901

PIIC2902

PIIC

2903

PIIC2904

PIIC

2905

PI

IC29

06

PIIC2907

PIIC

2908

COIC

29

PIIC

3001

PIIC3002

PIIC

3003

PIIC3004

PIIC3005

PIIC3006

PIIC

3007

PIIC

3008

COIC

30

PIJ201

PIJ202

PIJ203

PIJ204

PIJ205

PIJ206

PIJ207

PIJ208

PIJ209

PIJ2010

PIJ2011

PIJ2012

PIJ2013

PIJ2014

PIJ2015

PIJ2016

PIJ2017

PIJ2018

PIJ2019

PIJ2020

PIJ2021

PIJ2022

PIJ2023

PIJ2024

PIJ2025

PIJ2026

PIJ2027

PIJ2028

PIJ2029

PIJ2030

COJ2

PIR170

1 PIR

1702

COR1

7

PIR440

1 PIR

4402

COR4

4

PIR450

1 PIR

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COR4

5

PIR460

1 PIR

4602

COR4

6

PIR470

1 PIR

4702

COR4

7

PITP301

COTP

3 PITP40

1 CO

TP4

PITP501 COT

P5

PITP601

COTP

6

PIIC2505

PIJ203

NLEE

M100

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PIIC2506

PIJ202

NLEE

M100

0P

PIIC2705

PIJ206

NLEE

M101

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PIIC2706

PIJ205

NLEE

M101

0P

PIIC2805

PIJ209

NLEE

M102

0N

PIIC2806

PIJ208

NLEE

M102

0P

PIIC

2905

PIJ2012

NLEE

M103

0N

PIIC

2906

PIJ2011

NLEE

M103

0P

PIIC3005

PIJ2015

NLEE

M104

0N

PIIC3006

PIJ2014

NLEE

M104

0P

PIJ2018

NLEE

M105

0N

PIJ2017

NLEE

M105

0P

PIJ2021

NLEE

M106

0N

PIJ2020

NLEE

M106

0P

PIJ2024

NLEE

M107

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PIJ2023

NLEE

M107

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PIC2101 PIC2401

PIC3101 PIC3301

PIC3701 PIC3801

PIC4301

PIIC902

PIIC2502

PIIC2504

PIIC2702

PIIC2704

PIIC2802

PIIC2804

PIIC2902

PIIC2904

PIIC3002

PIIC3004

PIJ201

PIJ204

PIJ207

PIJ2010

PIJ2013

PIJ2016

PIJ2019

PIJ2022

PIJ2025

PITP601

PIIC901

PIJ2027

PITP401

NLI2

C10S

CL

PIIC903

PIJ2026

PITP301

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PIIC905

PIIC

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PIIC

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PIR

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PIIC

2701

PIR

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PIIC

2708

PIR

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PIIC

2801

PIR

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PIIC

2808

PIR

4502

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PIIC

2901

PIR

4601

POADC0SDOC0P

PIIC

2908

PIR

4602

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PIIC

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PIR

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PIIC

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PIR

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PIC2102 PIC2402

PIC3102 PIC3302

PIC3702 PIC3802

PIIC

2503

PIIC

2507

PIIC

2703

PIIC

2707

PIIC

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PIIC

2807

PIIC

2903

PIIC2907

PIIC

3003

PIIC

3007

PIC4302 PIIC904

PIJ2030

PITP501

PIJ2028

PIJ2029

POADC0CLKOUT0N

POADC0CLKOUT0P

POADC0SDOA0N

POADC0SDOA0P

POADC0SDOB0N

POADC0SDOB0P

POADC0SDOC0N

POADC0SDOC0P

POADC0SDOD0N

POADC0SDOD0P

11

22

33

44

55

EE

DD

CC

BB

AA

4W

arsa

w U

nive

risty

of T

echn

olog

yN

owow

iejsk

a 15

/19

5

LVD

S In

terf

ace

-28

.01.

2020

03:3

4:22

LVD

S_IF

CA

.Sch

Doc

Size

File

Rev

Shee

tof A3

Sam

pler

Proj

ect/E

quip

men

t

ART

IQ

G.K

.D

esig

ner

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X/X

XX

X-

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c v2

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-La

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od.

Doc

umen

t

Prin

t Dat

e

27.0

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anno

t op

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IGN

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GN

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GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

I2C

0_SD

AI2

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D1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

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0

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C160

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C158

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C157

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GN

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P3V

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P0

P3V

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P0

C162100nF

GN

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AI2

C0_

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C153

100nF

GN

D

A0

1

A1

2

A2

3

P04

P15

P26

P37

GN

D8

P49

P510

P611

P712

INT

13

SCL

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VC

C16

IC38

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P3V

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ND

GN

DP3

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P3V

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P0

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con

nect

or: I

O a

re L

VD

S, I2

C is

3V

3 LV

CM

OS,

P3V

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P up

to

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A, P

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up

to 1

ATE

RM

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T0TE

RM

_STA

T1TE

RM

_STA

T2TE

RM

_STA

T3TE

RM

_STA

T4TE

RM

_STA

T5TE

RM

_STA

T6TE

RM

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T7

TER

M_S

TAT[

7..0

]TE

RM

_STA

T[7.

.0]

Cop

yrig

ht W

UT

2017

This

doc

umen

tatio

n de

scrib

es O

pen

Har

dwar

e an

d is

lice

nsed

un

der t

he C

ERN

OH

L v.

1.1.

You

may

redi

strib

ute

and

mod

ify th

is

docu

men

tatio

n un

der t

he te

rms

of th

e CE

RN

OH

L v.

1.1.

(h

ttp://

ohw

r.org

/CER

NO

HL)

. Thi

s do

cum

enta

tion

is d

istri

bute

d W

ITH

OU

T A

NY

EX

PRES

S O

R IM

PLIE

D W

AR

RA

NTY

, IN

CLU

DIN

G O

F M

ERC

HA

NTA

BILI

TY, S

ATIS

FACT

ORY

Q

UA

LITY

AN

D F

ITN

ESS

FOR

A P

ART

ICU

LAR

PU

RPO

SE.

Plea

se s

ee th

e CE

RN

OH

L v.

1.1

for a

pplic

able

con

ditio

ns.

EEM

0_0_

NEE

M0_

0_P

EEM

0_1_

PEE

M0_

1_N

EEM

0_2_

NEE

M0_

2_P

EEM

0_3_

PEE

M0_

3_N

EEM

0_4_

NEE

M0_

4_P

EEM

0_5_

PEE

M0_

5_N

EEM

0_6_

NEE

M0_

6_P

EEM

0_7_

PEE

M0_

7_N

PGIA

-CS

PGIA

-SC

K

PGIA

-MO

SI

PGIA

-MIS

O

AD

C_S

DO

A_N

AD

C_S

DO

A_P

AD

C_S

CK

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DC

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K_P

AD

C_C

NV

VC

C15

34

GN

D2

IC19

SN65

LVD

S1D

BV

T

1%R30 100

GN

DP3

V3

GN

D

EEM

0_0_

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0_N

GN

DP3

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GN

D

GN

D

1%R31 100

EEM

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GN

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IC17

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GN

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36 100

VC

C1

53 4

GN

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RG

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P3V

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0

EEM

0_4_

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1306

PIIC

1307

PIIC

1308

COIC

13

PIIC

1401

PIIC

1402

PIIC

1403

PIIC

1404

PIIC

1405

COIC

14

PIIC

1501

PIIC

1502

PIIC

1503

PIIC1504 PIIC1508 CO

IC15

A

PIIC1504 PI

IC15

05

PIIC

1506

PIIC

1507

PIIC1508

COIC

15B

PIIC1601

PIIC

1602

PIIC

1603

PIIC

1604

PIIC

1605

PIIC

1606

PIIC

1607

PIIC1608

COIC

16

PIIC

2601

PIIC

2602

PIIC

2603

PIIC

2604

PIIC

2605

PI

IC26

06

PIIC

2607

PI

IC26

08

PIIC

2609

PIIC26010

PIIC26011

COIC

26

PIL1

01

PIL1

02

COL1

PIL3

01

PIL3

02

COL3

PIL4

01

PIL402

COL4

PIL5

01

PIL5

02

COL5

PIL6

01

PIL6

02

COL6

PIL1

001

PIL100

2

COL10

PIL110

1 PI

L110

2

COL1

1

PIL1

201

PIL120

2

COL1

2 PI

L130

1 PIL

1302

COL13

PIR701

PIR702

COR7

PIR801

PIR802

COR8

PIR1801 PIR1802

COR18

PIR1901

PIR1902

COR19

PIR2001

PIR2002

COR20 PIR2101 PIR2102

COR21

PIR2201

PIR2202 COR2

2

PIR2301

PIR2302 CO

R23

PIR2401 PIR2402

COR24

PIR2501

PIR2502

COR25

PIR2601 PIR2602

COR26 PIR2701

PIR2702

COR27

PIR2801

PIR2802

COR28

PIR2901

PIR2902

COR29

PIR3201

PIR3202

COR32 PIR3801

PIR3802

COR38

PIR4801

PIR4802

COR48

PIR5101

PIR5102 CO

R51

PIR520

1 PIR

5202 COR5

2

PIR5301 PIR5302 COR5

3 PIR5401 PIR5402

COR54

PIR560

1 PIR

5602 COR5

6

PIR5701

PIR5702 CO

R57

PIR14201

PIR14202

COR142 PIR14301

PIR14302

COR143

PITP701

COTP

7

PITP801

COTP

8

PITP901

COTP

9

PITP1001

COTP10

PITP1101

COTP11

PITP1201

COTP12

PITP1301

COTP13

PIC1801 PIC1901

PIC2601 PIC2701

PIC2802 PIC2901

PIC3001

PIC3201 PIC3401

PIC3601 PIC3901

PIC4001 PIC4201

PIC4401

PIC4501

PIC4601

PIC4801 PIC4902

PIC5002

PIC5102

PIC5201

PIC5301

PIC5501 PIC5602

PIC5801 PIC5901

PIC6002 PIC6101

PIC6201

PIC6301 PIC6401

PIC6601

PIC6801 PI

C690

1

PIC7702

PIC11201

PIC11502

PIC11701 PIC11802

PIC12001 PIC12101

PIC12201 PIC12301

PID802

PID901

PIIC303

PIIC305

PIIC402

PIIC702

PIIC801

PIIC806

PIIC

8011

PIIC

1303

PIIC

1306

PIIC

1307

PIIC

1401

PIIC1504

PIIC

1603

PIIC

1606

PIIC

1607

PIIC

2601

PIIC

2606

PIIC26011

PIR801

PIR2101

PIR2701

PIR2801

PIR2901

PIR3801

PIR4801

PIR5401

PIR14301

PIC4602

PIC5202 PID902

PIIC

1405

PIR3202

PITP901

PIC1902 PIC4402

PIIC

1402

PIL

1302

PIC4002

PIIC304

PIL1

201

PIR1901

PIC1802 PIC4202

PIL120

2 PI

L130

1

PIC2702 PIC2801

PIL100

2 PIL

1101

PIC3202 PIC3402

PIC3602 PIC3902

PIC4901

PIC6302 PIC6402

PIC12202 PIC12302

PIIC301

PIIC802

PIIC803

PIIC

2602

PIL6

02

PIC4

701

PIIC703

PIC6501 PI

IC13

04

PIC6602 PID502 PI

IC15

06

PIR520

1

PIC6802 PI

D202

PI

IC15

03

PIR2202

PIR4802

PIC6

902

PID402

PIIC807

PIIC

2603

PIR560

1

PIC11401

PIIC

1604

PIC1

1601

PIIC403

PID6

01

PIIC

2607

PIR5701

POREF0S\H\D\N\

PID6

02

PIIC

1305

PIIC

1403

PIIC

1501

PIR1801

PIR520

2

PIIC302

PIR802

PIIC306

PIR701

PIR1902

PIIC404

PIR2601 PIR2702

PIIC704

PIR5301 PIR5402

PIIC804

PIIC805

PIR2401

PIR2802

PIIC809

PIL3

01

PIIC

1302

PIR14201

PIR14302

PIIC

1404

PIR3201

PIR3802

PIIC

1502

PIR2301

PIIC

1507

PIR5102 POSR0O\E\

PIIC

1602

PIR2501

PIR2902

PIIC

2604

PIIC

2605

PIR2001

PIR2102

PIIC

2609

PI

L501

PIC4

702

PIC5502 PIC5601

PIIC705

PIR5302

PITP1001

PIC12002 PIC12102

PID501

PIIC

1505

PIIC

2608

PIIC26010

PIL1

01

PIL5

02 PIR2002

PIR5101

PIC5001 PIC5302

PID2

01

PIIC701

PIL1

02

PIR2302

PITP1101

PIC6202 PIC11402

PIC11501 PIIC1601

PIR2502

PITP1301

PIC5802 PIC5902

PIIC808

PIIC8010

PIL3

02

PIL4

01

PIR2402

PIR5702

PIC6001 PIC6102

PID4

01

PIIC

1605

PIIC1608

PIL402

PIR1802

PIR560

2

PITP1201

PIC4802

PIIC1508

PIL6

01

PIC3002 PIC5101

PIC6502 PID801

PIIC

1301

PIR14202

PITP701

PIC2902

PIC7701

PIC11202

PIC11702 PIIC401

PIIC

1308

PIL1

102

PIC2602

PIIC307

PIL1

001

PIR702

PIR2201

PIC4502

PIC1

1602

PIC11801 PIIC405

PIR2602

PITP801

POREF0S\H\D\N\

POSR0O\E\

Appendix 1. Details on the used boards

Appendix 1.2. Details on Zotino

Following the Zotino project page [50], it ‘is a 32-channel, 16-bit DAC EEM with an

update rate of 1MSPS (divided between the channels). It was designed for low noise and

good stability’.

The Zotino’s key features are:

• ‘Current hardware revision: Rev 1.1

• Width: 4HP

• Channel count: 32

• Resolution: 16-bit

• Update rate: 1MSPS, which may be divided arbitrarily between the channels

• Analogue bandwidth: 3rd-order Butterworth response with 75kHz cut-off; ?V/s

slew-rate

• Output voltage: ±10V

• Output impedance: 470Ohm in parallel with 2.2nF

• DAC: AD5372BCPZ

• EEM connectors: power and digital communication supplied by a single EEM con-

nector.

• Power consumption: 3W without load, 8.7W with max load on all channels’.

71

11

22

33

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

J31 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

J4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

J51 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

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C_O

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UT_

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1

CLI

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1

CLI

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GN

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1

CLI

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GN

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1

CLI

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1

CLI

P32

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1

CLI

P33

GN

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1

CLI

P34

GN

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1

CLI

P36

GN

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1

CLI

P37

GN

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1

CLI

P38

GN

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1

CLI

P39

GN

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1

CLI

P40

GN

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1

CLI

P41

GN

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1

CLI

P42

GN

D

1

CLI

P43

GN

D

1

CLI

P44

GN

D

1

CLI

P45

GN

D

1

CLI

P46

GN

D

1

CLI

P47

GN

D

1

CLI

P35

GN

D

1

CLI

P48

GN

D

1

CLI

P49

GN

D

1

CLI

P50

GN

D

1

CLI

P51

GN

D

1

CLI

P52

GN

D

1

CLI

P27

GN

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C96

1uF

GN

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P3V

3

1% R116220

1% R117220

1% R118220

C95

82pF

GN

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C68

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7182pF

GN

DG

ND

shie

ld c

lips

Pelti

er c

onta

cts

Temperature regulator

TEC

+

TEC

-

RT1

10k

GN

D

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

J2

P3V

3_M

P

1%R8220 1%R9220 1%R

10220 1%R

12220

TEC positioning components

N12

V0A

N12

V0A

TEC

1

CP2

0147

H

TEC

hea

t sin

k

B2B3B4

TEC

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ount

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LDA

Cn

CLR

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RES

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2V0

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Max

0.3

A@

12V

R15

Undefined

GN

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TP18

R26

Undefined

R27

Undefined

B1

R280 R290

GN

D

GN

DB

7

Fron

t pan

el g

roun

ding

C15

Und

efin

edG

ND

C11

Und

efin

edG

ND

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7

DAC

-28

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2020

03:3

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pen

Har

dwar

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d is

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he C

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PIC101 PIC102

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PIC701 PIC702 COC

7 PIC801 PIC802

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PIC901 PIC902 COC

9 PIC1201 PIC1202

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PIC3101 PIC3102 CO

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PIC3301 PIC3302 CO

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3

PIIC302

PIIC303

PIIC304

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PIIC306

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PIIC502

PIIC503

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

5020

PIIC

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PIIC

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PIIC

5023

PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC5036

PIIC

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PIIC5038

PIIC5039

PIIC5040

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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03:3

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Cop

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2017

This

doc

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tatio

n de

scrib

es O

pen

Har

dwar

e an

d is

lice

nsed

un

der t

he C

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OH

L v.

1.1.

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may

redi

strib

ute

and

mod

ify th

is

docu

men

tatio

n un

der t

he te

rms

of th

e CE

RN

OH

L v.

1.1.

(h

ttp://

ohw

r.org

/CER

NO

HL)

. Thi

s do

cum

enta

tion

is d

istri

bute

d W

ITH

OU

T A

NY

EX

PRES

S O

R IM

PLIE

D W

AR

RA

NTY

, IN

CLU

DIN

G O

F M

ERC

HA

NTA

BILI

TY, S

ATIS

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Q

UA

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AN

D F

ITN

ESS

FOR

A P

ART

ICU

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PU

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Plea

se s

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1.1

for a

pplic

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1%R7 1k1%R5 1k

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2

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22

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44

55

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DD

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yrig

ht W

UT

2017

This

doc

umen

tatio

n de

scrib

es O

pen

Har

dwar

e an

d is

lice

nsed

un

der t

he C

ERN

OH

L v.

1.1.

You

may

redi

strib

ute

and

mod

ify th

is

docu

men

tatio

n un

der t

he te

rms

of th

e CE

RN

OH

L v.

1.1.

(h

ttp://

ohw

r.org

/CER

NO

HL)

. Thi

s do

cum

enta

tion

is d

istri

bute

d W

ITH

OU

T A

NY

EX

PRES

S O

R IM

PLIE

D W

AR

RA

NTY

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CLU

DIN

G O

F M

ERC

HA

NTA

BILI

TY, S

ATIS

FACT

ORY

Q

UA

LITY

AN

D F

ITN

ESS

FOR

A P

ART

ICU

LAR

PU

RPO

SE.

Plea

se s

ee th

e CE

RN

OH

L v.

1.1

for a

pplic

able

con

ditio

ns.

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C3

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+

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100nF

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max

imum

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ou

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cap

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r is 1

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We'r

e cu

rrent

ly u

sing

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s is f

ine

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ctor

of a

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2 PIC301 PIC302

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PIC13101 PIC13102

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PIC13201 PIC13202 COC132

PIC13301 PIC13302

COC133

PIC13401 PIC13402 COC134

PIC13601 PIC13602

COC136

PIC13701 PIC13702 COC137

PIC13801 PIC13802

COC138

PIC13901 PIC13902 COC139

PIC14001 PIC14002

COC140

PIC14101 PIC14102 COC141

PIC14201 PIC14202 COC142

PIC14401 PIC14402 COC144

PIC14701 PIC14702 COC147

PIC14801 PIC14802 COC148

PIC14901 PIC14902 COC149

PIC15001 PIC15002 COC150

PIC15101 PIC15102 COC151

PID101 PID102 COD

1

PID201 PID202 COD

2

PIIC101

PIIC102

PIIC103

PIIC104

PIIC105

PIIC106

PIIC107

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PIIC

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PIIC

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PIIC

2704

PIIC

2705

PIIC

2706

PIIC

2707

PIIC

2708

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8

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01

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COL9

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2

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PIC13202 PIC13301

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PIC13801 PIC13901

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PIC14801 PIC14901

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PITP601

PITP701

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PIC6401

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PIC13002

PIIC107

PIL601

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PIL701

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CC

BB

AA

7W

arsa

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nive

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echn

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yN

owow

iejsk

a 15

/19

7

LVD

S &

I2C

-28

.01.

2020

03:3

9:54

LVD

S_IF

C_D

AC

.Sch

Doc

Size

File

Rev

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tof A3

Zotin

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GN

DG

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1%R21 100

1%R22 100

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1%R19 100

1%R18 100

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Cop

yrig

ht W

UT

2017

This

doc

umen

tatio

n de

scrib

es O

pen

Har

dwar

e an

d is

lice

nsed

un

der t

he C

ERN

OH

L v.

1.1.

You

may

redi

strib

ute

and

mod

ify th

is

docu

men

tatio

n un

der t

he te

rms

of th

e CE

RN

OH

L v.

1.1.

(h

ttp://

ohw

r.org

/CER

NO

HL)

. Thi

s do

cum

enta

tion

is d

istri

bute

d W

ITH

OU

T A

NY

EX

PRES

S O

R IM

PLIE

D W

AR

RA

NTY

, IN

CLU

DIN

G O

F M

ERC

HA

NTA

BILI

TY, S

ATIS

FACT

ORY

Q

UA

LITY

AN

D F

ITN

ESS

FOR

A P

ART

ICU

LAR

PU

RPO

SE.

Plea

se s

ee th

e CE

RN

OH

L v.

1.1

for a

pplic

able

con

ditio

ns.

EEM

con

nect

or: I

O a

re L

VD

S, I2

C is

3V

3 LV

CM

OS,

P3V

3_M

P up

to

20m

A, P

12V

up

to 1

A.

I2C

_SD

AI2

C_S

CL

TP13

TP11

TP12

TP14

EEPR

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lato

rs


9 PIC2001 PIC2002

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1 PIC2201 PIC2202

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3 PIC2401 PIC2402

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8


9 PIC7001 PIC7002

COC70

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PIIC802

PIIC803

PIIC804

PIIC805

PIIC806

PIIC807

PIIC808

PIIC809

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PIIC

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PIIC8027

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PIIC8038

PIIC

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PIIC8043

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PIIC

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PIIC8047

PIIC8048

PIIC8049

COIC

8

PIIC901

PIIC902

PIIC903

PIIC904

PIIC905

PIIC906

PIIC907

PIIC908

PIIC909

PIIC

9010

PIIC

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PIIC9012

PIIC9013

PIIC9014

PIIC

9015

PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC9025

PIIC

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PIIC

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PIIC

9028

PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC

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PIIC9042

PIIC

9043

PIIC

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PIIC

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PIIC

9046

PIIC

9047

PIIC

9048

PIIC

9049

COIC

9

PIIC

3201

PIIC

3202

PIIC

3203

PIIC

3204

PIIC

3205

COIC

32

PIJ3701

PIJ3702

PIJ3703

PIJ3704

PIJ3705

PIJ3706

PIJ3707

PIJ3708

PIJ3709

PIJ3

7010

PIJ3

7011

PIJ3

7012

PIJ3

7013

PIJ3

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PIJ3

7015

PIJ3

7016

PIJ3

7017

PIJ3

7018

PIJ3

7019

PIJ3

7020

PIJ3

7021

PIJ3

7022

PIJ3

7023

PIJ3

7024

PIJ3

7025

PIJ3

7026

PIJ3

7027

PIJ3

7028

PIJ3

7029

PIJ3

7030

COJ37

PIR601

PIR602

COR6

PIR110

1 PIR

1102

COR1

1

PIR130

1 PIR

1302

COR1

3

PIR140

1 PIR

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COR1

4

PIR160

1 PIR

1602

COR1

6

PIR170

1 PIR

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7

PIR180

1 PIR

1802

COR1

8

PIR190

1 PIR

1902

COR1

9

PIR200

1 PIR

2002

COR2

0

PIR210

1 PIR

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1

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PIR2202

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2

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PIR2302

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3

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1 PIR

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COR5

1

PIR880

1 PIR

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8

PIR970

1 PIR

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7

PIR990

1 PIR

9902

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9

PIR101

01 PIR

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PIR141

01 PIR

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01 PIR

14402

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01 PIR

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01 PIR

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01 PIR

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01 PIR

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01 PIR

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PI

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02

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PITP1101

COTP11

PITP1201

COTP12

PITP1301

COTP13

PITP1401 COTP14

PIC1901 PIC2001

PIC2101 PIC2201

PIC2301 PIC2401

PIC3801

PIC6901 PIC7001

PIIC806

PIIC807

PIIC8018

PIIC8023

PIIC8027

PIIC8031

PIIC8034

PIIC8038

PIIC8043

PIIC8049

PIIC906

PIIC907

PIIC

9018

PIIC

9023

PIIC

9027

PIIC

9031

PIIC

9034

PIIC

9038

PIIC

9043

PIIC

9049

PIIC

3202

PIJ3701

PIJ3704

PIJ3707

PIJ3

7010

PIJ3

7013

PIJ3

7016

PIJ3

7019

PIJ3

7022

PIJ3

7025

PIR160

1

PIR170

1

PIR190

1

PIR200

1

PIR210

1

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PIR157

02

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3201

PIJ3

7027

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L POI2C0SCL

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3203

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A POI2C0SDA

PIIC8048

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PIIC8047

PIJ3702

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01

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P

PIIC804

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02

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PIIC803

PIJ3705

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P

PIIC8010

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02

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PIIC809

PIJ3708

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01

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DS20

P

PIIC8014

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02 NLLVDS30N

PIIC8013

PIJ3

7011

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P

PIIC

9048

PIJ3

7015

PIR160

02

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PIJ3

7014

PIR160

01

NLLV

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P

PIIC904

PIJ3

7018

PIR163

02

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PIIC903

PIJ3

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01

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P

PIIC

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PIJ3

7021

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6602

NLLVDS60N

PIIC909

PIJ3

7020

PIR1

6601

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P

PIIC9014

PIJ3

7024

PIR1

7002

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PIIC9013

PIJ3

7023

PIR1

7001

NLLV

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P

PIIC801

PIIC

8040

PIR160

2

PIIC805

PIIC

8042

PIR170

2

PIIC808

PIIC

8019

PIR180

2

PIIC

8012

PIIC

8021

PIR190

2

PIIC8017

PIIC

8020

PIIC

8022

PIIC

8039

PIIC

8041

PIR601

PIIC

8025

PIIC

8026

PIR

9702

PIIC

8028

PIR

1402

PIIC

8029

PIIC

8032

PIIC

8033

PIR

1302

PIIC

8035

PIIC

8036

PIR

1102

PIIC8044

PIIC901

PIIC

9040

PIR200

2

PIIC905

PIIC9042

PIR210

2

PIIC908

PIIC

9019

PIR2202

PIIC9012

PIIC

9021

PIR2302

PIIC

9017

PIIC

9020

PIIC

9022

PIIC

9039

PIIC

9041

PIR157

01

PIR17101

PIIC9025

PIIC

9026

PIR

8802

PIIC

9028

PIR

5102

PITP1401

PIIC

9029

PIIC

9032

PIIC

9033

PIR

10102

PIIC

9035

PIIC

9036

PIR

9902

PIIC

9044

PIIC

3205

PIR110

1 POSCKI

PIR130

1 POSDI

PIR140

1 POSDO

PIR510

1 POBUSY

PIR880

1 POCLRn

PIR970

1 POCSN

PIR990

1 POCSN0EXT

PIR101

01 POLDACn

PIC1902 PIC2002

PIC2102 PIC2202

PIC2302 PIC2402

PIC6902 PIC7002

PIIC802

PIIC

8011

PIIC

8015

PIIC

8016

PIIC

8024

PIIC

8030

PIIC

8037

PIIC

8045

PIIC

8046

PIIC902

PIIC

9011

PIIC

9015

PIIC

9016

PIIC

9024

PIIC

9030

PIIC

9037

PIIC

9045

PIIC

9046

PIR602

PIR180

1

PIR2201

PIC3802 PIIC

3204

PIJ3

7030

PITP1301

PIJ3

7028

PIJ3

7029

POBUSY

POCLRn

POCSN

POCSN0EXT

POI2C0SCL

POI2C0SDA

POLDACn

POSCKI

POSDI

POSDO

Appendix 2. Code used for tests and measurements

Listing Appendix 2.1: Code used for declaration of Servo module and all of its parameters

from migen import *from migen.build.platforms.sinara import kasli

from artiq.gateware.szservo import servo

from artiq.gateware.szservo.pads import ZotinoPads, SamplerPads, pgiaPads

from .eem2 import *# number of channels used for control

channels_no = 2

Kps = [0.1007 for i in range(channels_no)]

Kis = [839.19 for i in range(channels_no)]

plat = kasli .Platform(hw_rev="v1.1")

# numbers of EEM extentions to which particular boards are connected

sampler_conn = 3

sampler_aux = 2

zotino_conn = 4

# getting EEM extentions’ and theirs subsignals’ names

adc_io = Sampler.io(sampler_conn, sampler_aux)

dac_io = Zotino.io(zotino_conn)

# mapping EEM extensions’ signals to physical pins

plat.add_extension(adc_io)

plat.add_extension(dac_io)

# extracting name used by other functions

adc_eem = adc_io[sampler_aux][0].split("_")[0]

pgia_eem = adc_io[2][0].split("_")[0]

dac_eem = dac_io[zotino_conn][0].split("_")[0]

# creating pads wrapper

adc_pads = SamplerPads(plat, adc_eem)

pgia_pads = pgiaPads(plat, pgia_eem)

dac_pads = ZotinoPads(plat, dac_eem)

# creating params used by each of the modules used by Servo

adc_p = servo.ADCParams(width=16, channels=channels_no, lanes=int(channels_no/2),

t_cnvh=4, t_conv=57 − 4, t_rtt=4 + 4)

iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=16, word=16,

accu=48, shift=11, channel=3, profile=1)

dac_p = servo.DACParams(data_width = 24, clk_width = 2,

channels=adc_p.channels)

pgia_p = servo.PGIAParams(data_width = 16, clk_width = 2)

# initial values of PGIAs’ gains − for every amplifier there are two bits of information; all of them

# are concatenated into 16−bits−wide vector

pgia_init_val = 0x0000

# creating an instance of a Servo class

m = servo.Servo(adc_pads, pgia_pads, dac_pads, adc_p, pgia_p, iir_p, dac_p,

pgia_init_val, Kps, Kis)

m.submodules += adc_pads, pgia_pads, dac_pads

77


m.comb += m.start.eq(1) # PID controller’s start pin driven constantly high

clk_signal = Signal()

clk125 = plat.request("clk125_gtp")

m.specials += [

Instance("IBUFDS_GTE2", i_I = clk125.p, i_IB = clk125.n, o_O = clk_signal),

Instance("BUFG", i_I = clk_signal, o_O = m.cd_sys.clk)

]

plat.build(m, run=True, build_dir = "building/pid/{}ch/pgia{:0>4x}/Kp_{}_Ki_{}".format(

channels_no, pgia_init_val, Kps[0], Kis[0]), build_name = "top")

Listing Appendix 2.2: Code used for gaining access to corrseponding FPGA’s peripheral

signals and pins

from migen import *from migen.build.generic_platform import *from migen.genlib.io import DifferentialOutput

from artiq.gateware.szservo import pads as servo_pads

from artiq.gateware.szservo import servo

def _eem_signal(i):

n = "d{}".format(i)

if i == 0:

n += "_cc"

return n

def _eem_pin(eem, i, pol):

return "eem{}:{}_{}".format(eem, _eem_signal(i), pol)

class _EEM:

@classmethod

def add_extension (cls, target, eem, *args, **kwargs):

name = cls.__name__

target.platform.add_extension(cls.io(eem, *args, **kwargs))

print("{} (EEM){}) starting at RTIO channel {}"

.fromat(name, eem, len(target.rtio_channels)))

class Sampler(_EEM):

@staticmethod

def io(eem, eem_aux, iostandard = "LVDS_25"):

ios = [

("sampler{}_adc_spi_p".format(eem), 0,




) ,

("sampler{}_adc_spi_n".format(eem), 0,




78


) ,

("sampler{}_pgia_spi_p".format(eem), 0,






) ,

("sampler{}_pgia_spi_n".format(eem), 0,






) ,

] + [

("sampler{}_{}".format(eem, sig), 0,

Subsignal("p", Pins(_eem_pin(j, i, "p"))),

Subsignal("n", Pins(_eem_pin(j, i, "n"))),

IOStandard(iostandard)

) for i , j , sig in [

(2, eem, "sdr"),

(3, eem, "cnv")

]

]

if eem_aux is not None:

ios += [

("sampler{}_adc_data_p".format(eem), 0,

Subsignal("clkout", Pins(_eem_pin(eem_aux, 0, "p"))),

Subsignal("sdoa", Pins(_eem_pin(eem_aux, 1, "p"))),

Subsignal("sdob", Pins(_eem_pin(eem_aux, 2, "p"))),

Subsignal("sdoc", Pins(_eem_pin(eem_aux, 3, "p"))),

Subsignal("sdod", Pins(_eem_pin(eem_aux, 4, "p"))),

Misc("DIFF_TERM=TRUE"),


) ,

("sampler{}_adc_data_n".format(eem), 0,

Subsignal("clkout", Pins(_eem_pin(eem_aux, 0, "n"))),

Subsignal("sdoa", Pins(_eem_pin(eem_aux, 1, "n"))),

Subsignal("sdob", Pins(_eem_pin(eem_aux, 2, "n"))),

Subsignal("sdoc", Pins(_eem_pin(eem_aux, 3, "n"))),

Subsignal("sdod", Pins(_eem_pin(eem_aux, 4, "n"))),

Misc("DIFF_TERM=TRUE"),


) ,

]

return ios

class Zotino(_EEM):

@staticmethod

79


def io(eem, iostandard="LVDS_25"):

return [

("zotino{}_spi_p".format(eem), 0,






) ,

("zotino{}_spi_n".format(eem), 0,






) ,

] + [

("zotino{}_{}".format(eem, sig), 0,

Subsignal("p", Pins(_eem_pin(j, i, "p"))),

Subsignal("n", Pins(_eem_pin(j, i, "n"))),

IOStandard(iostandard)

) for i , j , sig in [

(5, eem, "ldac_n"),

(6, eem, "busy"),

(7, eem, "clr_n"),

]

]

80

jakub matyas - m-labs

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