jianhui zhang,copyright © 2015 pearson education, inc. 主板上的主要部件 总线(bus)...

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Copyright © 2015 Pearson Education, Inc. Jianhui Zhang, Ph.D., Associate Prof. College of Computer Science and Technology, Hangzhou Dianzi Univ. Email: [email protected]

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Page 1: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Jianhui Zhang, Ph.D., Associate Prof.

College of Computer Science and Technology, Hangzhou Dianzi Univ.

Email: [email protected]

Page 2: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Chapter 2:Data Manipulation

Computer Science: An OverviewTwelfth Edition

by J. Glenn Brookshear

Dennis Brylow

Page 3: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-3

Chapter 2: Data Manipulation

• 2.1 Computer Architecture• 2.2 Machine Language• 2.3 Program Execution• 2.4 Arithmetic/Logic Instructions• 2.5 Communicating with Other Devices• 2.6 Program Data Manipulation• 2.7 Other Architectures

Page 4: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-4

Computer Architecture

• Central Processing Unit (CPU) or processor– Arithmetic/Logic unit versus Control unit– Registers

• General purpose• Special purpose

• Bus• Motherboard

Page 5: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-5

Figure 2.1 CPU and main memory connected via a bus

Page 6: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

John von Neumann Model

Computer Architecture4 sub-system: storage, arithmetic logic unit(ALU)

control unit , input/output unit

CPU

storage

control unit

ALU

input output

Page 7: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

storage

CPU

Output device

interiorstorage

Externalstorage

Input device

peripheral equipment connected with CPU through the adapters on the ports

Page 8: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

adapter

CPU

Input device adapter Output

device

adapter

Externalstorage

How to connect these assembly unit

CS(chipset)

Bus interiorstorage

Page 9: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

“CPU”和“内部存储器”是两个例外:它们不需要通过适配器就能和总线连接。

或者说:只有外围设备才需要通过适配器和总线相连。

adapter Output deviceadapter

There are many types of BUSs

Each BUS connects with one adapter

CPU

Input device

adapter

Externalstorage

CS(chipset)

interiorstorage

Each adapter connects with BUS through slot /socket

“CPU”and“interiorstorage”are 2 exception:they needs not adapter and can connect with bus directly

Page 10: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

External device adapter

CPU

Internalstorage

外部存储器

Main board

Power adapter

EthernetadapterMonitor adapter

Conce-ntrator

Monitorsound

equipment

Mirco-phone

Voice adapter

mouse Key board

Main Engine

what are they?

Page 11: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

主板上的主要部件

总线 (Bus) 前端总线 (Front‐Side Bus, FSB) 【CPU芯片组】 内存总线 (Memory Bus)【内存芯片组】 高速图形总线【显卡芯片组】

• PCI‐E,AGP 外部存储器总线【硬盘适配器、光驱适配器芯片组】

• SATA, IDE,SCSI 低速设备总线(LPC) 

• 【BIOS芯片组】• 【键盘适配器、鼠标适配器、软驱适配器、…芯片组】

通用型总线【其它外设适配器芯片组】• USB (Universal Serial Bus) • PCI,ISA

内部总线 (Internal Bus) 【芯片组内部互联】

接口:插槽 (Slot),插座(Socket),端口(Connector/Port) CPU插槽/座,内存插槽,PCI(‐E)插槽,ISA插槽 鼠标端口,键盘端口,USB端口

芯片组 (Chipset) 北桥芯片 (North Bridge):CPU、内存、显卡 南桥芯片 (South Bridge):BIOS、其它外围设备适配器

BIOS (Basic Input/Output System)

Page 12: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 12

主板上硬件系统的基本结构

CPU

北桥芯片

前端总线

CPU插槽/座

内部总线

内存插槽

内存内存总线

显卡图形

总线

显卡插槽

PCI总线

ISA总线

PCI插槽

ISA插槽

BIOS

外存适配器

USB适配器

网络适配器

声音适配器

LPC总线

低速设备适配器芯片组

软驱适配器

键盘适配器

鼠标适配器 LPC总线

一组端口

芯片组

……

超级IO芯片组 南桥芯片

CMOS

Page 13: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

北桥芯片

PCI插槽

CMOS电池

BIOSSATA外存端口

IDE外存端口软驱端口

主板电源端口

超级IO芯片组

内存插槽

CPU插座

CPU风扇电源

CPU风扇基座 声音适配器

网络适配器

PCI-E插槽

外围设备端口

南桥芯片

Page 14: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Page 15: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

main / chipset / BUS

CPU&other chips

Internal storage

External storage External device

Network cardSound card …

Page 16: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-16

Stored Program Concept

A program can be encoded as bit patterns and stored in main memory. From there, the CPU can then extract the instructions and execute them. In turn, the program to be executed can be altered easily.

Page 17: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-17

Terminology

• Machine instruction: An instruction (or command) encoded as a bit pattern recognizable by the CPU

• Machine language: The set of all instructions recognized by a machine

Page 18: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-18

Machine Language Philosophies

• Reduced Instruction Set Computing (RISC)– Few, simple, efficient, and fast instructions– Examples: PowerPC from Apple/IBM/Motorola

and ARM• Complex Instruction Set Computing (CISC)

– Many, convenient, and powerful instructions– Example: Intel

Page 19: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-19

Machine Instruction Types

• Data Transfer: copy data from one location to another

• Arithmetic/Logic: use existing bit patterns to compute a new bit patterns

• Control: direct the execution of the program

Page 20: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-20

Figure 2.2 Adding values stored in memory

Page 21: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-21

Figure 2.3 Dividing values stored in memory

Page 22: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-22

Figure 2.4 The architecture of the machine described in Appendix C

Page 23: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-23

Parts of a Machine Instruction

• Op-code: Specifies which operation to execute

• Operand: Gives more detailed information about the operation– Interpretation of operand varies depending on

op-code

Page 24: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-24

Figure 2.5 The composition of an instruction for the machine in Appendix C

Page 25: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-25

Figure 2.6 Decoding the instruction 35A7

Page 26: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-26

Figure 2.7 An encoded version of the instructions in Figure 2.2

Page 27: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-27

Program Execution

• Controlled by two special-purpose registers– Program counter: address of next instruction– Instruction register: current instruction

• Machine Cycle– Fetch– Decode– Execute

Page 28: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-28

Figure 2.8 The machine cycle

Page 29: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-29

Figure 2.9 Decoding the instruction B258

Page 30: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-30

Figure 2.10 The program from Figure 2.7 stored in main memory ready for execution

Page 31: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-31

Figure 2.11 Performing the fetch step of the machine cycle

Page 32: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-32

Figure 2.11 Performing the fetch step of the machine cycle (continued)

Page 33: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-33

Arithmetic/Logic Operations

• Logic: AND, OR, XOR– Masking

• Rotate and Shift: circular shift, logical shift, arithmetic shift

• Arithmetic: add, subtract, multiply, divide– Precise action depends on how the values are

encoded (two’s complement versus floating-point).

Page 34: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-34

Figure 2.12 Rotating the bit pattern 65 (hexadecimal) one bit to the right

Page 35: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-35

Communicating with Other Devices

• Controller: An intermediary apparatus that handles communication between the computer and a device– Specialized controllers for each type of device– General purpose controllers (USB and

FireWire)• Port: The point at which a device connects to a

computer • Memory-mapped I/O: CPU communicates with

peripheral devices as though they were memory cells

Page 36: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-36

Figure 2.13 Controllers attached to a machine’s bus

Page 37: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-37

Figure 2.14 A conceptual representation of memory-mapped I/O

Page 38: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-38

Communicating with Other Devices (continued)

• Direct memory access (DMA): Main memory access by a controller over the bus

• Von Neumann Bottleneck: Insufficient bus speed impedes performance

• Handshaking: The process of coordinating the transfer of data between components

Page 39: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-39

Communicating with Other Devices (continued)

• Parallel Communication: Several communication paths transfer bits simultaneously.

• Serial Communication: Bits are transferred one after the other over a single communication path.

Page 40: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 2-40

Data Communication Rates

• Measurement units– Bps: Bits per second– Kbps: Kilo-bps (1,000 bps)– Mbps: Mega-bps (1,000,000 bps)– Gbps: Giga-bps (1,000,000,000 bps)

• Bandwidth: Maximum available rate

Page 41: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Programming Data Manipulation

• Programing languages shields users from details of the machine:– A single Python statement might map to one,

tens, or hundreds of machine instructions– Programmer does not need to know if the

processor is RISC or CISC– Assigning variables surely involves LOAD,

STORE, and MOVE op-codes

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Page 42: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Bitwise Problems as Python Code

print(bin(0b10011010 & 0b11001001))# Prints '0b10001000'

print(bin(0b10011010 | 0b11001001))# Prints '0b11011011'

print(bin(0b10011010 ^ 0b11001001)) # Prints '0b1010011'

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Page 43: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Control Structures

• If statement:if (water_temp > 140):

print('Bath water too hot!')

• While statement:while (n < 10):

print(n)n = n + 1

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Page 44: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Functions• Function: A name for a series of

operations that should be performed on the given parameter or parameters

• Function call: Appearance of a function in an expression or statement

2-44

x = 1034y = 1056z = 2078biggest = max(x, y, z)print(biggest) # Prints '2078'

Page 45: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Functions (continued)

2-45

• Argument Value: A value plugged into a parameter

• Fruitful functions return a value• void functions, or procedures, do not

return a valuesideA = 3.0sideB = 4.0# Calculate third side via Pythagorean Theoremhypotenuse = math.sqrt(sideA**2 + sideB**2)print(hypotenuse)

Page 46: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Input / Output

# Calculates the hypotenuse of a right triangle

import math

# Inputting the side lengths, first trysideA = int(input('Length of side A? '))sideB = int(input('Length of side B? '))

# Calculate third side via Pythagorean Theoremhypotenuse = math.sqrt(sideA**2 + sideB**2)

print(hypotenuse)

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Page 47: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Marathon Training Assistant# Marathon training assistant.

import math

# This function converts a number of minutes and # seconds into just seconds.def total_seconds(min, sec):

return min * 60 + sec

# This function calculates a speed in miles per hour given# a time (in seconds) to run a single mile.def speed(time):

return 3600 / time

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Page 48: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Marathon Training Assistant (continued)# Prompt user for pace and mileage.pace_minutes = int(input('Minutes per mile? '))pace_seconds = int(input('Seconds per mile? '))miles = int(input('Total miles? '))

# Calculate and print speed.mph = speed(total_seconds(pace_minutes, pace_seconds))print('Your speed is ' + str(mph) + ' mph')

# Calculate elapsed time for planned workout.total = miles * total_seconds(pace_minutes, pace_seconds)elapsed_minutes = total // 60elapsed_seconds = total % 60

print('Your elapsed time is ' + str(elapsed_minutes) +' mins ' + str(elapsed_seconds) + ' secs')

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Page 49: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc.

Figure 2.15 Example Marathon Training Data

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Time Per Mile Total Elapsed Time

Minutes Seconds Miles Speed (mph) Minutes Seconds

9 14 5 6.49819494584 46 10

8 0 3 7.5 24 0

7 45 6 7.74193548387 46 30

7 25 1 8.08988764044 7 25

Page 50: Jianhui Zhang,Copyright © 2015 Pearson Education, Inc. 主板上的主要部件 总线(Bus) 前端总线(Front‐Side Bus, FSB) 【CPU 芯片组】 内存总线(Memory Bus

Copyright © 2015 Pearson Education, Inc. 0-50

Other Architectures

• Technologies to increase throughput:– Pipelining: Overlap steps of the machine cycle– Parallel Processing: Use multiple processors

simultaneously• SISD: No parallel processing• MIMD: Different programs, different data• SIMD: Same program, different data