layout guidelines

8132019 Layout Guidelines

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Layout Guideline For High Speed Designs

1

Purnachandar Poshala

Applications Manager - HSP



What does Signal Integrity mean to YOU

Ringing

OvershootUndershoot

Monotonicity

Crosstalk

Signal-to-Noise Ratio (SNR)

Timing Jitter

Duty-cycle jitter

Signaling Topologies

Eye performance

Impedance discontinuity

Signal TerminationsReturn Loss

Insertion Loss

Pk-to-pk data jitter

Channel modeling

ISI degradation Impedance controlNoiseDistortion

Bit-error-rate On-die termination (ODT) Pre-emphasisDe-emphasis

Return Path discontinuity

ome o ese r ore



Key points on SI

bullbull SSignal IIntegrity (SI) ensures signals

ndash are of sufficient quality to reliably transmit their required information

ndash do not cause problems to themselves or to other components in the system

bullbull SISI applies to Digital Analog and Power electronics

bullbull SISI issues are more common now because

ndash electronics are more dense

ndash chips have lower voltage higher speeds

bullbull SISI is multidisciplinary ndash needs knowledge of RF digital systems

ndash circuit design EM modeling

bullbull SISI assures the circuit design operates as intended (in the first-pass) and theseprinciples must be designed in

Correct design relies on experience best practices analysisCorrect design relies on experience best practices analysisand simulation to ensure desired signal qualityand simulation to ensure desired signal quality



Examples of SI issues (12)

Courtesy Rajen Murugan



Transmission Line

When must we treat a trace like a transmission line

If the trace length is bigger than

L = trace lengthtR = rise time (10 to 90)

tPR = signal propagation rate For FR4 150psin lt tPR lt 175psin

PR

R

t

t L

sdot

ge

6

5

tR can be approximated as

max7

2

f t R

sdot=

PRt f L

sdotsdotsdotge

67

2

max

Under the below condition the trace needs to be considered and analyzed as

transmission line



Transmission Line

R = series resistance of the conductor per unit lengthL = series inductance of the conductor per unit lengthC= capacitance due to dielectric layer per unit length

How to treat a transmission line

6

G= admittance due to dielectric layer per unit length

β α ω ω γ jC jG L j R +=++= ))(( Propagation Equation

C L

C jG L j R Z =

+

+=)()(0

ω ω Characteristic Impedance

Lossless trace



Transmission Line reflection

Reflection coefficient gives the ratio between the reflected voltage amplitude and

the incident voltage amplitude at the receiver

Vs Zo

R s

R L

A B

ρA ρB

0

0

Z R Z R

L

L

+

minus= ρ

7

Rs clock source output impedanceRL terminationZ0 transmission line characteristic impedance

Ideally ρ must be 0 meaning RL=Z0 Any discontinuity in the impedance value duringthe signal propagation path will generate reflections




8

Propagation Delay 550ps



EMI origin

The Electric Field around a conductor is proportional to the voltage or current whichflows

Single Ended maximum radiation (TEM)

Balanced Differential Ended coupled electric fields are tied up and cannotescape

Unbalanced Differential Ended excess in the fringing field

9

Single Ended Balanced

DifferentialUnbalancedDifferential



EMI origin

Emissions due non-idealities

10



EMI reduction design

Field distribution in transmission line

11

How to further reduce Shield traces to GND on both sides




Differential signal

12

Minimize the imbalances between the conductors of each pair

Close coupling between the conductors of each pair



Signal Routing coupling and crosstalk

To reduce coupling we shouldbull Increase Isolation between aggressor and victimbull Isolate the Power suppliesbull Make sure the ground is low impedance to reduce ground bouncebull

Coupling Zones

13

bullSingle Ended signals return current density drops to 4 when DH =5 anddrops to 1 when DH = 10bull Differential signals

bulldistance between two pairs should be gt2Sbull distance between a pair and SE signal trace gt3S or even better to

different planebull guard ground trace or ground fill distance gt2S



Signal routing minimizing the skew

Minimize the propagation time difference between the two signals of adifferential pair A mismatch generates common mode noise that will be emittedas radiation

The propagation velocity on a board is given by

r

cV

ε =

14

c = 02998 mmps speed velocityεr = dielectric constant ( for FR-4 is 42)

The reciprocal will give us the propagation time for 1mm board trace For FR-4

case this is 684ps

Match the lengths of a pair within 120 of the signal rise time



Analog and Digital Ground

bull Reasons to not split the ground plane1 Strong chance for error in making the split

2 Could cause a large inductive loop which gives rise to noise

bull FactWith proper decoupling and grounding many single GND planesperform as good as split ground planes

15



Routing Guidelines for SI

1 Do not make discontinuities in the reference plane of signals

2 Use only straight or 45 degree bending traces Do not use 90 degreebendings

3 Do try to remove stubs If unavoidable keep the length minimum4 Draw same traces if possible

5 Draw traces with the same length

7 Use higher Z0 traces for multi-drop systems for compensation8 Increase spacing to reduce crosstalk

9 Place ground vias next to signal vias

10 Draw ground and power traces as wide as possible

11 Reduce the stub length of de-coupling capacitors

12 Place a ground net next to a power net



983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086

The length of a trace use to connect a capacitor has a big impact on parasitic inductance and resistance

of the mounting This trace should be as short and wide as possible Wherever possible minimize the

trace by locating vias near the solder pad landing Further improvements can be made to the mounting

by placing vias to the side of capacitor lands or doubling the number of vias as shown in Figure 110

below

trace

pad

via

Mounting geometry for reduced inductance

Via-in-pad

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Power supply

Poor Bypassing

DO NOT have vias between bypass capsand active device ndash Visualize the highfrequency current flow

Ensure Bypass caps are on same layer

as active component for best results

Route vias into the bypass caps andthen into the active component

18

Good Bypassing

e more v as e e er

The wider the traces the better

The closer the better(lt05cm lt02rdquo)

Two or Multi-Layer Ceramic surfacemounting capacitors in parallel shouldbe placed at each VCC pin



Rule 1 Donrsquot make discontinuities in thereference plane

s

G

s

Gw

3w

bull There should be no discontinuities in the reference plane within 3W

s

G

s

G



Rule 2 Use straight or 45 degree bendingtraces Do not use 90 degree bendings

bull Use straight lines if possible

bull If bending is really needed use only 45 degree bending

bull 90 degree bendings induce a parasitic capacitance of ~03pF



Rule 3 Do try to remove stubs Ifunavoidable keep the length minimum

bull Stubs create impedance discontinuities causing mismatch and therefore may

cause reflections and degrading return-loss performance try

minimizingeliminating them on high-speed signaling paths



Rule 4 Draw same traces if possible

bull

bull For differential lines this is critical



Rule 5 Draw traces with the same length

bull Length-matching is critical on differential interfaces to achieve good SIon differential parameters and minimize differential-to-common modeconversions



Rule 6 Keep the space of differential linesconstant

bull The differential Z0 can be different with a different space

bull Uniform spacing on differential pairs is critical for impedance uniformityalong trace-length



Rule 8 Reduce crosstalk

bull Separate traces as far as possible



Rule 9 Place ground vias next to SignalVias

S1

GND

S1

S2

S1

S2

bull Distance between S1 via and GND via needs to be calculated to havesimilar Z0 as traces

S2GND



Rule 10 Draw power and ground as wideas possible

vdd

gnd

vdd

gnd

bull Reduces Static and Dynamic IR drop impact

bull Stitch PG planes across layers with vias as much as possible



Rule 11 Reduce the stub length for de-coupling capacitors

bull Stub length increases inductance which causes bigger power noise



What does Signal Integrity mean to YOU

Ringing

OvershootUndershoot

Monotonicity

Crosstalk

Signal-to-Noise Ratio (SNR)

Timing Jitter

Duty-cycle jitter

Signaling Topologies

Eye performance

Impedance discontinuity

Signal TerminationsReturn Loss

Insertion Loss

Pk-to-pk data jitter

Channel modeling

ISI degradation Impedance controlNoiseDistortion

Bit-error-rate On-die termination (ODT) Pre-emphasisDe-emphasis

Return Path discontinuity

ome o ese r ore



Key points on SI


















Transmission Line





PR

R

t

t L

sdot

ge

6

5


max7

2

f t R

sdot=

PRt f L

sdotsdotsdotge

67

2

max


transmission line



Transmission Line



6



C L

C jG L j R Z =

+

+=)()(0


Lossless trace






Vs Zo

R s

R L

A B

ρA ρB

0

0

Z R Z R

L

L

+

minus= ρ

7






8




EMI origin





9





EMI origin


10





11





Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd









Key points on SI


















Transmission Line





PR

R

t

t L

sdot

ge

6

5


max7

2

f t R

sdot=

PRt f L

sdotsdotsdotge

67

2

max


transmission line



Transmission Line



6



C L

C jG L j R Z =

+

+=)()(0


Lossless trace






Vs Zo

R s

R L

A B

ρA ρB

0

0

Z R Z R

L

L

+

minus= ρ

7






8




EMI origin





9





EMI origin


10





11





Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd













Transmission Line





PR

R

t

t L

sdot

ge

6

5


max7

2

f t R

sdot=

PRt f L

sdotsdotsdotge

67

2

max


transmission line



Transmission Line



6



C L

C jG L j R Z =

+

+=)()(0


Lossless trace






Vs Zo

R s

R L

A B

ρA ρB

0

0

Z R Z R

L

L

+

minus= ρ

7






8




EMI origin





9





EMI origin


10





11





Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd









Transmission Line



6



C L

C jG L j R Z =

+

+=)()(0


Lossless trace






Vs Zo

R s

R L

A B

ρA ρB

0

0

Z R Z R

L

L

+

minus= ρ

7






8




EMI origin





9





EMI origin


10





11





Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd












Vs Zo

R s

R L

A B

ρA ρB

0

0

Z R Z R

L

L

+

minus= ρ

7






8




EMI origin





9





EMI origin


10





11





Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd










8




EMI origin





9





EMI origin


10





11





Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd









EMI origin





9





EMI origin


10





11





Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd









EMI origin


10





11





Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

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via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd











11





Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

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via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd










Differential signal

12







Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd











Coupling Zones

13









r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd












r

cV

ε =

14



case this is 684ps








15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd













15















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd





















983120983144983161983155983145983139983137983148 983116983137983161983151983157983156 983107983151983150983155983145983140983141983154983137983156983145983151983150983155 983107983151983150983156983086





below

trace

pad

via


Via-in-pad

983110983145983143983157983154983141 983089983092983086983088983098 983107983137983152983137983139983145983156983151983154 983152983148983137983139983141983149983141983150983156 983143983141983151983149983141983156983154983161 983142983151983154 983145983149983152983154983151983158983141983140 983149983151983157983150983156983145983150983143 983145983150983140983157983139983156983137983150983139983141



Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd









Power supply

Poor Bypassing





18

Good Bypassing

e more v as e e er







s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd










s

G

s

Gw

3w


s

G

s

G
















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd






















bull


















S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd























S1

GND

S1

S2

S1

S2


S2GND




vdd

gnd

vdd

gnd










vdd

gnd

vdd

gnd







layout guidelines

Documents