lecture 4 - number representations, dsk hardware, assembly programming · 2014-02-12 · bit...

Colorado State University Dept of Electrical and Computer Engineering ECE423 – 1 / 30

Lecture 4 - Number Representations, DSKHardware, Assembly Programming

James Barnes ([email protected])

Spring 2014

References


The next two lectures will focus on data types, hardware and programming (C,assembly). References:

● TRETTER: Data types and number representations – Tretter Chapter 1, onE-reserve at library

● WIKI: Fixed Point Arithmetic - Wikepediahttp://en.wikipedia.org/wiki/Fixed-point_arithmetic

● CHAISSING: Architecture and Instruction Set of the C6x Processor -Chaissing 2005, Chapter 3

● TI: TMS320C6000 CPU and Instruction Set Reference Guidehttp://www.engr.colostate.edu/ECE423/docs/spru189f.pdf

http://en.wikipedia.org/wiki/Fixed-point_arithmetic

http://www.engr.colostate.edu/ECE423/docs/spru189f.pdf

Data Types, Number Representations

❖ References

Data Types, NumberRepresentations

❖ C Data types vsC671X Core Data Units

❖ Fixed Point Numbers

❖ Addition Overflow❖ Representing SignedFixed-point Numberswith Integers (QfNotation)

❖ Addition/Multiplicationand Normalizing.

❖ IEEE Floating PointNumbers❖ Floating Point NumberTypes

❖ Precision of SinglePrecision Floating PointNumbers

C6713 Hardware

C6713 AssemblyLanguage Programming


C Data types vs C671X Core Data Units


● C specifies a number of data types based on arithmetic type (fixed pt vs float,signed vs unsigned)

● The DSP processor is register-oriented. The data types are based on howmuch of a register is required to hold the data

● In assembly programming, the only time the arithmetic type is recognized isin arithmetic instructions

C type Width C671X Name C671X Load C671X ArithInstruction Instruction

char, signed char, uchar 8 BYTE LDB1, LDBU ABS A0short, signed short, ushort 16 HWORD LDH1,LDHU ABS A0int, signed int, uint 32 WORD LDW,LDWU ABS A0– 40 LONG (LDB and LDW) ABS A1:A0float 32 float LDW ABSSP A0double 64 double LDDW ABSDP A1:A0

1sign-extended

Fixed Point Numbers


● C considers all fixed point numbers to be integers (radix pt to right of LSB).For integers, the radix point is just a convenience for humans.

● C type unsigned int:

✦ valdec =

31∑

n=0

dn2n, range [0, 232 − 1]

✦ Rules for unsigned integer different than for signed integers. DSP chiphas separate instructions for unsigned integer, for example ADDU

● C type int:

✦ valdec = −d31 ∗ 231 +

30∑

n=0

dn2n, range [−231, 231 − 1]

✦ d31 is the sign bit, 1 ⇒ negative✦ Arithmetic is 2’s complement

Addition Overflow


● Overflow can occur; two criteria (tests)

1. Result has different sign than both operands (cannot get overflow whenoperand signes different).

2. Carry-out of sign bit is different than carry-in of sign bit.

● DSPs can clamp result to maximim or minimum (”saturate”), ex. SADD

Representing Signed Fixed-point Numberswith Integers (Qf Notation)


● Binary point of N bit number is f positions to the left of the LSB, wheref=[0,N-1] (binary point cannot be to the left of the sign bit)

● User must manage movement of binary point - DSP has no knowledge ofbinary point

● Qf or Qm : f representation:

● valdec = 2−f· (−d312

31 +

30∑

n=0

dn2n)

● DSP frequently uses Q15 with 16b words. In Q15, values range from[−1, 1− 2−15].

Addition/Multiplication and Normalizing.


● Under addition, the binary point does not move.

✦ Addition overflow can occur as with integers.

● Under multiplication, the binary point moves to the left. Ex: multiplying two 16bit numbers results in a 32 bit number. For Q15, the binary point will be 30positions to the left of the LSB (to the right of the sign bit) and there will betwo sign bits (sign extension).

✦ To reduce the answer to a Q15 result, the 32 bit number must beright-shifted by 15 bits and the lower 16 bits used.

● Example with Q0.2 (in class).

IEEE Floating Point Numbers


● float: 32b single precision - 6-8 decimal places of precision● double: 64b double precision - 15-17 decimal places of precision● Organization of float as stored in memory.

Floating Point Number Types


● 5 float number categories

Type e f Value(dec)

Infinity 255 0 (−1)s · ∞

NAN 255 6= 0 undefinedNormal 1≤e<255 6= 0 (−1)s · 2e−127 · (1 + f)

Denorm 0 6= 0 (−1)s · 2−126 · f

Zero 0 0 (−1)s · 0 (note: ±0)

● NORM (”normal” or ”normalized”)

✦ has biased exponent 2e−127; the ”real” range of the exponent is [-126,127]

✦ mantissa has implied 1, ”real” range is [1, 1 + (1− 2−23)]

✦ Range [2−126, (2− 2−23) · 2127]

Precision of Single Precision Floating PointNumbers


● NORMs have the same relative precision over their entire range

✦ e=1: 8 · 106 values in range [2−126, 2−125− 2−149], step size 2−149

✦ e=2: 8 · 106 values in range [2−125, 2−124− 2−148], step size 2−148

and so forth. For a given mantissa value, as the step size increases, the numbervalue increases proportionately such that the relative precision remains constant( 1

8·106).

● DENORMs have reduced precision.

✦ The smallest DENORMs have 100% step size (2−149to2 · 2−149)

C6713 Hardware

❖ References


C6713 Hardware❖ C6713 High-LevelBlock Diagram

❖ CPU Functional Units

❖ Instruction Fetch❖ Register and BusArchitecture❖ General vs SpecialPurpose Registers

❖ Special PurposeRegister Map

❖ Functional Units



C6713 High-Level Block Diagram


CPU Functional Units


Instruction Fetch


● Instructions are fetched up to eight at a time in 256-bit wide “fetch packets”.● Each instruction occupies a 32-bit slot.● The human assembly writer, optimizing compiler, or optimizing assembler indicates

which instructions can be executed in parallel and the fetch packet is written toinstruction memory with that information.

Reference: TI

Register and Bus Architecture


● 16 32b registers in A and B register stack● Bus structure

✦ Each functional unit can write to any register in its stack✦ Each functional unit can take input operands from any register in its stack✦ There are cross-paths which allow a functional unit to take one operand

from the other stack

General vs Special Purpose Registers


Special-purpose registers vs general purpose: any register can be used forcomputation but...

● Registers A1, A2, B0, B1, and B2 are used for conditionals (example later)● Input operands to a function call are placed in A4,B4,A6,B6,...● Return value of function placed in A4● Function return address (PC+1 for function call) is placed in B3 WHEN

control passes to the function

The processor will automatically save and restore registers A0-A9 and B0-B9during a ”context switch”, which happens during a function call.

Special Purpose Register Map


Notice the form of the asm function prototype.

Functional Units


Name Function(s) Arithmetic Type

D ALU, memory access fixed pt onlyL ALU fixed pt, floatM Multiply only fixed pt, floatS ALU, bit manipulation, branch instructions fixed pt, float

Operation Mnemonic Functional Unit Delay SlotsLatency (clock cycles) (clock cycles)

Fixed Pt Arith, Logic – 1 0Multiply MPY 1 1Load LDH, LDW 1 5Branch B 1 6DP Multiply MPYDP 4 9

C6713 Assembly Language Programming

❖ References


C6713 Hardware


❖ Why/Why NotAssembly?

❖ Format of AssemblyInstruction❖ Register andLoad/Store Cross-Paths❖ Note on AddressingMemory

❖ Initializing Pointerswith MVKH, MVKL

❖ Calling AssemblyFunctions (PassingArguments)

❖ Program Flow(Conditionals andBranches, Loops)

❖ Instructions thatRequire Wait States(NOP)

❖ Functional Unitfixed-point Instructions

❖ Functional Unitfloating-point Instructions


Why/Why Not Assembly?


● Plusses

✦ Speed

■ Compiler is good at finding parallel operations, but humans can dobetter

■ Re-ordering of instructions and re-use of register results can reducenumber of LOAD/STORE operations or make better use of NOP waitcycles

✦ Smaller program size by better use of registers for scratch memory✦ Good way to learn the hardware

● Minuses

✦ Slower development✦ For a complex program, an optimizing compiler may do better than the

human

● Linear assembly is a compromise between C and ”straight” assembly

✦ Assembler assigns registers, chooses functional units, finds instructionsthat can be executed in parallel, puts in delays (NOPs). User choosesinstructions, defines variables and program flow.

Format of Assembly Instruction


Register and Load/Store Cross-Paths


Note:

● The destination must be on the same side (A vs B) as the functional unit● For LDx instructions, ”the same side as” means the side the address pointer

register is on.

Note on Addressing Memory


● Memory addresses are 32b wide● Memory is byte-addressable● There are two memory addressing modes: linear (used here) and circular

(discussed later).● The pointer post-increment/post-decrement operation does the right thing

depending on the type of the LD/ST instruction

✦ ExLDW .D1 *A0++,A7will increment A0 by 4

Initializing Pointers with MVKH, MVKL


How do you initialize a pointer to memory?

1. ZERO , but what if you want to access a non-zero location?2. MVKH,MVKL

● Must be applied in right order (see example)

Calling Assembly Functions (PassingArguments)


● We saw that function arguments are passed in regs A4,B4,...

✦ long (40b integer) arguments and results occupy two adjacent

● When calling ASM from C, the C compiler will put extra instructions in thecompiled program to save A0-A9 and restore them after the ASM functioncall is completed.

Program Flow (Conditionals and Branches,Loops)


● ANY instruction can be made conditional. If the condition (conditional registervalue) is false (all 0’s), the instruction is not executed

● Making a loop requires

1. A label2. A conditional register3. A branch statement

(In-class example)

Instructions that Require Wait States (NOP)


● The following instructions that we will use require wait states: LDx, STx,B, MPY

● Register transfers, ADD,SUB are all 1-cycle● How to use delay slots: instead of NOP: do something useful that does not

depend on results of the instruction needing wait states.

(In-class example).

Functional Unit fixed-point Instructions


Functional Unit floating-point Instructions


lecture 4 - number representations, dsk hardware, assembly programming · 2014-02-12 · bit...

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