Local Trigger Control Unit prototype

M. Della Pietra, A. Di Cicco, P. Di Meo, G. Fiorillo, P. Parascandolo

• LTCU discriminates the 18 inputs comparing them with a remote controlled threshold (one for each input). It can mask the noisy inputs

•It gives as output two Trigger proposals (T0 and T1), each one coming from FastOR of 9 inputs.

• It measures the rate of Trigger proposals for each input.

• All the board functionalities are driven by a remote controller through RS232

LTCU

9

T1

T29 TCU

32 from v791

• 1 board for each of 20 Racks per chamber (80 in total) where the induction II and collection planes are cabled in

• It receives as input 9 + 9 analogical 32 coming from the v791 boards (generally 9 of 2nd induction and 9 of collection)

LTCU Prototype overview

CH_out

Xilinx Spartan 2

RS_232

DAC

PC

v7

93

No I

np

ut

VTh (from induction II plane)

(from collection plane)

9

9

9

9

BACK FRONT

TCU

VT

h

Induction II plane signal

Collection plane signal

18 discriminators

v791

T1n

T2n

Pulse Test

LTCU prototype layout diagram

Pulse Test

Oscillator10 MHz

Channel Out Ch_out

LTCU – Input for 1ch

RC

filte

r

n from v791 Dn to FPGA

SDATA from FPGA

SCLK from FPGA

TL712 - Discriminator

DAC

Vref = ~ 250 mV

8 bit = 256 step 0.1 mV step

signal from FPGA

LM6171 – LM6172 Voltage follower to drive discriminator

input

Test pulse input

60 KHz Noise filter

-+ -

+

-

+

TLC5628C 8bit – 8ch

serial

RS232 in\out2 FastOR out 18x1 Mux out VME controller in\out

18 TL711 discriminatorsTLC5628C 8bit – 8ch serialXILINX Spartan 2 XC2S100 – 5PQ208

LTCU prototype

Front

Back

18 ASum input

No inputPower supply input

10 MHz OscillatorLM6171 - Input voltage followersLM6172 to drive threshold discriminators input

LTCU – FPGA block diagram

RS_232interface

INPUT InterfaceMask & fast OR

SyncFired

channelsrecorder

Internal Xilinx

Spartan 2 RAM

Time window

Read mask Write mask

Read cnt

Write DACDAC interface

4

9

9

18 18

D[17-0]

Test pulse

SDATA

SCLK

3

3

T1

T2

D[8-0]

D[17-9]

S_IN

S_OUT

MUX18D[17-

0]

Read channel

Chout

Status of FPGA logic design

• RS232 interface logic are implemented and simulated

• Test pulse and DAC logics are under test on board

• Input interface and FastOR are implemented

• Mask block and fired channel recorder must be designed

LTCU – FPGA contents: schematic

RS232 – interface block

FastOR block

LTCU - RS232 interface• Receives RS232 serial data:

– Write mask: 4 byte (1 Control Word + 3 byte data);

– Read mask: 1 byte (CW);– Write DAC: 3 byte (1 CW + 2 byte data);– Read cnt: 2 byte (1 CW + 1 byte data);– Time window: 1 byte (CW);– Test pulse: 1 byte (CW);– Read channel: 2 byte (1 CW + 1 byte data).

• Gives in output:– External signal: RS232 serial out, 3 signals for

each DAC, 4 test pulse signals; – Internal signal: write mask words, read channel

word, read count word, time window signal

LTCU - RS232 interface: schematic

10 bit SIPO input register and

RS232 controller Operation controller

Control word decoder

DAC controller

Read Cnt, Mask, Time window and Read channel controller

RS232 datasheet

• Asyncronous one directional two data lines bus

• Every transfer is composed by start bit, 8 bit data (from LSB to MSB), stop bit.

• Rate: 9600 bps (100s pulse duration)• Lines standby state: H

LTCU - RS232 controller

• Recognizes start transition.• Gives ten sampling pulses:

– First pulse after 50s from falling edge of the start transition

– Then every 100s

• Gives load pulse after stop bit.• Data are stored in an external SIPO 10 bit

register each sampling pulse

LTCU - RS232 controller: schematic

Start detector and sync block

Sampling pulses generator

Load and reset generator

Simulation input conditions:

• 1 byte data: 01010101 (55\HEX)

• data rate: 9600 bps

LTCU – RS232 controller: simulation

• Input data pulse duration: 100 s • First sampling pulse 50 ns after Start bit H-L transition• Sampling pulse period after first: 100 s

Data are correctly stored

LTCU – FPGA operation• WRITE_MK: mask input channel. Control word byte:

00100000• READ_MK: read which channels are masked. CW

byte: 01100000• WRITE_DAC: set discriminators threshold. CW byte:

00010000• READ_CNT: read channel hits from memory. CW

byte: 01010000• TEST_P: test pulse mode. CW byte: 000010tt (2 LS

bits to select channels to test)• T_WIN: set time window to count fired input. CW

byte: 000001ww (2 LS bits to select time window width)

• READ_CH: set one input channel to output. CW byte: 11000000

LTCU – Control word decoder

• Receives 1 byte data

• Decodes the control word received

• Give a different signal for each control word

LTCU – Control word decoder: schematic

LTCU – Operation controller

• FSM designed in ONE HOT logic;• Receives signal from Control word

controller;• Gives different enable signal for

each controller of RS232 interface;• Give test pulse and time window

signals.

LTCU – Operation controller: schematic

Read mask: 1 states

Write mask: 4 states

Write DAC: 3 states

Read cnt: 2 states

Test pulse: 1 states

Time windows width

2 LS bit decoder

Time window: 1 states

2 LS bit decoder

Read channel: 2 states

LTCU – Operation controller: simulation

• First LOAD pulse enables Control word controller

• Control word controller decodes Write DAC command and gives a pulse on WRITE_DAC line

• After WRITE_DAC pulse the FSM gives 2 pulse to store 2 byte data

EX: Write DAC

Data are correctly stored

DAC datasheet (I)• TLC5628 – octal 8bit DAC;• Serial interface digital data input;• Digital data are clocked into internal DAC serial

register on the falling edge of the clock signal;• DAC output are updated only when LOAD

becomes low (L);• 12 bit data transmission: 3bit DAC channel + 1bit

range RNG (fixed to L) + 8bit voltage code;

DAC datasheet (II)• Setup time data input tsu (DATA-CLK): min

50ns;

• Hold time data input tv (CLK-DATA): min 50ns;

• Setup time clock eleventh falling edge to load pulse tsu (CLK-LOAD): min 50ns;

• LOAD pulse duration tw: min 250 ns;

• Setup time load to new clock transmission tsu (CLK-LOAD): min 50ns;

• Clock frequency: max 1 MHz;

LTCU - DAC controller

• Receives two byte data:• LS byte: CODE [7-0]

• MS byte: XXX A1_DAC A0_DAC A2_CH A1_CH A0_CH

• Give serial clock, serial data and load to selected DAC on board

LTCU - DAC controller: schematic

Two PISO input registers

DAC address decoder

Serial Clock and shift pulse generator

Outputs

Load and reset generator

Simulation input conditions:

• MS byte: 000 00 001 (01\HEX): DAC0 – Channel B selected

• LS byte: 01010101 (55\HEX)

LTCU - DAC controller: simulation

• Clock pulse duration: 1.6 s• Setup time (DATA-CLOCK): 800 ns

• Hold time (CLOCK-DATA): 800 ns

• Load pulse duration: 300 ns

• Last bit hold time (CLOCK-DATA): 400 ns

• Setup time (CLOCK-LOAD): 100 ns

Datasheet conditions respected

LTCU – FPGA preliminary occupancy

Occupancy 11%

LTCU – Control Software

• LTCU prototype is controlled via RS232 by LTCU Control software developed in NI Labview;

• The LTCU Control drives all the boad functionalities;

• Software is partially developed: ready up to now DAC threshold controller and Test pulse controller

Only enabled channels are sent to LTCUThe transmission start when send button is pressed

LTCU – Slow Control software: DAC threshold controller

Each channel threshold can be set

All channels can be set together

LTCU – Slow Control software: Test pulse controller

Only enabled channels are tested when Send button is pushed

Conclusions

• The LTCU prototype board are printed• The electric test of board is in

progress• The LTCU RS232 interface and its all

functionalities are designed and simulated

• The LTCU control software is partially developed

To do

• Design Fired channels recorder • Post-layout simulation of full

FPGA logic• Test board functionality• Test with detector signals