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UC Berkeley EE241 Jan M. Rabaey
Logic Design Styles for HighPerformance or Low Energy
Jan Rabaey
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UC Berkeley EE241 Jan M. Rabaey
Logic Design Styles
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UC Berkeley EE241 Jan M. Rabaey
CMOS Logic Styles (1)
PUN
PDN
ABC
OUT
VDD
GND
ABC
Complementary
robustscales
large and slow
LOGICNETWORK
ABC
OUT
Pass Transistor Logic
simple and fastnot always very efficientversatile
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UC Berkeley EE241 Jan M. Rabaey
CMOS Logic Styles (2)
LOAD
ABC PDN
OUTGND
GND
VDD
Ratioed Logic
small & faststatic power
RPDN <<RLOAD
VDD
PDN
φ
In1In2In3
Out
φ
CL
Dynamic Logic
Small & fastest!Noise issuesScales?
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UC Berkeley EE241 Jan M. Rabaey
Differential Logic
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UC Berkeley EE241 Jan M. Rabaey
Differential Logic
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UC Berkeley EE241 Jan M. Rabaey
DCVSL
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UC Berkeley EE241 Jan M. Rabaey
Karnaugh Map Technique
10 tors
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UC Berkeley EE241 Jan M. Rabaey
0
1
00 01 11 10x1
x2x3
0
0
0 01
1 1 1
Idea: find shared expressions
Build sharescubes first!
LOAD
x1
x3
x1
x3
x2 x2
Q Q
LOAD
x1
x3
x1
x3
x2 x2
Q Q
x1 x2
Add othercubes next.
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UC Berkeley EE241 Jan M. Rabaey
Example: Q = x1x2x3x4 + x1(x2+x3+x4)
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UC Berkeley EE241 Jan M. Rabaey
Using Ordered BDDs
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UC Berkeley EE241 Jan M. Rabaey
DSL Differential Split Logic
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UC Berkeley EE241 Jan M. Rabaey
But … Consumes Static Power
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UC Berkeley EE241 Jan M. Rabaey
Simulation Results for Different Adders
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UC Berkeley EE241 Jan M. Rabaey
Pass Transistor Logic
Advantages:versatile - programmable through interconnectcan be extended to low voltage swingnot gate based - rather multiplexer oriented
Issues:choice of basic cellswitch selectionperformance issuessynthesis
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UC Berkeley EE241 Jan M. Rabaey
Conditional Sum Adder
Rothermel (JSSC 89) tp ~ 1 + log2N
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UC Berkeley EE241 Jan M. Rabaey
Evolutions in Pass-transistor
Double pass-transistor logic
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UC Berkeley EE241 Jan M. Rabaey
Impact of Vdd on Delay
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UC Berkeley EE241 Jan M. Rabaey
NMOS-only Pass Transistor Networks
Similar to DCVSL
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UC Berkeley EE241 Jan M. Rabaey
Level-Restoring Schemes
Cross-coupledPMOS
Sense AmplifyingLatch
FeedbackRestorer
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UC Berkeley EE241 Jan M. Rabaey
Level Restoring Schemes
Vdd = 1.5 V
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UC Berkeley EE241 Jan M. Rabaey
(2) Modify Thresholds
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UC Berkeley EE241 Jan M. Rabaey
Leakage Currents
Simulated for 0.6 micron technology
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UC Berkeley EE241 Jan M. Rabaey
Important : Biasing of output Inverters
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UC Berkeley EE241 Jan M. Rabaey
CPL
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UC Berkeley EE241 Jan M. Rabaey
CMOS versus CPL
Reduced swing at internal nodes: Vtp=Vtn=0.4 V; Vtpass = 0
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UC Berkeley EE241 Jan M. Rabaey
Performance and Power Dissipation
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UC Berkeley EE241 Jan M. Rabaey
Control thresholds dynamically
(Assaderaghi 94): DTMOS
Example: VT = 0.4V at 0 V; 0.17V at 0.5 V
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UC Berkeley EE241 Jan M. Rabaey
Impact of Forward Biasing
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UC Berkeley EE241 Jan M. Rabaey
Impact of forward biasing
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UC Berkeley EE241 Jan M. Rabaey
0.5V CPL (ISSCC 96)
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UC Berkeley EE241 Jan M. Rabaey
Lean Cell Library
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UC Berkeley EE241 Jan M. Rabaey
Various Logic functions of the Lean cell library
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UC Berkeley EE241 Jan M. Rabaey
Sample Circuits
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UC Berkeley EE241 Jan M. Rabaey
Comparison
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UC Berkeley EE241 Jan M. Rabaey
Comparisons per Cell
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UC Berkeley EE241 Jan M. Rabaey
Performance versus supply voltage
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UC Berkeley EE241 Jan M. Rabaey
Swing-Restored Pass-Transistor Logic
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UC Berkeley EE241 Jan M. Rabaey
L-DPTL: A Low Power Logic Family
Latched Differential Pass-transistor Logic
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UC Berkeley EE241 Jan M. Rabaey
Adder circuit in SRPL
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UC Berkeley EE241 Jan M. Rabaey
SRPL Delay Model
Extra Cap.
Not enough drive
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UC Berkeley EE241 Jan M. Rabaey
L-DPTL Versus Static CMOS (SPICE)
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UC Berkeley EE241 Jan M. Rabaey
SAPL
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UC Berkeley EE241 Jan M. Rabaey
SA-F/F Circuits
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UC Berkeley EE241 Jan M. Rabaey
Discrete Cosine Transform(DCT) in SAPL
1.5 ns 20b carry-skip adder(x1.5 speed, 30% area, 50% power reduction)
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UC Berkeley EE241 Jan M. Rabaey
DCT MAC Simulated Waveforms
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UC Berkeley EE241 Jan M. Rabaey
A Comparison[Zimmerman and Fichtner - July 97]
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UC Berkeley EE241 Jan M. Rabaey
CMOS and Pass-Transistor Logic
Beware: no low-threshold devices considered!
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UC Berkeley EE241 Jan M. Rabaey
Full Adders
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UC Berkeley EE241 Jan M. Rabaey
Generic Gates
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UC Berkeley EE241 Jan M. Rabaey
Configurable Logic
input
out
vdd
LUT Tree
LUTConfigMem
input mux
lut inputs
3-input LUT
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UC Berkeley EE241 Jan M. Rabaey
Comparison for 3-input LUT
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UC Berkeley EE241 Jan M. Rabaey
Comparison for 3-input LUT