low charge button and stripline bpm electronics based on microtca

Low charge button and stripline BPM electronics based on MicroTCA

Bastian Lorbeer, DESY, MDI DITANET workshop CERN, 17 January, 2012

Development status of the first MicroTCA based

BPM system

Outline

OUTLINE

• FLASH 1 and FLASH 2• Requirements• Concept and Signals • Acquisition• Evaluation• Summary And Outlook

FLASH 1 AND FLASH 2

Bastian Lorbeer | DITANET Workshop | 17 January 2012 |

Stripline and button installed BPMs in FLASH

dump

FEL beam

bypass line

matchingsection matching

section

undulators

collimatorsection

gunaccelerating

modulesbunch

compressors

button BPM

stripline BPM

cavity or re-entrant cavity BPM

New uTCA based BPM electronics will successively replace old VME based systems in FLASH

5 different button BPM types deliver different amplitude andsignal shape 2 different types of stripline BPM Source: Drawing from Nicoleta Baboi,

DESY, MDI


Performance of installed BPMs at FLASH

button type BPMs Stripline BPMs

For both types of BPMs the resolution is sufficient down to a charge ca. 0.5nC-> below this level new electronics or improvement in the existent are necessary

Source: Measurements by Nicoleta Baboi, DESY, MDI


Button / Stripline BPM for FLASH 2

Extraction top view

Button and stripline BPMs will be equipped with MicroTCAsystems

FLASH 2

Extraction regionwhere many BPMswill be installed

REQUIREMENTS


Relevant parameters for electronics design

bunch charge 0.1-1 nC

bunch spacing ≥222 ns

maximum macro-pulse repetition rate 25 Hz

Beam Pipe Diameter 40.5 mm

Single bunch resolution 50 μm

Averaged RMS resolution over 1000Bunches of identical train 10 μm

Operation range for maximum resolution +/- 3 mm

Operation range delivering reasonable signal +/-10 mm

Source: Dirk Nölle, Boris Keil, Winfried Decking: „The European XFEL Beam Position Monitor System”, Conceptual Design Report Document 3: Requirements & Interface Definition Rev. 1.00, June 15, 2010

t

I

100msDuty cycle ~ 0.8% (XFEL 0.65%)

1-9 mA

t

I 800s (XFEL 650s)Ipeak~ 2.5 kA

Macro-pulseduration

t

I1.0-0.111s (XFEL 200s)

bunch spacing

The FLASH2 specifications are compatible withXFEL requirements

CONCEPT AND SIGNALS


Conceptual system design

Example follows:Warm buttontype XFEL

Delay up to 100ns,Not fix yet ! Combiner type:

broadbandRF cable 3/8“Length < 30m

RTM low chargePeak detectorelectronics

SIS830010channel ADC board

Housing is aMicroTCA crate

U1 U2

+Stripline BPM


Button BPM simulation and measurement

Dirk Lipka et. al.: „Button BPM Development for the European XFEL”, Proceedings of DIPAC2011, Hamburg, Germany, MOPD19, Measurement data from 1. May 2011 at SDUMP

Measured : 11.29 ± 0.72 mm

Simulated : 10.61 mm

monitor constant SDUMP:

feedthroughs spectra of button signal after cable

Diameter: 40.5 mmButton size: 17 mm


Typical button BPM receiver Input Signal / Charge sweep

Measurement at SDUMP on 1 May 2011

Signal of horizontal plane, delay: ~55ns Cable length: ~80m Charge sweep

100mV ~ 100pC

Position ~ 3.75mm

minimum of bunch signal for centered beamis displayed here !

55ns

Position information U1, U2


Typical Stripline BPM receiver input signal

Stripline parametersbeamline dia = 34 mm stripline length = 200.5mmcable type / length = 3/8‘‘ Acome / ~20 mMonitor constant = 20mm

1.35ns

Filtered with a 8 orderlow pass filter at 500MHzBetter use a flat time response filter here !

Signal here shown for one stripline

ACQUISITION


VME vs. MicroTCA

VMENumber of new developments is decreasing,sales are still constant

Bus technology has speed limitations

Wide busses create a lot of noise in analog channels

But, a lot of I/O modules are available

No standard management on crate level

No management on module level

So far no extension bus survived

One damaged bus line stops a whole crate

Address and interrupt misconfigurations are hard to find

MicroTCAScaleable modern architecture

From 5 slot µTCA … full mesh ATCA

Gbit serial communication links

High speed and no single point of failure

Standard PCIe, Ethernet (, SRIO) communication

Redundant system option

99.999% availability is possible

Well defined management

A must for large systems and for high availability

Hot-swap

Safe against hardware damage and software crashes

Courtesy: Kay Rehlich, MCS, DESY


MicroTCA systems currently used at DESY-MDI

System specs are based on the PICMG standard (MTCA 4.0 for Physics)

Zone 3 connector

Laboratory crate system

Front Back

19‘‘ production crate system6 slots 12 slots

CPU HD &VGA

DigitizerAMC

timing analogfrontendRTM


LCBPM RTM Rear Transition Module

RTM LCBPM made by MDI1 / FEB

Zone 3 connector:

Power supply

Input 1

Input 2

Test pulse in

MPS

TTL Gate

External clkTest pulse out


RTM one channel

one channel for one plane

active temperature Stabilization of diode31.25dB range

0.25 dB steps

Gain ~ 36dB

To ADCbuffersOn digitizerboardvia Zone 3connector


Typical Output signals of RTM

Input signal to front end100ns delay for second pulsegenerated with AWG

resembles zero offset signal

Output signal after peak detector test port

750mV for first pulse

From here: calculation of offset position !First pulse: information for U1Second pulse: information for U2

62ns

Signals from one plane combinedafter a delay line of 14 m


ADC input circuitry and clocking scheme

Clock dividers:Phase offsetProgrammable delay

ADC buffer

chip w/ 2 ADCs

Traces to ADC board are length compensated on SIS 8300-V2

125MSPS

10 channels

Clock distribution for various clocking schemes

Optional Clocking from: external clocks fed from RTM, or backplane

Block diagram: SIS8300 μTCA FOR PHYSICS Digitizer User Manual, SIS8300-M-1102-2-V211.doc as of 05.08.11

EVALUATION


ADC / buffer noise of DC coupled channels

Typical timetrace of single ADC channel:

measurement with ~100Ω input termination

counts

peak-peak!

all channels on the board:

These are the DC coupled channels !!

in mV

Plotted forall 10 channels

All channels have a noise band less than1.2mV – approximately 11/12 Bits


Noise of RTM and AMC in crate with 50 Ohm input load

ADC channels of one plane (e.g. horizontal plane)

all ADC channels of digitizer board

All channels have a noise band less than1.5mV –still ca.10 Bits


Current laboratory setup

Arbitrary Waveform Generator:10Bit Resolution12GS/s (-3dB @ 3.5GHz)

Input signal

Trigger

Dicharge pulse

bunch signals

raw data outRead out witha MATLAB tool fromserver

Free running clockat 125MHzat the moment

Access serversProvided by MCS, DESY


A train of output pulses

Input signal - combined signal of two buttons in one plane

Example:Signal levels correspond to a 40.5 mm button BPM (17 mm button) @ 30 pCclose to the center

Performance data not yet calculated from pulse train output!

pos 1 pos 2


Summary & Outlook

OUTLOOK• More detailed analysis of available data

• More lab tests (position sweep for different charges)

• Evaluation in machine of the system to come Feb/

Mar 2012

• Improvements in the power supply on RTM and signal

conditioning

• Development of correction tables for individual

charges

• Possible switching to 250MSPS ADC with 14Bits on

the acquisition card

• Series production of redesign at the end of summer

2012

• Development of FPGA firmware to process data on

acquisition card

• Correction algorithm for large offsets of the beam

SUMMARY• Measures each bunch in train with repetition rate of

222ns

• Dynamic range from 0.1 to 1nC

• Calibration with 10 Bit resolution input signals in the

lab

• Online testing possible between macropulses

• Free running mode and synchronous mode

• Timing and clocks delivered by the the machine in the

synchronous mode

THANKS

Jorgen Lund-Nielsen, Rudolf Neumann, Frank Schmidt-Föhre, Nicoleta Baboi, Dirk Nölle, Petr Smirnov, Peter Göttlicher, Bart Faatz, and many others

BACKUP SLIDES


Position sweep with AWGLinearity of Front End (RTM)


Signal in the receiver and discharge path

After first LNA

After second LNA

After discharger andbuffer

After discharger testportsignal


Power supply noise

8V power supply ext DC: Vrms = 28uVrms Vpkpk = 220uV

Measurement limit: Vrms = 13uVrmsVpkpk = 100uVpkpk

Measured in a bandwidth B= 1GHz !!!

Measured outside the crate with laboratory DC supply


Low noise amplifier output noise

Eval board LNA: Vrms = 242uVrms Vpkpk = 1.7mV

Measurement limit: Vrms = 13uVrmsVpkpk = 100uVpkpk

Measured in a bandwidth B= 1GHz !!!

Measured outside the crate with external DC supply


LNA evalboard vs. LNA PCB

Evalboard *100 and external supply LNA on PCB *100 and crate supply

1.8us repetitive spikes from crate supply555kHzNaked crate brings 3.6us repetitive ripple277kHzcrateBehind DCDC


Bandwidth of frontend „RF part“

-3dB corner at ~ 330MHzFlat time response !


FEMTO preamp risetime / bandwidth

Measured with AWG square 1000 Measured with Jorgens pulser


Toroids resolution


Synchronisation with Machine Timing

Courtesy: Attila Hidvégi, Stockholm University Physics Departement, Rev 0.1.2

Purpose• Distribute clocks and trigger information to the whole accelerator system and experiments.• Deliver the 1.3 GHz main RF-frequency and other derived frequencies.• Synchronize the clock-phases and keep them drift free, with a total jitter: <5 ps (RMS).• Deliver clocks and triggers through the backplane and through the front panel.• Cost efficiency

Features• Both transmitter and receiver functionality• Delivers clocks and triggers through front panel

and backplane.• 8 M-LVDS signals to the backplane• Main frequency is 1.3 GHz• Derived frequencies are divided from the main

frequency, and synchronized in phase• Clock outputs are adjustable in stepsof 100 ps• Single SFP for optical communication• ~25 W power consumption


History of BPMs at DESY

SEDAC Module anno 1985, Rudolf Neumann, Jörg Neugebauer uva.

Tektronix Scanconverter anno 1976, people involved: Franz Peters, Rudolf Neumann

XFEL BPM prototype in 2007, Thomas Traber,project assigned to PSI

Wendt Elektronik, VME based since 1995 and earlierin operation at FLASH w/ remote access since 2005,electronics with many modifications and improvementsby Jorgen Lund-Nielsen and Wolfgang Riesch

low charge button and stripline bpm electronics based on microtca

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