low power explicit type pulse triggered flipflop using tspc latch based on signal feedthrough scheme

7/24/2019 LOW POWER EXPLICIT TYPE PULSE TRIGGERED FLIPFLOP USING TSPC LATCH BASED ON SIGNAL FEEDTHROUGH SC

1/6

International Journal of AdvaVol. 2, Issue 10, October 2015

LOW POWTRIGGERE

LATCH BASED

Litty Vargh

Pg St

Abstract: In this brief, a low-power flip-flopsingle phase clock latch based on a signal fedischarging path problem existing in convespeed and power performance. Based onconventional P-FF design explicit pulse dat

performance edges on power and power- dela

Keywords: Flip flop, Pulse triggered, True sin

1. INTRODUCTION

Flip-flops are the basic memorystoring information. Hence, they are th

building blocks for all sequential circuits. Acan store only one bit of information. Innowadays often employ many FF-rich moregister file and shift register. It is also esti

power consumption of the clock system, whclock distribution networks and storage elemas 50% of the total system power. FFs thusignificant portion of the chip area and poweto the overall system design [1], [2]. Flip-more often since they can all be synchronionly at the active edge of the enable signasignal for the flip-flops is usually the gloclocksignal.

Availabl

ced Research Trends in Engineering and Technolog

All Rights Reserved 2015 IJARTET

R EXPLICIT TYPE FLIPFLOP USINON SIGNAL FEEDT

SCHEME ese1, S.Udhayakumar 2, Swaminathan Veerapandian 3

udent 1, Assistant Professor 2 ,Employee 3

(FF) design using an explicit type pulse-triggered stred-through scheme is presented. The proposed design stional explicit type pulse-triggered FF (P- FF) designs.simulation results using Tanner EDA, the proposea-close-to-output (ep-DCO) by 8.2% in data-to-Q del-product metrics are 22.7% and 29.7% respectively.

gle phase clock, signal feed through

elements forfundamental

ingle flip-flopigital designs

dules such asated that the

ich consists ofnts, is as high

s contribute ar consumptionflops are usedzed to changel. This enableal controlling

Fig (1)In Pulse triggered flip flop

rising (or falling) edge of the clockgenerator circuit (Fig 1). This pulselatch. Sampling of latch is done in ththe pulse generator. Race conditions athe opening time (i.e , the transpareshort. The combination of the glitchlatch results in a positive edge-triggerflip flops which has time borrowingup time is pulse triggered flip flops. I

power P-FF design based on a siObserving the delay discrepancy in ladesign shortens the longer delay bdirectly to an internal node of the latc

ISSN 2394-3777 (Print)ISSN 2394-3785 (Online)

online at www.ijartet.com

(IJARTET)

13

ULSETSPC

HROUGH

cture and a modified trueccessfully solves the longIt helps to achieve better

design outperforms they. In the mean time, the

, a short pulse around theis created through a pulse

acts as the clock input to ais short window created byre thus avoided by keepingt period) of the latch very

generation circuitry and theed register. The only type ofapability with negative set-

n this brief, proposes a low- gnal feed-through scheme.

tching data 1 and 0, thefeeding the input signal

design to speed up the data


2/6


transition. This mechanism is implemented bsimple pass transistor for extra signal

combined with the explicit pulse generatioforms a new P- FF design with enhanced spedelay- product (PDP) performances.

II. EXISTING METHOD A.Conventional explicit typePFF

(a)

Fig (a) shows the schematic of the Explicit- PClose-to-Output flip-flop (ep-DCO) which isone of the fastest flip-flops due to itscharacteristics. The pulse generator of theData-Close-to-Output flip-flop uses the dinverters to generate the pulse at the doublclock. In the ep- DCO, there are two stages, tdynamic and the second stage is static. Tdrives three transistors-MP1,MN2 and MN3.is connected to MN1 and the circuit capthrough MP2. When the flip-flop is transpadata propagates to the output, after the tranMN2 and MN3 will turn off because of thethe pulse at the same time, point X chanvoltage because that MP1 is on at this time.after the transparent period. Hence, any chancannot be passed to the output. This givesswitching power dissipation. To overcomemany remedial measures such as conditconditional precharge, conditional diconditional pulse enhancement scheme have

Availabl



introducing ariving. When

n circuitry, ited and power-

lse Data- considered as

semi-dynamicExplicit-Pulse

elay of threee edge of thee first stage ise clock pulseThe input dataures the data

rent, the input parent period,ow voltage ofe to the high

So MN4 is offge at the inputrise to largethis problem,

ional capture,charge, and

been proposed

[3][7].

(b)

Fig. (b) shows a contechnique[5]. An extra nMOS transioutput signal Q_fdbk is employed sothe input data remains 1. In additiinternal node X is simplified and co

pull-up pMOS transistor only. But tdelay caused by a discharging pathtransistors, i.e., MN1 MN3. To ovspeed performance, a powerful pullwhich causes extra layout area and po

(c)

Fig(c) shows the modifie(MHLFF) [8] . It also uses a staticnode X is removed. A weak pull-up

by the output signal Q maintains theequals 0. Despite its circuit simpliencounters two drawbacks. First, sdischarged, a prolonged 0 to 1 deladeteriorates further, because a lev(deviated by one VT) is applied toMN3. Second, node X becomes floativalue may drift causing extra dc powe



(IJARTET)

14

itional discharged (CD)tor MN3 controlled by thethat no discharge occurs ifn, the keeper logic for thensists of an inverter plus ais design face a worst caseconsisting of three stackedrcome this delay for better-down circuitry is needed,

er consumption.

hybrid latch flip flopatch. The keeper logic attransistor MP1 controlledlevel of node X when Q

city, the MHLFF designince node X is not prey is expected. The delayl- degraded clock pulsethe discharging transistorng in certain cases and itsr [7].


3/6


(d)Fig: (d) Proposed P-FF design

Fig.(d) shows a similar P-FF desiusing a static conditional discharge techdiffers from the CDFF design in usingstructure. Node X is thus exempted from pcharges. It exhibits a longer data-to-Q (D-to-the CDFF design. Both designs face a wor caused by a discharging path consisting oftransistors, i.e., MN1MN3. To overcome t

better speed performance, a powerful pull-dis needed, which causes extra layout areaconsumption.

III .PROPOSED TECHNIQUE

The proposed design introduces a

Availabl



gn (SCDFF)ique(15) . It

static latcheriodical pre) delay than

t case delayhree stackedis delay forwn circuitryand power

signal feed-

through technique to improve the ddifferences that lead to a unique TSP

makes the proposed design distinFirst, a weak pull-up pMOS transistoto the ground is used in the first staggives rise to a pseudo-nMOS logic stkeeper circuit for the internal node Xto the circuit simplicity, this approcapacitance of node X [9], [10]. Secocontrolled by the pulse clock is includrive node Q of the latch directlyscheme). Along with the pull-up trastage inverter of the TSPC latch, thiauxiliary signal driving from the inpnode level can thus be quickly pulltransition delay. Third, the pull-dostage inverter is completely remoemployed pass transistor MNx provThe role played by MNx is t hus tdriving to node Q during 0 to 1 data tnode Q during 1 to 0 data transiti

The principles of FF operatiare explained as follows. When a cltransition occurs, i.e., the input datalevel, on current passes through thekeeps the input stage of the FF frosame time, the input data and the outpcomplementary signal levels and theoff. Therefore, no signal switching oOn the other hand, if a 0 to 1 datadischarged to turn on transistor MPhigh. With the signal feed througobtained from the input source via tthe delay can be greatly shortened.

IV.PERFORMANCE ANA

The pulse width design is cdata capture as well as the powertransistors of the pulse generator logiof 120 ps in pulse width. Since thdirect output driving from the inputthe power consumption of the data iincluded. The output of the FF is loaAn extra loading capacitance of 3 fF i



(IJARTET)

15

elay. Mainly three majorC latch structure and it

ct from the previous one.MP1 with gate connectede of the TSPC latch. Thisyle design, and the chargecan be saved. In addition

ch also reduces the loadnd, a pass transistor MNxed so that input data can(the signal feed- throughsistor MP2 at the seconds extra passage facilitatesut source to node Q. Thed up to shorten the datan network of the secondved. Instead, the newlyides a discharging path.ofold, i.e., providing extraansitions, and dischargingns.

ons of the proposed designck pulse arrives, if no data

and node Q are at the sameass transistor MNx, which

any driving effort. At theut feedback Q_fdbk assumeull-down path of node X is

ccurs in any internal nodes.transition occurs, node X is, which then pulls node Q

scheme, a boost can bee pass transistor MNx and

LYSIS

rucial to the correctness ofconsumption [11]-[14], the

are sized for a design spece proposed design requiresource, for fair comparisonsnput buffer (an inverter) isded with a 20-fF capacitor.s also placed at the output of


4/6


the clock buffer [7].

Table I : Feature comparison of various FF designs

A .Power Consumption Performance of FF D

Table I summarizes the circuit featsimulation results. For circuit features,

proposed design does not use the leasttransistors, it has the smallest layout area. Tattributed to the signal feed-through schlargely reduces the transistor sizes on the

path. In terms of power behavior, the propothe most efficient in five out of the six testsavings vary in different combinations of tesFF design. For example, if a 25% data s

pattern is used, the proposed design iseconomical.

Availabl



signs

ures and thelthough thenumber ofis is mainly

eme, whichdischarging

ed design isatterns. The

t pattern anditching testore power-

Table II: Leakage power comparis

Referring to Table II, the leof the proposed design is very clodesigns. The MHLFF design is the odc power consumption because ofnode. Its dc (leakage) power consumothers and is thus excluded from the c

B. Timing Parameters of FF Designs

After the analysis of powexamine the timing parameters of thethe set-up time is measured as the optthe clock edge) of applying input dat

power and D-to-Q delay. In other wothe optimization of PDPDQ instead o

The PDP values of the prothan other designs in almost all setup(d). For most P-FF designs, the mini

negative setup times. This is becintroduced by the pulse generator sapplied after the triggering edge of the

(d) PDPDQ versus setup time s

(e) C-to-Q delay versus hold



(IJARTET)

16

n in standb mode

akage power consumptionse to that of other P-FFe that suffers from a largea non full-swing internal ption is much higher thanomparison [7].

r performances, we thense FF designs. In this brief,imal timing (with respect toto minimize the product of

rds, its choice is based onthe D-to-Q delay alone.

posed design are smallertime settings shown in Fig

um PDP values occur at

ause of the extra delay o that input data can beclock.

ttings

time settings .


5/6


The measured setup and hold ti proposed design are 85.7 and 120.1 ps, resp

but one P-FF designs under comparison extiming parameters. The exception is the MHwhich has a slightly positive setup time and atime than its counterparts because of a sigenerator. A longer hold time mainly affect tthe driving logic. If P-FFs are adopted idesign, the hold time constraint can be ea

because of a prolonged clock-to-Q delay propdesigns. Introducing an input delay buffer ismeasure to alleviate the hold time requiremen

Fig (f) shows the PDP DQ perfordifferent data switching activities. The propoutperforms others in all but the case of Sswitching activity (all zero). The PDP DQ valunder the test pattern with 25% switching actilisted in Table I.

(f)

V.CONCLUSION

In this brief, presented a novel P-Femploying a modified TSPC latch structure ia mixed design style consisting of a pass tra

pseudo-nMOS logic. The key idea was to profeed through from input source to the internalatch, which would facilitate extra driving totransition time and enhance both power

performance. The design was intelligentlyemploying a simple pass transistor.

Availabl



mes of theectively. All

hibit similarLFF design,shorter holdmpler pulsehe design of

the entireily satisfiederty in P-FFlso a simple

t.

ance underosed designDFF at 0%es obtained

vity are also

F design byncorporatingsistor and a

vide a signalnode of theshorten theand speed

achieved by

ACKNOWLEDGEMEN

The authors acknowledgestudents, faculty of Sri Eshwar C,Kinathukadavu for helping in the desiauthors also thank the anonymous recomments that helped to improve this p

REFERENCE

1) H. Kawaguchi and T. Sakurai, A reduceRCSFF) for 63% power reduction, IEEE5, pp. 807811, May1998.

2) K. Chen, A 77% energy saving 22-transistwith adoptive-coupling configuration in 40Solid-State Circuits Conf. , Nov. 2011, pp. 33

3) B. Kong, S. Kim, and Y. Jun, Conditio power reduction, IEEE J. Solid-State CircAug.2001.

4) N. Nedovic, M. Aleksic, and V. G. Otechniques for power-efficient dual-edge cl

Power Electron. Design , Aug. 2002, pp. 56

5) P. Zhao, T. Darwish, and M. Bayoumi, conditional discharge flip-flop, IEEE TranSyst., vol. 12, no. 5, pp. 477484, May 2004.

6) M.-W. Phyu, W.-L. Goh, and K.-S.edgetriggered flip-flop using an output-con Proc. IEEE Int. Symp. Circuits Syst. , May 20

7) Y.-T. Hwang, J.-F. Lin, and M.-H. Sheu, design with conditional pulse enhancementScale Integr. (VLSI) Syst. , vol. 20, no. 2, pp.

8) S. H. Rasouli, A. Khademzadeh, A. Afz power single- and double-edge-triggered flip IEE Proc. Circuits Devices Syst. , vol. 152, n

9) H. Mahmoodi, V. Tirumalashetty, M. Cooclocking scheme using energy recovery an

Large Scale Integr. (VLSI) Syst. , vol. 17, no.

10) P. Zhao, J. McNeely, S. Venigalla, G. P. KuDowney, Clocked-pseudo-NMOS flip-flosupply systems, IEEE Trans. Very Largeno. 9, pp. 11961202, Sep. 2009.

11) M. Alioto, E. Consoli, and G. Palumb



(IJARTET)

17

the contributions of thellege of Engineering n and for tool support. The

iewers for their thoughtfulaper .

d clock- swing flip- flop ( J. Solid-State Circuits , vol. 33, no.

r single phase clocking Dflip- flopnm CMOS, in Proc. IEEE Int.

8339.

nal-capture flip-flop for statisticalits , vol. 36, no. 8, pp. 12631271,

lobdzija, Conditional prechargeocking, in Proc. Int. Symp. Low-59.

High-performance and low power s. Very Large Scale Integr. (VLSI)

eo, A low-power static dualrolled discharge configuration, in05, pp. 24292432.

ow power pulse triggered flip-flopscheme, IEEE Trans. Very Large361366, Feb. 2012.

li-Kusha, and M. Nourani, Low-flops for high speed applications,. 2, pp. 118122, Apr.2005.

e, and K. Roy, Ultra low powerd clock gating, IEEE Trans. Very1, pp. 3344, Jan.2009.

mar, M. Bayoumi, N. Wang, and L. ps for level conversion in dualcale Integr. (VLSI) Syst. , vol. 17,

o, General strategies to design


6/6


nanometer flip-flops in the energy-delay space, IESyst., vol. 57, no. 7, pp. 15831596, Jul. 2010.

12) M. Alioto, E. Consoli, and G. Palumbo, Flip-flop eersus Clock Slope and impact on the clock netwo

Trans. Circuits Syst. , vol. 57, no. 6, pp. 12731286, Ju

13) M. Alioto, E. Consoli, and G. Palumbo, Analysisthe energy-delay-area domain of nanometer CMOSmethodology and design strategies, IEEE Trans.

Integr. (VLSI) Syst. , vol. 19, no. 5, pp. 725736, May

14) M. Alioto, E. Consoli and G. Palumbo, Analysisthe energy-delay-area domain of nanometer CMOSresults and figures of merit, IEEE Trans. Very L(VLSI) Syst. , vol. 19, no. 5, pp. 737750, May 2011.

15) M.-W. Phyu, W.-L. Goh, and K.-S. Yeo, static dual edgetriggered flip-flop using an output-cocon- figuration, in Proc. IEEE Int. Symp. Cir2005, pp. 24292432

BIOGRAPHY

MISS.LITTY VARMasters Degree in VLSri Eshwar College oKinathukadavu,Received Bachelors Dfrom MBC College ofTechnology,Kerala. Aare Low power VLSElectronics.

Mr. S. UDHAYAssistant professorCollege of Engineerito AnnaKinathukadavu, Coispecialization area isCommunicationMicrowave Engineeri

Availabl



E Trans. Circuits

ergy/performancerk design, IEEEn. 2010.

nd comparison inlip-flops: Part I

Very Large Scale011.

nd comparison inlip-flops: Part II -

rge Scale Integr.

low-powerntrolled dischargeuits Syst. , May

HESE doing I Design from

f Engineering,Coimbatore.

egree in ECEEngineering &ea of interestsI and Digital

KUMAR isat Sri Eshwarng, (Affiliated

University),mbatore. HisVLSI Design,ystem andng.

VEERAPA Network(TelecommTataCommuinterest is N



(IJARTET)

18

Mr.SWAMINATHAN

DIAN is working asExecutivenications) innications Ltd. His area oftwork Systems.

low power explicit type pulse triggered flipflop using tspc latch based on signal feedthrough scheme

Documents