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BiTS 2016

March 6-9, 2016Burn-in & Test Strategies Workshop www.bitsworkshop.org

Proceedings Archive

Archive- Session 5

March 6 - 9, 2016

Hilton Phoenix / Mesa Hotel

Mesa, Arizona

© 2016 BiTS Workshop – Image: Stiop / Dollarphotoclub

BiTS 2016


Proceedings Archive

Presentation / Copyright Notice

The presentations in this publication comprise the pre-workshop Proceedings of the 2016 BiTS Workshop. They reflect the authors’ opinions and are reproduced here as they are planned to be presented at the 2016 BiTS Workshop. Updates from this version of the papers may occur in the version that is actually presented at the BiTSWorkshop. The inclusion of the papers in this publication does not constitute an endorsement by the BiTS Workshop or the sponsors.

There is NO copyright protection claimed by this publication. However, each presentation is the work of the authors and their respective companies: as such, it is strongly encouraged that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies.

The BiTS logo and ‘Burn-in & Test Strategies Workshop’ are trademarks of BiTS Workshop.

2

BiTS 2016


Proceedings ArchiveBiTS Workshop 2016 Schedule

Session

Session Chair

Performance DayTuesday March 8 - 10:30 am

West Meets East & Cutting Edge

"LPDDR4 Signal & Power Performance Optimization By Hardware""通过测试硬件的优化来提升LPDDR4信号和电源的性能"

Yuanjun Shi - Twinsolution TechnologyXiao Yao - HiSilicon Technologies Co

"Reliability Characterization of Unpackaged (bare) die for Silicon Photonics module"

Sujata Paul, Andrew Fong, Samir Alqadhy, Huy Nguyen, Zoe Conroy - CiscoTom Elliot, Jag Jassal - Evans Analytical Group

"Advanced High Energy CO2 Spray Cleaning Technology for Burn-In Test Substrate Cleaning Applications"

Nelson Sorbo - Cool Clean Technologies

"Texas Instruments Final Test Contactor Qualification Process and Low Profile Contactor Solution"

James Tong, Hisashi Ata - Texas Instruments

5Ashok Kabadi

Approve Final/BiTS2016s5p1Shi.pptx

Approve Final/BiTS2016s5p1Shi.pptx

Approve Final/BiTS2016s5p1Paul.pptx

Approve Final/BiTS2016s5p2Sorbo.pptx

Approve Final/BiTS2016s5p3Tong.pptx

Cutting Edge - Advanced Technology / New ApproachesBiTS 2016Session 5 Presentation 2


Reliability Characterization of

Unpackaged (bare) die for

Silicon Photonics module

Sujata Paul, Andrew Fong, Samir Alqadhy,

Huy Nguyen, Zoe Conroy - Cisco

Jag Jassal, Tom Elliot

EAG (Evans Analytical Group)

2016 BiTS Workshop

March 6 - 9, 2016Conference Ready

mm/dd/2014



Contents

• Introduction

• Cisco CPAK 100G Module

• Packaged vs Bare die qualification

• Qualification Hardware

• Stress profile

• Conclusion

Reliability Characterization of Unpackaged (bare) die for Silicon Photonics module 2



Introduction• BI (burn In) and qualification (HTOL, ELFR, ESD, LU etc) traditionally

takes place on packaged parts.

• The use of bare die going directly onto an application module becoming

more common. Die will never be packaged.

• Hence traditional methods of qual are no longer an option.

• An easy, cost effective solution for qualifying >1000 bare ( to meet

JEDEC specs) die needs to be assessed to mitigate field fail risk.

• We have developed a comparative low cost and portable burn-in and test

solution which is useful for low volumes or quick solutions

• This form factor is portable to

– BiB (Burn-in-Board): HTOL and ELFR stress

– ATE Load board: Characterization testing

– ESD/LU tests

• This solution allows complex tests and burn-in functions to be carried out

with good correlation to wafer and Die Level Handler sort.




Cisco CPAK for 100Gbps Solution

4

• Bare die dominates in the module

• Complex supply chain

• Challenge: Ensure Quality and Reliability of the components

Inside the module

Reliability Characterization of Unpackaged (bare) die for Silicon Photonics module



Packaged vs Bare die qualification

5

Wafer Sort

Wafer Dicing

Packaging and Assembly

Pre-BI Package tests

BI testing

Post-BI Package test

Fully functional and reliable devices ready to be shipped

Product

qualification

(HTOL, ESD, LU)

Bare Die Qualification Options

1. Wafer Level BI and Test

2. Packaged Die

3. Die Carrier

4. Daughter Card (DC)

Bare Di assembly

(Fully qualified and

reliable die get

assembled into

application module

Bare Die Test (Wafer

Sort or Die Level

Handler)

Source of Bare die

(Full production

wafers or MPW)

NPI ProductionProduction




Bare die qual options


• Wafer Level Burn In and TestNot a workable Solution.

Cost high, and design of wafer not suitable for BI power supplies

• Packaged DieCost becomes high for packages and sockets for 1500 die

• Die CarrierCost is high and die pad pitch is too small at 60um.

• Daughter Card (DC)-Most cost effective.



Bare Die Reliability Test Cisco Semiconductor L1 qual Bare die qual

HTOL Grade-A/-S

• 79u x 3 lots = 237 units with 0 fails (or fail)

• Duration = 1000 hours

Plan for grade A:

79 die MPW lot1, 79 die MPW

lot2

79 die prod lot

EFR Grade-A/-S

• 3500 units (3 lots) @ 48 hours w/ 0 fails

Grade-A (Low Volume)

• 1167 units (1 lot) @ 48 hours w/ 0 fails

Grade A low volume.

TC • JESD-22-A-104-D (25 u x 3 lots = 75 units) Done in Module

HTS JESD-22-A-103-C

THB (Biased)

• JESD22-A-101B Done in Module

HBM ESD

• JS-001• 3 units w/ 0 fail

3 units done in PGA for Die1

3 units done in DC for Die2

LU 3 units done in PGA for Die1

3 units done in DC for Die2

CDM ESD

• JESD22-C101 (3 units w/ 0 fail) Done in Module

7Reliability Characterization of Unpackaged (bare) die for Silicon Photonics module



Hardware required for qual stress and test

• Bare die assembly on a custom daughter card or package

• BiB design and assembly

• ATE board design with right pin configuration

8

Two Different Bare die were used

Die1:40/45nm ASIC Die2: CoC

die size is 5900 µm x 2380 µm. die size is 2850 um x 1700 um.




Two different packaging was used

Small PCB board

(Daughter Card)

PGA

Bare Die Assembly

9

The die is wire bonded

to the package

• Die1:Assembled on Daughter Card and PGA

package. We used PGA for ESD and LU evaluation

for Die1 at early stage. PGA is not cost effective for

HTOL and EFR (1500 parts) evaluation.

• Die2: Assembled on Daughter Card only.

• PGA parts correlate to T0H Test data on Daughter

Card parts. Both DC and PGA parts T0H data

correlate to Wafer Sort and Die Level Handler Test

data at room temp.




Burn In Boards and ATE board

10

BiB Mother board Daughter Card on BiB

Mother boards with connector (DIMM socket)

used for the Bare Die Assembled on DC. This

BiB supports 16 DC and can connect 120 pins

from the die to the DC with 4 Power supply.ATE 93K Boards used




ESD and LU HW

11

Die2: CoC

Verifier Board for MK2

• DC are easily portable to ESD and LU tools with a fixture board.

• DC approach provides Pre and Post ESD/LU full functional

tests on the bare die.

ESD/LU MK4 docking board

for PGA parts for Die1




Burn In Pattern for HTOL/ELFR Stress

12

• 5 parts run 30mins with pattern1. 5 parts run with pattern2 for 30mins.

• The DUT reaches its operational temperature after register initialization has

finished.

• The silicon temperature can be measured on ATIO0, ATIO1 ports:

Tj=(ATIO0-ATIO1)/0.3968 - 278.25 [C]. ATIO0 and ATIO1 are Analog Test IO.

• 10 parts were run at 25C, 100C, 125C, 140C and 150C Ambient temp.

• The die temp (Tj) is 7-10C higher than the ambient temp.

• HTOL stress temp=140C

Measuring accurately the die temp with Temp Sense Diode




Conclusion

• We have implemented a solution for Bare die HTOL, ELFR,

ESD, LU Stress.

• One of the cheapest (making it possible to run more than 1000

parts for ELFR) solution for bare die qual.

• Portable to and from BiB to ATE tester, ESD, LU tool

• Provides full functional test pre and post BI and ESD/LU

• DC approach also provides easy access for any PFA for post

qualification failures.

• This qualification and test screening methodology provides

higher quality and rapid TAT for first Customer shipping.

13Reliability Characterization of Unpackaged (bare) die for Silicon Photonics module

march 6 - 9, 2016 hilton phoenix / mesa hotel mesa ... phoenix / mesa hotel mesa, arizona ... die...

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