MEASUREMENT AND EVALUATION OF POWER ANALYSIS

ATTACKS ON ASYNCHRONOUS S-BOX

ABSTRACT:

This paper demonstrates the hardware implementation of a recently

proposed low-power asynchronous Advanced Encryption Standard substitution box (S-Box)

design that is capable of being resistant to side channel attack (SCA). A specified SCA standard

evaluation field-programmable gate array (FPGA) board is used to implement both synchronous

and asynchronous S-Box designs. This asynchronous S-Box is based on self-time logic referred

to as null convention logic (NCL), which supports a few beneficial properties for resisting SCAs:

clock free, dual-rail encoding, and monotonic transitions. These beneficial properties make it

difficult for an attacker to decipher secret keys embedded within the cryptographic circuit of the

FPGA board. Comparisons on the resistance to SCAs of both the original and proposed S-Box

design are presented. The power measurement results showed that the NCL S-Box.

EXISTING SYSTEM:

To provide the error detection, recognizing that previously proposed schemes are not well

suited to compact implementations, it is proposed to adopt a hybrid approach consisting of parity

codes in combination with partial circuit redundancy. For compact ASIC implementations,

taking such an approach gives a better ability to detect faults than simple parity codes, with less

area cost than proposed schemes which use full hardware redundancy

EXISTING SYSTEM ALGORITHM:

DES

Triple DES

EXISTING SYSTEM DRAWBACKS:

Power consumption is high

Area high

Easily hack the architecture

PROPOSED SYSTEM BLOCK DIAGRAM:

PROPOSED SYSTEM TECHNIQUE (ALGORITHM):

AES Algorithm

Null Convention Logic (NCL)

PROPOSED SYSTEM ADVANTAGES:

These beneficial properties make it difficult for an attacker to decipher secret keys

embedded within the cryptographic circuit of the FPGA board.

Lower total power consumption during regular operation.

SOFTWARE REQUIREMENT:

ModelSim6.4c

Xilinx 9.1/13.2

HARDWARE REQUIREMENT:

FPGA Spartan 3/ Spartan 3AN

REAL TIME APPLICATION:

The growth of innovation for these devices can be seen in today’s mobile phones,

portable devices and computer/network security in industrial control system.

FUTURE ENHANCEMENT:

We will be implementing AES Encryption using Null Convention Logic.

ALTERNATE TITLES:

Title 1: Efficient Asynchronous S-box Implementation on FPGA

Title 2: Asynchronous S-box Implementation for Advance Encryption Standard Algorithm

Title 3: Realization of Asynchronous S-box Implementation using Verilog HDL

PROJECT FLOW:

First Phase:

60% of Base Paper (3 Modules only Simulation)

Second Phase:

Remaining 40% of Base Paper with Future Enhancement (Modification)