mixed-signal systems-on-chip: architectures and design toolsmixed-signal systems-on-chip:...
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Mixed-Signal Systems-on-Chip: Architectures and Design Tools
Alex Doboli, PhDAssociate Professor
Department of Electrical and Computer EngineeringState University of New York, Stony Brook, NY 11794
Email: [email protected]
The “Wish List”
• A new development paradigm that:– Much more efficient design methodologies
– Higher Level Of Abstraction For Development
– Exploit design reusability & retargeting– Frees Designers From Low Level Implementation Details– Produces Interoperable And Portable Designs– Supports Reconfigurability– Provides Extensive, and Extensible, Third-Party Device
Libraries– Is Self-Documenting– Is scalable and extensible
Research, Entrepreneurial & Educational Challenges
• High-level AMS synthesis?
Stephan Ohr, “Synthesis proves to be Holy Grail for analog EDA”, EE Times, 06/08/1999
Research, Entrepreneurial & Educational Challenges
– AMS design is “art” and less “science” • Theory? Methodology? How to invent application-
specific topologies & circuits?
– Architectures?
– Few CAD tools (mostly simulators: SPICE etc.)• Transistor is not a switch! (modeling)• Design usually at a low level (transistors, layout)
– Who will develop the architectures & tools?
– Who designs AMS systems? EE/CE/CS/all?
Presentation outline
• PSoC: embedded mixed-signal architecture
• Related research at Stony Brook
• Systematic methodology for ∆Σ ADC design
• Automated circuit modeling
• Education & training
• Conclusions
Embedded Mixed-Signal Architectures
• Cypress’ programmable PSoC mixed-signal SoC
• Main features:– Hardware programmability
• Programmable analog blocks• Programmable digital blocks• Programmable interconnect • Programmable I/Os• Programmable clocks• Selectable power supply
– Integration as an SoC
PSoC Mixed-Signal Architecture
Why PSoC-like architectures ?
• PSOC supports/helps:
– Design reusability & retargeting (library)
– Predictable performance (library of models)– Frees designers from low level implementation
(pre-characterized cells)– Supports Reconfigurability– Supports extensive, and extensible, third-party
device libraries– Is scalable and extensible (programmable
transceivers, PLLs, software radio)
PSoC Mixed-Signal Architecture
PSoC Mixed-Signal Architecture
PSoC Mixed-Signal Architecture
• Analog blocks are programmable– Programmable functionality (control registers)– Programmable inputs & outputs
• Analog blocks of two types– Continuous time blocks– Switched capacitor blocks (type C and type D)
• Connected to programmable I/O ports
• Programmable interconnect – Three kind of programmable interconnect
Programmable interconnect
Programmable CT blocks
Programmable SC blocks
PSoC Mixed-Signal Architecture
Some CAD related Issues
• Higher Level Of Abstraction For Development– What behavioral descriptions are synthesizable? DAEs, TFs,
SFGs?
– How do you correctly mix together continuous time and discrete time descriptions?
– What standard specification notations? VHDL-AMS, Verilog-A, MATLAB/SIMULINK, UML?
• Frees Designers From Low Level Implementation Details– How do you synthesize a set of DAEs? (application-specific
topologies)
– Does the design work? (circuit modeling)
– CAD tools for transistor sizing and layout (Neoliniar CADENCE)
• Supports Reconfigurability– Reconfigurable AMS architectures, reconfigurable ADCs, filters
VLSI System Design Laboratory(http://www.ece.sunysb.edu/~vsdlab)
Lab director: Dr. Alex Doboli,Email: [email protected], Phone: 631-632-1611
Lab expertise: • Embedded mixed-signal systems • CAD for system&circuit optimization• Analog circuit modeling• IP core integration
Research funding (since 2001): • NSF Center for Design of Analog and Digital IC • AFRL • NSF ITR• DARPA, IBM, DAC, Cypress
Academic results:• 3 PhDs graduated • 3 MS graduated• 19 journal papers• 65 peer reviewed conference papers
IC Developments:• Rhapsody CAD tool (ADC design)• ISIS CAD tool (SoC integration)• SoC design in 0.18µm process
VLSI System Design Laboratory(http://www.ece.sunysb.edu/~vsdlab)
• G. Gielen, R. Rutenber, “Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits”, Proceedings of IEEE, Vol. 88, No. 12, pp. 1825-1852, 2000:
“Recently, a first attempt was presented towards the full behavioral synthesis of analog systems from (annotated) VHDL-AMS behavioral descriptions”.
• A. Doboli, R. Vemuri, "Behavioral Modeling for High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS", IEEE Transactions on CADICS, Vol. 22, No. 11, 2003, pp. 1504-1520. (among the most downloaded papers in 2005)
Rhapsody: Automated design of analog and mixed-signal systems
Topology generation andsystem architecture selection:
VHDL-AMS specifications:entity aaa is
…end entity;
Performance evaluation
Circuit and interconnect
models
Obtained performanceConstraint transformation,
floorplanning and global routing
Performance evaluation (simulation)
Rhapsody (snapshots)
Benefits
Quality:- Complements SD toolbox (finding NTF and STF), Cadence’s
NeoCircuit (transistor sizing) and NeoCell (layout generation) - Produces SD topologies customized to performance specific
requirements- less complex, better sensitivity to parameter variations, and
lower power consumption- Finds 6x-10x more constraint-satisfying solutions than
CircuitExplorer (Synopsis) and NeoCircuit (Cadence)Effort:
- Designs (including circuit sizing using NeoCircuit and layout using NeoCell) can be ready much faster
- Designers can focus on more challenging issues, like system topology, selecting circuits
- Can be used by less-experienced designers- Prototyping of new applications, e.g., reconfigurable SD ADC
Application-specific ∆Σ modulator topologies
Application-specific ∆Σ modulator topologies
• The topology is an SFG containing integrators and having all signal paths and coefficients of the signal paths defined
• A topology differs from another one in terms of the type of the integratorsignal paths definition numerical coefficients of the signal paths
• For topology synthesis, they are the control parameters and uniquely determine a topology
Traditional ∆Σ modulator topologies
3rd order Delta-Sigma modulator topologies (a) Chain of Integrators with Feedforward Summation (b) Chain of Integrators with Feedforward Summation and Local Feedback (c) Chain of Integrators with Distributed Feedback (d) Chain of Integrators with Distributed Feedback, Distributed
Feedforward and Local Feedback
Previous work: I
F. Medeiro, A. Verdu, A. Vazquez, “Top-down Design of High Performance Delta-Sigma Modulators”, Kluwer, 1999
• Designers have to select an incomplete topology based on experience
• Coefficient design is the only degree of freedom to be explored.
Set integrator types
Define signal paths
Explore coefficient values
An incomplete
topology is defined
Previous work: II
K. Francken, G. Gielen, “A High-level Simulation and Synthesis Environment for Delta-Sigma Modulators”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 22, No. 8, 2003, pp. 1049-1061.
• Selected incomplete topologies (or complete topologies) are stored in a library
• Given design specifications, such as SNR and DR, the tool selects one with the smallest power consumption
Save and selectoptimal solution
Yes
No
Set integrator types
Define signal paths
Explore coefficient values
Meet Specification?
Previous work: III
O. Bajdechi, G. Gielen, J. Huijsing, “Systematic Design Exploration of Delta-Sigma ADCs”, IEEE Transactions on Circuits and Systems I, Vol. 51, No. 1, Jan 2004, pp. 86-95.
A filter level exploration of the design space defined by abstract topology parameters
implemented using theprevious design flow
Subject to sensitivityanalysis for yield
possible design solutions
Several best solutions interms of power consumption
Application-specific ∆Σ modulator topologies
• Y. Wei, H. Tang, A. Doboli, "DATE06: Systematic Methodology for Designing Reconfigurable Delta Sigma Modulator Topologies for Multimode Communication Systems", invited paper, IEEE Transactions on CADICS, accepted for publication.
• H. Tang, H. Zhang, A. Doboli, "Refinement based Synthesis of Continuous-Time Analog Filters Through Successive Domain Pruning, Plateau Search and Adaptive Sampling", IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 25, No. 8, pp. 1421-1440, August 2006.
• H. Tang, A. Doboli, "High-Level Synthesis of Delta-Sigma Modulators Optimized for Complexity, Sensitivity and Power Consumption", IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 25, No. 3, pp. 597-607, March 2006.
Proposed synthesis methodology
Define the solution space region with all the possible modulator topologies
Formulate topology synthesis as an MINLP (Mixed-Integer Nonlinear Programming) problem
Formulate the design requirements as symbolic cost functions and solve for the optimal solution
Advantages:• Global optimal solution is guaranteed• The methodology is scalable• The methodology could be fully automated
Generic topology for 3rd order modulator
adder the to from tscoefficien dfeedforwar andfeedback :adder theinput to from tscoefficien dfeedforwar :
adder theoutput to from tscoefficienfeedback :quantizer theinput to :
integrator theofoutput the:
thjji
thi
thi
thi
iYtibia
YiY
Generic topology for 3rd order modulator
Chain of Integrators with Feedforward Summation
Generic topology for 3rd order modulator
Chain of Integrators with Distributed Feedback
Generic topology for 3rd order modulator
Chain of Integrators with Feedforward Summation and Local Feedback
Generic topology for 3rd order modulator
Chain of Integrators with Distributed Feedback, Distributed Feedforward and
Local Feedback
Generic topology
(1) 1,...,1 ,0 ,01,...,1 ,,...,1 , if ,01,...,1 ,,...,1 , if ,0
+=≥≥+==<≤+==≥≥
NibaNiNjijtNiNjijt
ii
ji
ji
)()()()()()()()1(
)]()()()()([)(
)1()]()()()()([
)(
)1()]()()()()([
)(
33422411444
333223113333
332222112222
331221111111
zEzYtzYtzYtzVazubzVz
zYtzYtzYtzVazubzY
zzYtzYtzYtzVazub
zY
zzYtzYtzYtzVazub
zY
+×−×−×−×−×=−
×−×−×−×−×=
−×−×−×−×−×
=
−×−×−×−×−×
=
Symbolic TF for generic topology
• Generalize the symbolic expressions for Delta-Sigma modulator of any order
• For example, the numerator and denominator of of Delta-Sigma modulator of order are:
• Solve the above equation using MATHEMATICA toobtain and
dNTFnNTF
N
)()(zEzVNTF =
)()(zUzVSTF =
N
∑∑ ∑
∑∑
≠ ≠
−−−
=
−−
=
+
−+
+−−=
N
i
N
i
KNN
iiiiiiiiiiiii
KKKN
K
N
iii
KN
N
K
KN
Kn
ztttC
tCCNTF
K
KKKK
1 2
21212211)......)1(
...()1(
),...,,(),...,,(),...,,(
1
11
0
1
KNN
i
N
i
N
iiiiiiiiiiiii
KKKN
K
N
iii
KN
KN
KN
N
j
N
j
N
jjjjjjjjjjjjj
N
ii
KKKN
N
i
N
j
N
jjNjjNji
KN
N
iNii
KN
K
N
i
N
i
N
iiiiiiiiiiiii
KKKN
KN
iii
KN
N
K
KN
K
d
ztttC
tCCatttaC
ttaCtaC
tttCtCC
NTF
K
KKKK
K
KKKK
K
KKKK
−
≠ ≠
−−
=
−−
++
≠ ≠=
−−
= ≠++
−−
=+
−−
+
≠ ≠
−−
=
−−
=
+
∑∑ ∑
∑∑∑ ∑∑
∑ ∑∑∑
∑∑ ∑∑∑
−+
+−−+
+++−+
+−++−−
=
))......)1(
...()1()......
...()1(
...)......)1(...(()1(
1 2
21212211
1 2
21212211
1 2
2221
1 2
21212211
),...,,(),...,,(),...,,(
1
11
11),...,,(),...,,(),...,,(
1
1),1(),1(
22
11,
11
1
),...,,(),...,,(),...,,(1
11
0
1
Symbolic NTF and STF
• Complexity of growth of terms is roughly 4×N !
• Generally, modulator order is kept below 6~8, the symbolic expressions scale reasonably well
• MINLP is able to handle large number of constraints of different complexity
• Symbolic expressions for other combination of integrator types can be readily obtained via variable substitution
MINLP problem formulation
• By equating the symbolic TF to the desired TF, 3×(N+1) equations are obtained with (N+1)×(N+2) unknowns
• Properties for the symbolic TF:All terms are nonlinear expressions of the defined coefficient variables No quadratic terms
• This mild nonlinear formulation is suitable to be solved by NLP
• To select the signal paths, binary variables are defined, so MINLP
MINLP formulation
};1,0{ ),1( : ;0),( :
;0)( : ),( minimize
∈≤
=
ii
ii
i
ii
wxsatisfyxtosubjectwxxhtosubject
xgtosubjectwxxf
Linear constraints h are added considering the complexity of nonlinear product term Instead, we formulate h as:
small very is whereotherwise, 0 and if 1 εε =≥= iii wxxwxii wxx ×
Topology exploration flow
Initialize modulator order
Initialize combination
Initialize OSR
Initialize MAG
Generate NTF
Generate and solveMINLP program
Meet SNR, DR specification
Save solution
Go to next combination
Optimal solution
No
Yes
Yes
SNR, DR specification
Increase order
More combinations
Increase MAG
Increase OSR
YesYes YesYesNo No NoOSR in
rangeOrder
in rangeMAG in range
Minimum sensitivity test
Minimum power test
Minimum path test
Topology refinement
• Scaling => the voltage swings at the output of each integrator are within a certain range
• Nonideal blocks in Simulink
Experiment: 3rd order modulator
• 3rd order Delta-Sigma modulator• DR>70db•
• The topology is able to achieve DR=72db and SNR=67db
5.1 ,32 , ,5.1 ,3 max
==
===
MAGOSRVUPN ref
)6629.0529.1)(6685.0()1994.1)(1(
2
2
1 +−−+−−
=zzzzzzNTF
Optimal topology
A. Minimum signal path (topology not unique)
Optimal topology
B. Minimum sensitivity
Sensitivity cost function values are 1.723 and 2.250 respectively, with all (good case)L. Huelsman, “Active and Passive Analog Filter Design”, McGraw Hill, 1993
0.1 , ≤j
i
j
i
qx
Px SS
Topology from Toolbox
0.1, 3
34
3
3≥q
tqa SS
Sensitivity cost function values is 4.454, with some terms larger than 1.0, e.g.
R. Schreier, “The Delta-Sigma Toolbox 6.0”, www.mathworks.com/matlabcentral/fileexchange, Nov 2003.
Triple-mode continuous-time ∆Σ modulator
270kHz14.5/87EDGE190kHz15/90GSM615kHz13/80CDMA2000
1.92MHz11.5/70UMTSBandwidthDR (bits/dB)Mode
Design Specifications
484028, 32564484049664483--128962
GSM-EDGECDMA2000UMTSOSR
OrderDesign parameters
for possible candidates
[1] R. Veldhoven, “A Triple-Mode Continuous-Time ∆Σ Modulator With Switched-Capacitor Feedback DAC for a GSM/EDGE/CDMA2000/UMTS Receiver”, JSSC, Dec 2003.
Reconfigurable ∆Σ modulator topologies (1)
ΣΣ
0.5917−m10.5316−m20.5878−m3
1.3013−m21.3009−m1
1.3944−m3
ΣV
Σ ΣΣ
0.0785−m1
0.0442−m20.0360−m30.0013−m3
0.0024−m2
0.0069−m1
0.3420−m1
0.3605−m20.4008−m3
U
− 0.1970−m1
0.1667−m3 0.1670−m2
0.7720−m3
0.1552−m2
0.1324−m3 0.1364−m1
0.6244−m1 0.6585−m2
0.7987−m1
0.8988−m2 0.8762−m3
− −0.6274−m1
0.5261−m3 0.5133−m2
0.4815−m3
0.5159−m1, m2
0.4815−m3 m2 0.5159−m1,
0.1533−m3 0.1467−m2
0.1200−m1
Topology opt1
Generated topologies
Σ ΣΣ
U
−Σ Σ
0.0206−m3
0.0342−m1
0.0324−m2
ΣV
0.0349−m1
1.3000−m31.2080−m2
0.4545−m10.5556−m20.5163−m3
0.4545−m1
m2,m3
0.2222−m1
0.1829−m3 0.1769−m2
1.3000−m2,m3
0.4500−m1
0.4000−m1
1.4765−m10.5556−m20.5163−m3
1.3408−m10.1545−m1
0.8655−m2 0.8000−m3
0.4789−m2 0.4771−m3
−
0.5706−m1 0.5143−m2 0.6009−m3
0.0941−m2 0.0836−m3
0.2647−m1
0.0108−m1
−
Topology opt2
Design complexity
ηd : estimated design effort
ηp : estimated power consumption reduction
Np : # of signal pathsNp,r : # of non-reconfigurable cellsNc,r : # of reconfigurable cells
SNR degradation due to circuit noise
10−3
10−2
−150
−100
−50
0
Frequency (f/fs)
Spe
ctru
m (
dB)
Output spectrum comparison
opt2, noise = −60dB[1], noise = −60dBopt2, noise = −70dB[1], noise = −70dBopt2, ideal[1], ideal
−40 −35 −30 −25 −20 −15 −10 −5 0−10
0
10
20
30
40
50
60
70
80
90
Input amplitude [dB]S
NR
[dB
]
SNR comparison for different noise level
opt2, ideal[1], idealopt2, noise = −60dB[1], noise = −60dBopt2, noise = −50dB[1], noise = −50dB
Improvement as compared to the state-of-art design:3dB for the case of -60dB noise level5dB for the case of -50dB noise level
Experiments
Experiments
• Compare the triple-mode modulator with three single-mode modulators obtained with ∆Σ toolbox
– Design effort can be less than 1/3
– Complexity can be as less as 40%
– Power saving can be as large as 24.2%
– More robust to circuit nonidealities
Experiments using PSoC
• Implementation of a reconfigurable Delta-Sigma modulator using PSoC mixed-signal SoC
Experiments using PSoC
Experiments using PSoC
Experiments using PSoC
Education & Training
• Hugo De Man, “System-on-Chip Design: Impact on Education and Research”, IEEE Design & Test of Computers, July-Sept. 1999.
• System architects/designers:– Cross-disciplinary background: EE/CE/CS
– EE: signals, conversion techniques, impact of circuit nonidealities, and know how to tackle these
– CE: how HW & SW work together, abstraction levels, successive refinement, trade-off analysis
– CS: high-level description languages for systems, system and circuit modeling techniques, formal verification
Education & Training
Curricula, textbooks, projects, lab material, exercises?
A. Doboli and E. Currie“Embedded Mixed-Signal Systems: A Designer’s
Perspective”, due to be published in 2007.
Conclusions
• PSoC: embedded mixed-signal architecture
• Related research at Stony Brook
• Systematic methodology for ∆Σ ADC design
• Automated circuit modeling
• Education & training
Automated Macromodeling
• Produced macromodels:– Structural– No feedback dependencies (decoupled)– Symbolically characterized nonlinear current
sources– Extensible, accuracy is controllable– Insight into circuit– Reusable
Automated Macromodeling
f(vin)vin vout
Black-box macromodel
Vin1
v3v2
Vin2v1
VbnM5
M3 M4
M2M1
Circuit netlist Structural nonlinear macromodel
id3nkΣ
kid1nkΣ
kiCdb3nkΣ
kiCdb1nkΣ
k
id4nkΣ
kid2nkΣ
kiCdb4nkΣ
kiCdb2nkΣ
k
id3nkΣ
kid4nkΣ
kiCsb3nkΣ
kiCsb4nkΣ
kid1nkΣ
kiCdb5nkΣ
k
(sCgd4−gmg4)vin2 v1
gms4 C3(sCgd2−gmg2)v2
R3
(sCgd3−gmg3)vin1 v1
gms3 R2C2
V2
V3
C1 R1
V1
(sCgs3+gm3)vin1
(sCgs4+gm4)vin2
gmd3v2,eq
gmd4v3,eq
sCgd2v3,eq
(R2,C2)
Automated Macromodeling
v3
sCgd2v3
d3nk
iΣk
d4nk
iΣk
d5nk
iΣk
d3nk
iΣk
d1nk
iΣk
d4nk
iΣk
d2nk
iΣk
v3
(sCgd3−gmg3)vin1
gms3v1
C2 R2
v2
(sCgd4−gmg4)vin2
gms4v1
(sCgd2−gmg2)v2
C3 R3
v1
C1 R1
Σk
db5nkCCΣ
ksb4nkCΣ
ksb3nk
CΣk
db3nk CΣ
kdb1nk
CΣk
db2nkCΣ
kdb4nk
(sCgs3+gmg3)vin1
(sCgs4+gmg4)vin2
gmd3v2
gmd4
Vin1
v3v2
Vin2v1
VbnM5
M3 M4
M2M1
Circuit netlist
Automated Macromodeling
103
104
105
106
107
108
−100
−90
−80
−70
−60
−50
−40
Frequency [Hz]
HD
[dB
]
Comparison of HD2, HD3
HD3, SPICEHD3, modelHD2, SPICEHD2, model
Comparison of HD2, HD3
Automated Macromodeling
vout
Vin2
v3
RL CL
CfRfv2
Vin1
v4
v1
M1 M2
M6
M8
M9M7M5
M3 M4
Vbn
Automated Macromodeling
vout
d3nk
iΣk
d4nk
iΣk
d5nk
iΣk
CΣk
sb3nk CΣ
ksb4nk CΣ
kdb5nk
CΣk
db3nk CΣ
ksb2nkCΣ
ksb1nk
d3nk
iΣk
d1nk
iΣk
v3
d2nk
iΣk
d4nk
iΣk
CΣk
db2nk CΣ
kdb4nk
d8nk
iΣk
CΣk
sb8nk CΣ
kdb9nk
d9nk
iΣk
d6nk
iΣk
d7nk
iΣk
CΣk
db6nk CΣ
kdb7nk
gms3v1 (sCgd2)v3eq C2 R2(sCgd3−gmg3)vin1
vin1 Vin2 C1 R1(sCgs3+gmg3) (sCgs4+gmg4) gmd3 gmd4
v2eq v3eq
v1
v2
(sCgd2−gmg2)v2
(sCgd4−gmg4)vin2 gms4v1
(s(Cf+Cgd8)(1/Rf))v4eq C3 R3
(sCgs8+gmg8)v4 C5 R5
+1/Rf−gmg6)v3(sCgs8)v5eq
(s(Cgs6+Cf)
v4
C4 R4
Automated Macromodeling
103
104
105
106
107
108
−300
−250
−200
−150
−100
−50
0HD2 contribution
Frequency [Hz]
HD
2 [d
B]
M8M5M6M3,4M1,2HD2, modelHD2, SPICE
Automated Macromodeling
vout
Vin2
v3
RL CL
CfRfv2
Vin1
v4
v1
M1 M2
M6
M8
M9M7M5
M3 M4
Vbn
Automated Macromodeling
103
104
105
106
107
108
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
Frequency [Hz]
HD
[dB
]HD3 comparison for two−stage OpAmp
SPICEmodel
Automated Macromodeling
vo1
CΣk
db3nk
d7nk
iΣk
d3nk
iΣk
CΣk
db7nk
CΣk
db9nk
d11nk
iΣk
d9nk
iΣk
CΣk
db11nk
d1nk
iΣk
d3nk
iΣk
d5nk
iΣk
CΣk
sb1nkCΣ
ksb3nk CΣ
kdb5nk
CΣk
db1nk
d13nk
iΣk
d1nk
iΣk
CΣk
db13nk
v1
gms3
v1,eq(sCgd3−gmg3)
vin1
sCgd9v3,eq R5 C5
sCgd1vo1,eq
(sCgd9−gmg9)
v5
sCgs1v1,eq C3R3
(sCgs3+gmg3)vin1
(sCgs1+gm1)v3
gmd3v5 R1
gmd1vo1,eq C1
v3
(sCgd1−gmg1) gms1v1 Ro1 Co1
v5
v3
M13
R
Vo1 Vo2
ClCl
v1 v2
v4v3
v6
Vin1 Vin2
M1 M2
M14
M3
M9
M11 M6 M12
M4
M8
M10
M7
v5
Vbp Vcmfb Vbp
VbnM5
Automated Macromodeling
103
104
105
106
107
108
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency [Hz]
HD
[dB
]HD3 comparison for OTA
HD3, SPICEHD3, model
Automated Macromodeling
1 2 3 4 5 6 7 80
5
10
15
20
25
30
35
40
45
50
Number of iteration
Err
or [%
]complexity vs. accuracy
single−stage, up to 100MHzsingle−stage, up to 10MHztwo−stage, up to 100MHztwo−stage, up to 10MHz