System-on-Chip Subband Decomposition Architecturesfor Ultrasonic Detection Applications

Erdal Oruklu & Joshua Weber & Jafar Saniie

Received: 22 April 2011 /Revised: 26 July 2011 /Accepted: 29 August 2011 /Published online: 22 September 2011# Springer Science+Business Media, LLC 2011

Abstract This paper presents a hardware efficient system-on-chip (SoC) sensor architecture for ultrasonic imagingapplications that uses the split-spectrum processing (SSP)algorithm. The SSP design is realized using recursivesubband decomposition techniques for achieving minimalhardware and power consumption. Recursive implementa-tions of discrete Fourier transform (DFT) and discretecosine transform (DCT) are presented for subband decom-position which result in sparse transform operations andsignificantly reduced hardware and power requirements. Acomparative study and performance results present theadvantages of the recursive hardware architecture comparedto the conventional implementation of the SSP algorithmusing IP cores for FFT.

Keywords Recursive DCT. Ultrasound . Subbanddecomposition . Goertzel

1 Introduction

Ultrasonic imaging has applications in many industries,ranging from manufacturing, medical imaging, to non-destructive evaluation for quality control and safety. Inparticular, ultrasonic testing has been widely used for flawdetection and monitoring the integrity of the civil structuressuch as bridges [1, 2], detection of cracks in welds [3, 4]and concretes [5].

Ultrasonic sensors can identify the problems oftenhidden within these structures, becoming an effective

procedure for the safety, maintenance, repair and lifeextension of critical structures. However, the nature ofmeasured ultrasonic echoes is complex; measured scatteredechoes often consist of many multiple interfering echoes.Detection and unraveling these echoes for evaluating andcharacterizing source of echo scattering require advancedsignal processing methods such as frequency-diverse signaldecompositions [6]. These algorithms present a greatcomputational challenge due to real-time sensor dataprocessing and scalability needs. A conventional hardwaredesign based on microcontrollers and digital signal pro-cessors falls far short of meeting the combined demands ofhigh speed, compact area, low power and adaptabilityrequirements. On the other hand, Field Programmable GateArray (FPGA) devices facilitate fast development time andadaptable architectures for signal processing applications inmany domains [7–9], including ultrasonic testing andmeasurements [10]. Within the field of ultrasonics, FPGAuse is becoming more prevalent, with studies demonstratingtheir use in multi-mode techniques for reducing scanningtime [11] and in ultrasonic pulsed Doppler flow measure-ments [10]. Due to the unparalleled adaptability andscalability of FPGAs, they can be re-programmed, designscan be modified, changed and improved continuously withno extra cost overhead.

In this paper, we propose FPGA based smart sensornodes for ultrasonic imaging algorithms, specificallytargeting low-power and reduced hardware implementationsuitable for distributed sensor networks. In order to meetthese objectives, optimizations are required at both algo-rithm level and architectural level. The architecturesexplored in this paper target a well-established ultrasonicflaw detection algorithm, split-spectrum processing (SSP)[6]. The SSP algorithm is based on subband decompositiontechniques and it has high computational load and memory

E. Oruklu (*) : J. Weber : J. SaniieIllinois Institute of Technology,Chicago, IL, USAe-mail: erdal@ece.iit.edu

J Sign Process Syst (2012) 68:367–377DOI 10.1007/s11265-011-0623-9

requirements. In this study, in order to meet the highperformance and low power design goals, recursive filterstructures is introduced and realized on FPGA logic. Theserecursive filter structures are able to perform the signaldecomposition with significantly reduced logic resourcesand power consumption. In addition, the filter structures areable to produce each signal component independently,allowing for fine grained control of parallelism. Thisenables a sparse transform resulting in a large reduction incomputation complexity while maintaining the same overallperformance.

In Section 2, SSP algorithm for flaw detection isdiscussed. Section 3 presents the FPGA based platformdesigned for exploring multiple hardware/software (HW/SW) co-design approaches. Recursive implementations andtheir analysis are presented in Section 4. The results andcomparisons of the different architectures are discussed inSection 5.

2 Ultrasonic Detection Algorithms

Ultrasonic target detection is made difficult by the presenceof high scattering microstructure noise. This scatteringnoise is the result of a large number of small randomlydistributed scatterers arising from the microstructure of thematerials. When the transmitted wavelength of the ultra-sonic signal is larger than the microstructure of the materialunder test, the echoes exhibit Rayleigh scattering [12].These clutter echoes exhibit a large degree of randomnessin amplitude and sensitivity to frequency shifts. Specifically,microstructure scattering results in an upward shift in the

expected frequency of broadband ultrasonic scattering echoesor clutter. On the other hand, targets (flaws) are most oftenmuch larger than the transmitted wavelength and behave likegeometrical reflectors. Consequently, target echoes oftendisplay a downward shift in their expected frequency whichis caused by the overall effect of attenuation governed by thephysical properties of the propagation path. This downwardfrequency shift of the target echoes is a productive attributesince it enables the exploration of the frequency content ofultrasonic signals and subbands in order to improve the targetvisibility.

The SSP algorithm uses this fact to achieve decorrelationbetween the target (flaw) echo and clutter noise. Thealgorithm, as shown in Fig. 1, works by decomposing thewideband input signal into a series of overlapping narrowsubbands using transform techniques such as FFT or DCT.The subbands are placed as a series of overlappingbandpass filters which contain information about the flawechoes and a subset of the scattering noise. These subbandchannel outputs are then combined back together in a post-processing unit utilizing Bayesian [12] or order statistics[6]. Within order statistics, it is shown that an absoluteminimizer is able to achieve substantial performanceimprovements.

Figure 2 shows the output of eight subband channels foran experimental ultrasonic signal using a 5 MHz transducerand testing a steel block with an embedded flaw. It can beseen that clutter echoes are much more susceptible tofrequency variation compared to the flaw echo. For SSP,the most important performance metric is the Flaw-to-Clutter (FCR) ratio and it is used to judge the overallperformance of the algorithm. It relates the strength of the

TransformInverse

TransformInverse

1f

mf

2f

y (n)

m)n(X

2)n(X

1)n(X

)n(x

)n(s

BroadbandTransmitter

PostProcessing

Block

TransformInverse

TransformForward

ReceiverWindowing)(

Bandpass filters

Wideband signal

Subband Decomposition Block

SampleUnderTest

c

c

c

Figure 1 Split-spectrum processing target detection algorithm.

368 J Sign Process Syst (2012) 68:367–377

flaw echo to the surrounding clutter noise. This ratio is adirect representation of how a flaw echo can be detected inthe surrounding noise. The equation to calculate the FCR isgiven in (1).

FCR ¼ 20»log10 F=Cð Þ ð1Þwhere F is the maximum target echo amplitude and C is themaximum clutter echo amplitude.

An example SSP implementation result of ultrasonicexperimental data using minimum detector is shown inFig. 3. The results (typically more than 10 dB improve-ment) demonstrate the ability of the SSP algorithm toperform flaw detection robustly even when the input FCRis very poor.

3 FPGA Platform and Architectural Investigation

A highly modular and flexible FPGA system, based onXilinx Virtex 4 FPGA and A/D chips, has been designedand demonstrated in [13]. We leverage the modularity ofthis platform to compare multiple architectural and imple-mentation variations for efficiency. The modularity pro-

vides the reconfigurability of the design to support themany parameter changes necessitated by the SSP algorithm.To accomplish this task, the system tasks are broken intothree modules, signal capture, signal processing, andcommunications as shown in Fig. 4.

Signal capture module is composed of ADC chipswhich capture the incoming data from the ultrasonictransducer. The ADC converter allows for continuous dataacquisition at 14-bits of precision and 105 MHz samplerate. Furthermore, it has a dynamic range of ±1 V, givingthe ability to resolve very small signal changes. The ADCunit is controlled from and provides data to the mainFPGA (Virtex-4 FPGA by Xilinx). The incoming signaldata is captured using a single ADC chip. The sampleddata is the echo response from the pulsed firing of anultrasonic transducer. The system controls the firing of thetransducer and capturing of all echo data coming in fromthe dedicated ADC chips. It also provides pre-processing,by implementing a configurable amplifier to the incomingdata. The sampling of the incoming data is performedindependent of the signal processing; allowing for aconfigurable clock rate and a selectable sample rate forthe incoming data.

0 500 1000 1500 2000 2500−1

0

1

0 500 1000 1500 2000 2500−1

0

1

0 500 1000 1500 2000 2500−1

0

1

0 500 1000 1500 2000 2500−1

0

1

0 500 1000 1500 2000 2500−1

0

1

0 500 1000 1500 2000 2500−1

0

1

0 500 1000 1500 2000 2500−1

0

1

0 500 1000 1500 2000 2500−1

0

1

Data Points

Am

plitu

de

Flaw Echo

Flaw Echo

Flaw Echo

Flaw Echo

Flaw Echo

Flaw Echo

Flaw Echo

Flaw Echo

2500200015001000500

a) Experimental Ultrasonic Signal

b) Subband Channel Outputs

Data Points

0

1FlawEcho

Figure 2 Subband channels showing random variation for clutter echoes.

J Sign Process Syst (2012) 68:367–377 369

The communication module provides a channel thatallows for command and control from the host PC. It canmonitor the status of the FPGA operations through 16DMA channels providing a high bandwidth directionconnection to internal Block RAMs (BRAMs).

The signal processing module is different for eacharchitectural variation. In particular, radix-2, radix-4 FFTIP-cores and recursive implementations of DFT and DCTtransforms are investigated. The implementation of inter-faces to other modules and the implementation of the order

statistic post processor (minimization) remain the same inall designs compared.

As a base reference system, a 4-channel Radix-2 FFT withabsolute minimization post processing signal processingmodule is created. Using higher number of subbands (i.e.,8-channels instead of 4) typically increases the performance ofthe SSP algorithm by exploiting the frequency sensitivity of theclutter echoes; however, the system hardware requirements arealso increased significantly. Both FCR detection performanceand resource usage results will be presented in Section 4.

Virtex-4 FPGAUltrasonic Sensor Node

Signal CaptureModule

PulserControl

ADC andAmplifierControl

Signal ProcessingModule

SubbandDecomposition

Hardware

CommunicationModule

Pulser

Receiverand ADC

Excitation Pulse

Acousticsignal

Transducer

PC control andMatlab GUI

interfacePCI, USB and

wirelessinterface

Figure 4 FPGA based ultrason-ic imaging platform.

0 500 1000 1500 2000 25000

1

0.5

Am

plitu

de

0 500 1000 1500 2000 25000

1

0.5

Flaw echoClutter echoes

Flaw echo

Clutter echoes

0

0.5

1

Am

plitu

de0 500 1000 1500 2000 2500

Clutter echoes

Flaw echo

Am

plitu

de

a) Experimental Ultrasonic Signal

b) Flaw detection using FFT based SSP

c) Flaw detection using DCT based SSP

Figure 3 FCR improvement us-ing SSP algorithm.

370 J Sign Process Syst (2012) 68:367–377

3.1 FFT Architectural Variations

The signal processing base system was modified to utilizethree different DFT based implementation techniquesincluding Radix-2 and Radix-4 FFT designs using XilinxIP cores [14] and a hardware efficient design based onGoertzel’s algorithm [15]. The radix-2 and radix-4 FFTdesigns are based on the well-known Cooley-Tukeytechnique. These IP cores are highly optimized to utilizethe FPGA resources, specifically for efficient use of DSP48units and embedded memory elements within the Virtex-4FPGA.

3.2 Goertzel Architecture

Upon inspection of the SSP algorithm, it is clear that not alltransform coefficients are used for post-processing. Muchof the frequency information (transform coefficients) isunnecessary, and filtered out during the subband decompo-sition. Specifically, only around 10% of the total frequencyinformation is preserved in the subband decompositions(see Fig. 5 for the frequency region of interest). This is dueto the downward frequency shift of the flaw echoes andupward frequency shift of the clutter echoes in the Rayleighscattering region as explained in Section 2. If we want todetect flaw echoes, low-frequency region is the primaryregion of interest.

Consequently, we reason that much of the computationalload could be reduced by generating only the necessarycoefficients. Hence, the use of a sparse transform can bemore computationally efficient. In order to take advantageof this fact, we have implemented a Goertzel based Fouriertransform [16, 17]. The Goertzel algorithm has theadvantage that it can compute each frequency componentindividually. While slower on average to compute a singlefrequency component, we leverage the fact that we can nowcompute only a subset of the total frequency components toproduce a more efficient design.

Fourier transform kernel can be written as:

X ½½k� ¼XN�1

n¼0

x½n�WknN k ¼ 0; 1; . . . ;N � 1 ð2Þ

whereWN ¼ e�j 2pNð Þ ð3Þ

Goertzel takes advantage of the periodicity of W�knN in

order to reduce computation. We observe that:

W�kNN ¼ e j 2p

Nð ÞNk ¼ e j2pk ¼ 1 ð4Þ

Due to (4), right side of (2) can be multiplied byW�kN

N without affecting the result:

X ½k� ¼ W�kNN

XN�1

r¼0

x½r�WkrN ¼

XN�1

r¼0

x½r�W�kðN�rÞN ð5Þ

Define the sequence:

yk ½n� ¼X1r¼�1

x½r�W�kðn�rÞN u½n� r� ð6Þ

From (5) and (6) and the fact that x[n] = 0 for n < 0 andn ≥ N, it follows that

X ½k� ¼ yk ½n�jn¼N ð7ÞHence, X[k] can be obtained after N iteration of a filter

with the following system transfer function:

HkðzÞ ¼ 1

1�W�kN z�1

ð8Þ

The Goertzel IIR filter structure is shown in Fig. 6. Thisfilter structure is very straightforward to implement. It usesvery few hardware resources and takes advantage of thebuilt-in DSP48 elements in Virtex-4 FPGA [18] to performfast single cycle multiplications. The small resource

0 5 MHz 10 MHz 15 MHz 20 MHz0

0.5

1

Frequency Region of Interest(Subband Channels)

Figure 5 Subband locationsover frequency region ofinterest.

J Sign Process Syst (2012) 68:367–377 371

consumption of this implementation is advantageous in manyways. As each frequency component is generated indepen-dently, multiple instances of this filter structure can beimplemented to calculate in parallel. This allows for flexiblecontrol over the performance of the design against the cost inresource consumption. SSP implementation in Fig. 7 illus-trates this. If five Goertzel filter kernels are available in thesystem; they can be used for both forward and inverseFourier transform operations. For the forward transform, allfive kernels operate in parallel, calculating different frequen-cy coefficients since they are independent. Hence, execution

time of forward Fourier transform will be five times fastercompared to single Goertzel kernel use. For the inversetransform, four subband channels are necessary; eachGoertzel kernel executes one inverse DFT. The throughputof the system can be easily doubled by instantiating fivemore Goertzel filters. In Section 5, we present resultsutilizing both five and ten Goertzel filter kernels.

In Fig. 7, an absolute minimizer (an order statistics filter)is used for post-processing and the SSP result.

yminðnÞ ¼ min xiðnÞj j; i ¼ 1; 2; . . . ; k½ � ð9Þ

Figure 6 Goertzel discreteFourier transform blockdiagram.

Figure 7 SSP implementation using 5 Goertzel filter kernels.

372 J Sign Process Syst (2012) 68:367–377

where y is the SSP output, xi is the SSP channel i, and kis the total number of the SSP channels. This postprocessor step uses the partially uncorrelated observa-tions and makes use of statistical differences in thechannels corresponding to random processes inherent tomicrostructure and flaw echoes for improved flawdetection. The statistical differences of microstructureand target echoes can be exploited for improving theFCR.

3.3 DCT Architectures

Discrete cosine transform can be used in split-spectrumprocessing for subband decomposition requiring no com-plex number operations. In this work, we have created ahardware implementation of the DCT and integrated it into

the system platform, allowing comparisons between theperformance of DCT and FFT transforms.

As SSP works with very large data sets, most prior workinto DCT implementations is of limited applicability. Butsimilar to the Goertzel algorithm, we utilize a techniqueallowing for a sparse transform. Decomposing the DCTdown into a recursive type structure allows for calculationof values in a similar manner to the Goertzel based FFT.DCT can be implemented with a recursive IIR filterstructure using Clenshaw’s recurrence formula [19]. Althoughhardware requirements are very basic for the recursivestructure, computationally, it requires N2 clock cycles for Ndata points. In [20], faster recursive structures have beenpresented to improve the computation time. These structuresemploy a folding operation by exploiting the symmetryproperties of the cosine terms. Furthermore, even and odd

Figure 8 Recursive DCT foreven coefficients.

Figure 9 Recursive DCT forodd coefficients.

J Sign Process Syst (2012) 68:367–377 373

inputs can be processed separately with additional IIR filterblocks.

DCT kernel can be written as:

Y ½k� ¼ffiffiffiffiffi2

N

rEk

XN�1

n¼0

x½n� cos ð2nþ 1Þkp2N

k ¼ 1; 2; . . . ;N � 1

ð10Þ

Ek ¼ffiffiffi1

2

rfor k ¼ 0 and Ek ¼ 1 for k 6¼ 0 ð11Þ

A single folding operation applied to DCT results in:

Y ½k� ¼ffiffiffiffiffi2

N

rEk

XN2�1

n¼0

wk ½n� cos ð2nþ 1Þkp2N

ð12Þ

where

wk ½n� ¼ x½n� þ ð�1Þkx½N � 1� n� ð13ÞFor k = even samples, define:

Y ½k� ¼ffiffiffiffiffi2

N

rEkð�1Þk2gk N

2� 1

� �ð14Þ

where

gk ½j� ¼Xj

n¼0

wk ½j� n� cos nþ 1

2

� �qk ð15Þ

Z-transform of the convolution given in Eq. 15 can berepresented as a filter with the following transfer function:

Gk ½z�Wk ½z� ¼

cos qk2

� �ð1� z�1Þ1� 2 cos qkz�1 þ z�2

ð16Þ

Similarly for k = odd samples, define:

Y ½k� ¼ffiffiffiffiffi2

N

rEkð�1Þk�1

2 hkN

2� 1

� �ð17Þ

where

hk ½j� ¼Xj

n¼0

wk ½j� n� sin nþ 1

2

� �qk ð18Þ

The Eq. 18 can be represented as a filter with thefollowing transfer function:

Hk ½z�Wk ½z� ¼

sin qk2

� �ð1þ z�1Þ1� 2 cos qkz�1 þ z�2

ð19Þ

Figures 8 and 9 show second order IIR filter structures foreven and odd k, respectively. By implementing these twostructures in parallel, two frequency components can becomputed every N/2 cycles. Like the Goertzel based Fouriertransform, it is straightforward to implement the DCT IIRfilters. By using DSP48 elements, we can enable andinstantiate additional units to increase performance results.

Table 1 Flaw-to-clutter ratio improvement.

MatlabFFT

HW/SWCo-design

Hardware4-channel

Hardware8-channel

HardwareGoertzel DFT

MatlabDCT

RecursiveDCT

(dB) (dB) (dB) (dB) (dB) (dB) (dB)

Average Improvement 10.89 10.08 7.43 10.69 10.79 12.35 10.32

Standard Deviation 3.29 3.14 3.49 1.99 3.23 3.13 3.11

Table 2 FPGA processing time of the SSP algorithm.

Algorithm stage HW/SW codesign(with FFT accelerator)

Hardwareradix-4FFT

Hardwareradix-2FFT

Hardware GoertzelDFT (5 filterkernels)

Hardware GoertzelDFT (10 filterkernels)

HardwarerecursiveDCT (5 filterkernels)

HardwarerecursiveDCT (10 filterkernels)

Forward Transform 3,456 1,322 5,190 6,144 3,072 1,536 768

Window Filtering 91,456 1,024 1,024 1,024 1,024 1,024 1,024

Inverse Transform 13,824 1,322 5,190 30,720 15,360 7,680 3,840

Post Processing 196,661 1,024 1,024 1,024 1,024 1,024 1,024

Total Cycles 305,397 4,692 12,428 38,912 20,480 11,264 6,656

Clock Frequency 100 MHz 115 MHz 115 MHz 115 MHz 115 MHz 115 MHz 115 MHz

Total Time 3,050 μs 41 μs 108 μs 338 μs 178 μs 97 μs 57 μs

374 J Sign Process Syst (2012) 68:367–377

4 Experimental Results

4.1 Flaw-to-Clutter Ratio Enhancements

A set of ultrasonic A-scan data measurements (data size is1024 samples per A-scan) are processed by the SSParchitectures and benchmarked according to their FCRperformance. Table 1 presents the average FCR improve-ment results for all the implementations investigated in thisresearch. It is also important to point out that parameterchanges such as location, overlap amount and the numberof subbands can induce significant impact on FCRperformance. For fair comparison, these parameters wereidentical in each implementation.

The FFT and the DCT results are obtained from Matlabimplementations which use floating-point representationand serve as reference point and benchmark for FPGA-based hardware designs. A hardware/software (HW/SW)codesign implementation [13] which uses a C-programrunning on the soft-core Microblaze processor with adedicated FFT accelerator IP-core is also shown in Table 1.Variations between architectures occur due to the impact offinite word-length precision (16-bit internal datapath usedin all cases). In general, the recursive structures based onGoertzel and DCT are able to achieve nearly identicalperformance to Matlab implementations, outperformingFFT IP-core designs. Accumulator registers have beentailored to prevent overflow while maintaining the highestlevel of precision.

4.2 Execution Time

The main objective of the proposed ultrasonic smart sensorarchitectures is to achieve real-time processing of Ampli-tude Scan (A-Scan) data with minimal resource usage andpower dissipation. Typically, a processing rate exceeding1 KHz can be considered real-time for ultrasonic imaging.This gives only a 1 ms time window to perform capture andprocessing of A-Scan. The execution time results for all thearchitectures are shown in Table 2. Execution times foreach processing step in the SSP algorithm are alsopresented in Table 2.

All of the hardware architectures are able to achieve thenecessary repetition rate. It is important to note that theproposed recursive DCT structures are able to performfaster than radix-2 FFT implementations due to sparsetransform operations. In addition, the recursive structuresare much more adaptable to performance requirements.Since the recursive structures are able to produce eachfrequency component separately, multiple componentscould be produced in parallel by instantiating additionalfilter structures. Hence, doubling the number of filterkernels from 5 to 10 reduces the computation time almostby half for both Goertzel and DCT implementations (seeTable 2). This allows for direct control over the trade-offbetween needed performance and resource consumption.The fastest implementation is based on radix-4 FFT IP-core;however, it is also the most expensive implementation withrespect to area and power.

Table 3 FPGA resource usage.

HW/SW codesign(with FFT accelerator)

Hardwareradix-4 FFT

Hardwareradix-2 FFT

HardwareGoertzel DFT(5 filter kernels)

HardwareGoertzel DFT(10 filter kernels)

Hardwarerecursive DCT(5 filter kernels)

Hardwarerecursive DCT(10 filter kernels)

Slice 6,949 17,365 8,388 4,035 4,797 4,228 5,795

LUTs 8,768 18,302 9,415 5,495 7,089 5,530 7,576

DSP48s 25 90 30 20 40 12 24

RAM16 68 64 34 37 67 34 61

Figure 10 Power consumptioncomparison.

J Sign Process Syst (2012) 68:367–377 375

4.3 Resource Consumption and Power Dissipation

Resource consumption for all the designs is presented inTable 3. For the target platform Virtex-4 FPGA, there arefour major resources, slices of configurable logic, look-uptables (LUTs), embedded DSP48 multiply and accumula-tors, and embedded block RAM. Radix-4 FFT IP coreimplementation requires the largest resource consumptionwith minimal performance gain against recursive techni-ques. Goertzel and DCT implementations use similaramount of resources with the exception of DSP48 compo-nent. Significant savings (i.e., 75% and 50% less logicslices; 75% and 33% less DSP48s compared to radix-4 andradix-2 techniques, respectively) are observed againstconventional techniques while using five filter kernels inparallel. Table 3 also indicates that scaling is very efficient.Using ten filter kernels increase the hardware resourcesmarginally while almost doubling the performance.

Power consumption results are shown in Fig. 10. Totaldynamic power results follow the trend observed inresource usage given in Table 3. Recursive architectures,in particular DCT implementation, dissipate less dynamicpower (i.e., 25% compared to radix-2 implementation). Dueto fixed properties of the FPGA fabric, static powerconsumption is almost same and the margin of differencefor dynamic power is not as high as expected amongdifferent architectures. However, for an ASIC implementa-tion, power savings would be much more pronounced. Ifthe timing requirements are relaxed, the HW/SW codesigncan be used for least power consumption. It offers 50% lesspower consumption against recursive DCT.

5 Conclusion

In this paper, a hardware efficient implementation of ultrasonicdetection algorithms is studied using an FPGA based smartsensor platform. Recursive filters and sparse transform oper-ations are proposed for reducing area and power whileachieving real-time operation. The synthesis results show thatall design corners are improved when compared against thetraditional FFT implementations and HW/SW codesign plat-forms. The recursive architectures presented here are scalable,power efficient and especially well-suited for distributed sensorapplications such as structural health monitoring where smartand sustainable ultrasonic sensors are required.

References

1. Sinha, S. K., Schokker, A. J., & Iyer, S. R. (2003). Non-contactultrasonic imaging of post tensioned bridges to investigate corrosionand void status. IEEE Proceedings of Sensors, 1, 487–492.

2. Mori, H., Oshima, T., Mikami, S., Honma, M., & Funatsu, M.(1994). “Effect of individual decision of bridge expert on totalevaluation of bridge integrity”. Journal of Constructional Steel, 2.

3. Chassignole, B., Villard, D., Dubuget, M., Baboux, J. C., & ElGuerjouma, R. (2000). Characterization of austenitic stainlesssteel welds for ultrasonic NDT. Review of Progress in QNDE, 20,1325–1332.

4. Halkjaer, S., Sorensen, M. P., & Kristensen, W. D. (2000). Thepropagation of ultrasound in a austenitic weld. Ultrasonics, 38,256–261.

5. Carino, N. J., Sansalone, M., & Hsu, N. H. (1986). “Flawdetection in concrete by frequency spectrum analysis of impact-echo waveforms”. International Advances in NondestructiveTesting, 12.

6. Saniie, J., Nagle, D., & Donohue, K. (1991). Analysis of orderstatistic filters applied to ultrasonic flaw detection using split-spectrum processing. IEEE Transactions on Ferroelectrics andFrequency Control, 38(2), 133–140.

7. Lu, Y., Oruklu, E., & Saniie, J. (2008). Fast chirplet transformwith FPGA-based implementation. IEEE Signal ProcessingLetters, 15(1), 577–580.

8. Jung, S., & Kim, S. S. (2007). Hardware implementation of a real-time neural network controller with a DSP and an FPGA fornonlinear systems. IEEE Transactions on Industrial Electronics,54(1), 265–271.

9. Rodriguez-Andina, J. J., Moure, M. J., & Valdes, M. D. (2007).Features, design, tools, and application domains of FPGAs. IEEETransactions on Industrial Electronics, 54, 1810–1823.

10. Hong Hu, C., Zhou, Q., & Shung, K. (2008). Design andimplementation of high frequency ultrasound pulsed-wave Dopplerusing FPGA. IEEE Transactions on Ultrasonics, Ferroelectrics andFrequency Control, 55(9), 2109–2111.

11. Hernandez, A., Urena, J., Hernanz, D., Garcia, J. J., Mazo, M.,Derutin, J. P., et al. (2003). Real-time implementation of anefficient Golay correlator (EGC) applied to ultrasonic sensorialsystems. Microprocessors and Microsystems, 27(8), 397–406.

12. Saniie, J., & Nagle, D. (1992). Analysis of order statistic CFARthreshold estimators for improved ultrasonic flaw detection. IEEETransactions on Ultrasonics, Ferroelectrics and FrequencyControl, 35(5), 618–630.

13. Weber, J., Oruklu, E., & Saniie, J. (2011). FPGA-based config-urable frequency diverse ultrasonic target detection system. IEEETransactions on Industrial Electronics, 58(3), 871–879.

14. Xilinx LogiCORE IP Fast Fourier Transform (FFT), ProductSpecification, DS260, June 2009. Available at: http://www.xilinx.com/support/documentation/ip_documentation/xfft_ds260.pdf.

15. Beck, R., Dempster, A. G., & Kale, I. (2001). Finite-precisionGoertzel filters used for signal tone detection. IEEE Transactionson Circuits and Systems-II: Analog and Digital Signal Processing,48(7), 691–700.

16. Hwang, J.-K., & Li, Y.-P. (2010). Efficient recursive IDFT schemefor complex-valued signals in tap-selective maximum-likelihoodchannel estimation. Journal of Signal Processing Systems, 60(1),71–80.

17. Oruklu, E.,Weber, J., & Saniie, J. (2008). “Recursive filters for subbanddecomposition algorithms in ultrasonic detection applications”, IEEEUltrasonics Symposium, pp. 1881–1884, November 2008.

18. Xilinx XtremeDSP for Virtex-4 FPGAs User Guide, UG073, May 15,2008. Available at http://www.xilinx.com/support/documentation/user_guides/ug073.pdf.

19. Aburdene, M. F., Zheng, J., & Kozick, R. J. (1995). Computationof discrete cosine transform using Clenshaw’s recurrence formula.IEEE Signal Processing Letters, 1(7), 101–102.

20. Chen, C., Liu, B., Yang, J., & Wang, J. (2004). Efficient recursivestructures for forward and inverse discrete cosine. IEEE Trans-actions on Signal Processing, 52(9), 2665–2669.

376 J Sign Process Syst (2012) 68:367–377

Erdal Oruklu received his B.S. degree in Electronics and Commu-nications Engineering from Technical University of Istanbul in 1995and M.S. degree in Electrical Engineering from Bogazici University,Istanbul, Turkey in 1999. He received his Ph.D. degree in ComputerEngineering from Illinois Institute of Technology, Chicago, Illinois in2005. He is currently an Assistant Professor at Department ofElectrical and Computer Engineering in Illinois Institute of Technol-ogy where he is also the Director of VLSI and SoC ResearchLaboratory. Dr. Oruklu’s research interests are signal processinghardware, reconfigurable computing, advanced computer architec-tures, hardware/software co-design and embedded systems.

Joshua Weber received his B.S.E degree in Computer SystemsEngineering from Arizona State University in 2005 and M.S degree inComputer Engineering from Illinois Institute of Technology in 2008.

He is currently pursuing his Ph.D. at Illinois Institute of Technology.He is a member of the VLSI and SOC Research Laboratory. Mr.Weber's research interests are in embedded systems, reconfigurablecomputing, hardware/software co-design and digital logic design withFPGAs.

Jafar Saniie received his B.S. degree in electrical engineeringfrom the University of Maryland in 1974. He received his M.S.degree in biomedical engineering in 1977 from Case WesternReserve University, Cleveland, OH, and his Ph.D. degree inelectrical engineering in 1981 from Purdue University, WestLafayette, IN. In 1981 Dr. Saniie joined the Department ofApplied Physics, University of Helsinki, Finland, to conductresearch in photothermal and photoacoustic imaging. Since 1983he has been with the Department of Electrical and ComputerEngineering at Illinois Institute of Technology where he is aFilmer Professor, Associate Chair and Director of the EmbeddedComputing and Signal Processing (ECASP) Research Laboratory.Dr. Saniie’s research interests and activities are in ultrasonicsignal and image processing, statistical pattern recognition,estimation and detection, embedded digital systems, digital signalprocessing with field programmable gate arrays, and ultrasonicnondestructive testing and imaging. Dr. Saniie is an IEEE Fellowfor his contributions to “Ultrasonic Signal Processing forDetection, Estimation and Imaging”.

J Sign Process Syst (2012) 68:367–377 377