ncvescom2011-1
TRANSCRIPT
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Design Methodology of Standard Cell Library for
Sub-micron TechnologyRohit Tripathi
#1, Nikita Gupta
#2, Shruti Shabbarwal
*3
#,*Electronics and Communication Engineering (Microelectronics and Embedded Technology) Department
Jaypee Institute of Information Technology University
Noida- 201307, U.P., [email protected]
Abstract Digital standard cell libraries are a key element inevery modern VLSI design flow. The use of standard celllibraries offers shorter design time, induces fewer errors in the
design process, and is easier to maintain.This paper describes a novel design methodology to develop a
standard cell for sub-micron technology. The design flowdescribed in this paper is very systematic, easy to understand,time and area efficient. The novelty of this paper is an effort to
develop design methodology which is helping for novices. Thiscell library is based on ideas from Mississippi State libraries
designed and developed using Mentor Graphics design tool.
Keywords Modern VLSI design flow, standard cell libraries,MOSIS, Mentor Graphics design tool (IC-Flow), BSIM3v3, H-SPICE.
I. INTRODUCTIONThestandard-cells based design is one of the most prevalentfull custom masks set. The standard cell is also called polycell.
In this design style, all of the commonly used logic cells aredeveloped, characterized, and stored in a standard cell library.A typical library may contain a few hundred cells including
inverters, NAND gates, NOR gates, complex AOI (AND-OR-Inverter), OAI (OR-AND-Inverter) gates, D-latches, and flip-
flops.
In this paper we have adopted CMOS based logics, fordesigning low power and high speed standard cell library.
CMOS based logics are assembled from complementary pairsof p-type and n-type MOSFETs with minimum channel length.
II. DESIGN FLOWThe design flow hides as many details as possible by thecompany standards provided. We are focusing the detailed
steps of each design stage according to our design flow.Its principal stages are:
- Specification Circuit design Layout design Design
verification Characterization of cell circuit.The design flow is as shown in figure 1. The process of each
block of design flow methodology for our consideration is as
follows:
Figure 1: Standard cell library design flow
A) SPECIFICATIONRole of specification is to specify the functional requirements
for the design. Generally, the specifications of cell are:
Power dissipation Supply voltageDelay (Propagation delay, rise time and fall time)TemperatureNoise immunity
B) CELL DESIGNThe cell designed starts either using schematic or netlist entry.For designing the cell at this stage, first we determine width of
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p-mos (WP) and n-mos (Wn) according to the channel lengthwhich depend on the technology node. Value of WP andWnare determined by:
Fixing the switching point equal to the VDD/2 andanalysed the ratio between WP and Wn through the
general equation which is given below:
n
p
ptDDn
p
nt
th
K
K
VVK
KV
V
1
)( ,,
Where VDD Supply VoltageVt,n Threshold voltage of NMOS
Vt,p Threshold voltage of PMOS
Kn Gain factor of NMOS= oxnn
CL
W
Kp Gain factor of PMOS= oxpp
CL
W
Driving capability of the cell, i.e. the number offan-out that cell can drive. Fan-out depends uponthe load capacitance (CL) which is sum of all the
intrinsic capacitances and extrinsic capacitance
offered by the MOSFET. The capacitances wereanalytically calculated and verified with H-SPICE.
Figure 2, shows the schematic view of NAND gate usingDesign-Architect (Mentor Graphic design tool).
Figure2: Schematic view of NAND gate
C) LAYOUT DESIGNThe layout is performed to confirm the design geometry
constraints with the help of an error-free design rule checkaccording as we follow the MOSIS design rules for our cells.
The layout design rules for standard cell technique are
Signals are routed in poly-silicon perpendicular tothe power.
Power and ground rails traverse the cell at the topand bottom respectively.
To complete the logic gate, connections is made ofmetal1 and metal2, where metal1 routed
horizontally and metal2 vertically, respectively.
Then, the layout of cell is created using layout designed toolsaccording to thedeep sub-micron rules and Figure 3 shows the
layout of NAND gate using IC-station (Mentor Graphicdesign tool).
Table 1: Layout Development Rules
Cell Layout Setting Value
Cell Height 15
Cell Width Multiple of 5
Metal 1 Width 3 for all layers
Metal 2 Width 3 for all layers
Metal Offset 0 for all layers
Power/ Ground
Pins/ Rails
Multiple of 9 for VDD and
GND
Figure 3: Layout of NAND gate
D) DESIGN VERIFICATIONDesign verification is a greater importance for process design
which matches the layout and schematic of logic cell. In our
cell, we have made a comparison between the schematic andthe layout (LVS), from the extraction of corresponding netlists
directly.
E) CHARACTERIZATIONCharacterization of cells consists of capturing key parameters
of cells such as Transient and D.C. characteristics. It is
performed by extracting SPICE netlists from layout or
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schematic of cell and then simulating them with a SPICE
simulator using BSIM3v3 Model parameter. The simulation
result of NAND gate is shown in figure 4 and figure 5.
Table 2 shows transient characteristic of the NAND gate and
Table 3 shows D.C. characteristic of the NAND gate.
Figure 4: Transient-analysis of NAND gate
Figure 5: D.C. analysis of NAND gate
Table 2: Transient characteristics of NAND gate
Symbol Parameter Value UnittPLH /tPHL Propagation
delay3.82 ns
CL Loadcapacitance
6.82 pF
Table 3: D.C. characteristics of NAND gate
Symbol Parameter Value Unit
VIH High-levelInput voltage
2.94 V
VIL Low-level
Input voltage
1.74 V
VOH High-levelOutput voltage
5 V
VOL Low-levelOutput voltage
0 V
III.CONCLUSIONIC design is becoming more and more complex as the
technology shrinks. Design methodology based on standard
cell approach is thus required to inherit design within time tomarket. A novel design methodology presented in this papercovers all the aspects of circuit, layout and verification. The
approach is simple, easy to understand and adapt forsubmicron and deep submicron technology.
The work can be extended towards multiple input logic
gates. Moreover, basic combinational and sequential cells canalso be designed by following this approach.
ACKNOWLEDGMENT
The authors thank to Jaypee Institute of InformationTechnology (JIITU), Noida, for the laboratory and technical
support for entire project work.
REFERENCES
[1] Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic DigitalIntegrated CircuitsA Design Perspective (2nd Ed)
[2] R. Jacob Baker CMOS Circuit Design ,Layout, and Simulation(2 ndEd)
[3] J.B. Sullistyo and D.S. Ha, Development Standard Cells for TSMC0.25um Technology under MOSIS DEEP RULES, Department ofElectrical and Computer Engineering, Virginia Tech, Technical Report
VISC-2002-02, April 2002.
[4] S. Jennings, W. L. Tan and B. Reese, Standard Cell Library,Mississippi State University.
[5] J. Grad, J. Stine, A Standard Cell Library for Student Projects,Technical Report Illinois Institute of Technology 2002,
http://www.ece.iit.edu/~cad/scells
[6] MOSIS, http://www.mosis.org.