NexFET A New Power Device

Shuming Xu

Texas Instruments Incorporated, Power Stage BU, MS 4008, Bethlehem, PA 18015

Presenter: Sameer Pendharkar

Technology Development, TI Dallas

Introduction

2

Device Structure

3

Operation Principal

ElectricPotential

Linear (V)

-0.5645

2.06

5.15

8.24

11.33

14.42

17.51

20.6

23.69

26.78

31.51

-1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4

-0.8

-0.4

00.4

0.8

1.2

1.6

22.4

2.8

ElectricPotential

Linear (V)

-0.5645

2.06

5.15

8.24

11.33

14.42

17.51

20.6

23.69

26.78

31.51

-1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4

-0.8

-0.4

00.4

0.8

1.2

1.6

22.4

2.8

4

Measured Gate Charge Curve of NexFET

5

Figure of Merit of NexFET vs. Trench DMOS

6

Power Loss vs. Frequency for

Trench DMOS and NexFET

7

Measured UIS Capabilities at

low and high Inductance

With low inductance,

high avalanche current

density of 20A/mm2 is

proven to be reliable

even at 125C. With

large inductance, over large inductance, over

1 J avalanche energy

is sustained for a

device of 4mm2 active

area at both room

temperature and 125C.

8

Waveforms of 12V Rated Device in

12V Input Voltage Application

NO CHANGE!

Before 1000-hrs Test

After 1000-hrs Test

9

DC Ron Measurement

1) The test is performed under DC condition.

The gate voltage is 4.5V.

2) The on-resistance increased from

1.352mOhm to 1.383mOhm after the

1000-hrs continuous running test, which is

2.3% increase.

3) The on-resistance shows a rising trend

when the continuous running time is

increased but increase insignificant

Voltage/Current curve

5

6

7

Before 1000-hrs Test After 1000-hrs Test

increased but increase insignificant

On Resistance vs. Time

1.28

1.3

1.32

1.34

1.36

1.38

1.4

0 24 72 240 1000

Time (hours)

Ron (mOhm)

1

2

3

4

1 1.5 2 2.5 3 3.5 4 4.5 5

Current(A)

Voltage(mV)

10

NexFET Technology Enables Both Drain Down and Source Down

Silicon Implementation

Source

Drain

• Same architecture allows similar

optimization paths for different

applications

• Drain down supports industry

standard footprint products for drop

in

Gen1

11

Source

Drain

• Source down enables stack-die

technology for higher efficiency and

smaller footprint

• Continuous technology

improvements offer both source

down and drain down customers to

access better performance/price with

the same footprints

Gen2

Control

FET

Input

Supply

LO

CINPUT

Switch

Node

CESR

CESL

RPCB

LDRAIN

LSOURCE

PWM

Driver

Stack-Die Reduces Package Parasitics

X

VIN / Cu ClipHigh Side Die

Sync

FET

ILCO

Load

Driver

LDRAIN

LSOURCE

CTOTAL

X

X

A significant step in reducing package parasitics.

Low Side Die GND / Cu Lead frameVSW / Cu Clip

12

Efficiency for Stacked Die Solution

86

87

88

89

90

91

92

93

94

Eff

icie

ncy

6 Phase 350kHz/Phase, Vdd 5V, 12VIN, VID - 1.2V

86

87

88

89

90

91

92

93

94

Eff

icie

ncy

6 Phase 350kHz/Phase, Vdd 5V, 12VIN, VID - 1.2V

13

Stack die solution delivers better performance

compared to a discrete solution

80

81

82

83

84

85

86

0 20 40 60 80 100 120

Eff

icie

ncy

Output Current (A)

CSD86350Q5D

Infineon Optimos5

CSD86350Q5D: HS Ron

& LS Ron < 5mohm

BSC050NE5, BSC010NE5

80

81

82

83

84

85

86

0 20 40 60 80 100 120

Eff

icie

ncy

Output Current (A)

CSD86350Q5D

Infineon Optimos5

CSD86350Q5D: HS Ron

& LS Ron < 5mohm

BSC050NE5, BSC010NE5

Summary

• Gen1 NexFET with lower FOM has been

introduced with drain down structure –

common configuration to existing vertical

discrete transistors

• Gen2 NexFET was introduced with source • Gen2 NexFET was introduced with source

down architecture, enabling stack die

configuration, which improves the efficiency,

and reduces size and package cost by

~50%

14