Noise Canceling in 1-D Data: Presentation #3

Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar

M2

Feb 2nd, 2005Size Estimates and Floorplan

Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

Project Manager: Bobby Colyer

Status

• Design proposal (Done)• Architecture proposal (Done)

– Behavioral Verilog simulation and test bench (Done)

• Size Estimates and Floorplan:– Structural Verilog (85%)– Revised transistor count (Done)– Floorplan (Done)

• To be done:– Schematics (15%)– Layout (5%)– Spice simulation

FP

A

w0 RO

M

FP

M

cos

FP

A

sin

FP

M

x2

FP

S

out

input

FP

MShifter

FP

M

FP

M

x1

error

mu

sumw0

FP

AF

PA

w1w2

Last week’s Block Diagram…

Revised Block Diagram

counter ROM

FPMultiplier

1

FPMultiplier

2

0

1

0

1

FPMultiplier

3

FPAdder

2

FPAdder

1

FPAdder

3

FPSubtrat

or

Adder

FPSubtrat

or

Convert

Convert

sin

cos

Regx1

Regx2

X1 wireRegw 1

W1 wire

X2 wireRegw 2

W2 wire

RegDatu

m

Rege

Regmu

1000000000

Datum-offset

RegInput

RegOut

Alternator

RegOf f s

et

0

1

0

1

0

1

0

1

Behavioral Simulation Output

Converted Values from Verilog Simulation:Input: 9.3125 Output: 9.8227359 Error: -0.5

Original C Code Simulation Results:Input: 9.325461 Output: 9.650836 Error: -0.325

**Difference in values due to 16-bit precision

Results Comparisons (Output)

Result Comparison (Error)

Structural Verilog Example: Floating Point Multiplier

Metal Directionality

M2

M4

M1

M3

Note:Depending on the complexity of the blocks, metal 1 and metal 2 may be used in both directions.

Local vs Global Interconnects

M2

M4

M1

M3

Note:

Vdd! & Ground: M1, M2Internal Routing: M1, M2

Clock & Reset: M3, M4Global Routing: M3, M4

Last week’s transistor count…

Part Transistors

16-bit FPA 5x500 = 2500

16-bit FPM 5x4000 = 20000

SRAM 500

ROM 1600

Registers 7x16x14 = 1568

Total ≈ 26168

A more accurate transistor count…

Part Transistors

16-bit FPA 5x1700 = 8500

16-bit FPM 3x2028 = 6084

Registers 10x16x14 = 2240

ROM 800

Converter 2x312 = 624

MUX/DEMUX 384

Adder 248

Counter 214

Alternator 64

Total ≈ 19146 + Misc ≈ 22000

Tentative Floorplan

Total Area:

~190,000 µ²

Area EstimatesPart Area (µ²)

16-bit FPA 5x140x110 = 77000

16-bit FPM 3x140x106 = 44520

16-bit Register 10x33x24 = 7920

ROM 43x180 = 7740

MUX/DEMUX 6x6.8x57 = 2325.6

Converter 2x20x40 = 1600

Counter 1004.5

Adder 28x35 = 980

Alternator 1x48 = 48

Total ≈ 143138 µ² + Misc ≈ 190000 µ²

Ratio/Density

• Aspect Ratio:– 415µ x 450µ = 1:1.08

• Block Porosity:– 22000 transistors/190000µ2

– 0.12 transistors/µ2

Last week’s challenges…

• Timing issues– Need to reuse hardware (multipliers)

(reduced from 5 to 3)– Clock skew (needs to be addressed)– Pipelined architecture to increase speed

and throughput (not needed)

• SRAM implementation (not needed)

• ROM implementation (completed)

• Transistor count is too high (reduced through hardware reuse and block optimization)

This week’s challenges…

• Still working on finalizing out designs for the floating point adders and multipliers– Wallace tree multiplier vs Array

multiplier• Wallace implementation is

smaller because it reuses the intermediate products of the individual bits

– Leading zero counter for normalizing block

Questions?