olympus soc advance research on floorplnning

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aDvanCeD FloorplannIng wIth olympus-soC For Fast anD relIable DesIgn Closure

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advanced Floorplanning with olympus-soC

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IntroDuCtIonAs the first step in a netlist-to-GDSII design flow, floorplanning presents the SoC designer with challenges and opportunities that affect the rest of the design flow, from block implementation, to chip assembly and top-level closure. It is particularly important in hierarchical floorplanning to quickly solve macro and IO pad placement, accurately estimate timing, power and area, create top-level power networks, and to efficiently partition the design. Floorplanning for large, complex ICs and SoCs depends on a high capacity solution that allows early timing estimations in a multi-mode, multi-corner (MCMM) context, supports all varieties of multi-Vdd flows, and offers wide flexibility between automatic and manual placements of all floorplan objects.

In this paper, we review floorplanning challenges and show how the Olympus-SoC implementation system comprehensively addresses all those challenges to produce the best floorplan in the shortest time.

about hIerarChICal DesIgn methoDologIes Floorplanning is an essential element of hierarchical design flows, especially for large SoC designs. A typical SoC could include hundreds of RAMs, soft and hard IP, analog blocks, and multiple power domains. A hierarchical methodology extends the capacity of design-automation tools, improves tool runtimes, and mitigates overall design risk by minimizing last minute design changes.

A hierarchical design flow typically includes three main stages:

Floorplanning block placement, pin assignment, design partitioning, time budgeting, power and clock planning

Block implementation placement, clock tree synthesis (CTS), routing, optimization

Chip assembly block instantiation, top-level glue logic optimization, top-level CTS/routing, global wire buffering, power and clock routing, etc.

The decisions made during floorplanning about the location of pins, pads, blocks, and partitions, as well as the overall power plan, carry though and impact the rest of the implementation. Floorplanning allows designers to perform what-if analysis of critical design metrics such as performance, timing, power, and area when there is more flexibility in the layout. Estimations are shared, and floorplanning modifications are often done iteratively between the package or board designers, the chip-level designer, and the block-level engineers.

The outcome of the floorplanning stage is a completed arrangement of macros and IO pads, a power plan, and partitioned blocks that can then be implemented in parallel. After the block implementations are complete, everything is reassembled for top-level routing and optimization. This is where errors from poor floorplanning and block implementation are revealed, which leads to unnecessary iterations, late-cycle unpredictability, and missed market opportunities.

To minimize the impact of surprises in chip assembly, design teams need floorplanning, block implementation, and chip assembly tools that accommodate small changes without disrupting the design flow. The ability to efficiently incorporate small ECOs (engineering change orders) between the SoC-level and block level greatly reduce the risks associated with hierarchical flows, and shorten the time to design closure. We will elaborate more on the ECO process later in this paper.



FloorplannIng ChallengesEach design project has different challenges and goals, but there are some issues that commonly arise for physical design teams.

baD Io paD plaCement

A common situation during floorplanning is the lack of well defined IO constraints from the board or package teams. With no guidance on IO placement, the order and location of IO pads can be suboptimal for package-level requirements, and for chip level timing closure (Figure 1). The true impact of IO pad locations is usually obscure until more detailed placement and routing is complete, at which point designers must iterate back to floorplanning to fix the IO pad locations manually, then perform placement and routing again. These time-consuming iterations can add unacceptable risk to design schedules.

tIme-ConsumIng anD suboptImal maCro plaCement

Achieving optimal macro placement can be a significant challenge, particularly for SoCs with hundreds of cores, memories, and 3rd party IP. In years past, macro placement was a purely manual task. Today, designers must rely on floorplanning software for a quick, automated initial placement before manual refinement. Tools typically cluster macros based on wire length, but there may be other metrics to consider, such as critical path timing, power domains, congestion, and minimization of narrow channels between blocks. These are all factors that traditionally are addressed through manual refinement of the seed floorplan. The challenge lies in the difficulty of that task. On a practical level, designers need better seed placement, and a powerful macro editing capability that can assist in spacing and aligning groups of macros.

InaDequate regIon shapIng, partItIonIng, anD pIn assIgnment

In hierarchical flows, floorplans are partitioned into functional groups that constrain physical placement of standard cells and macros. The grouping criteria can be based on clock generation logic, hierarchical implementation boundaries, or voltage domains (multi-Vdd).

Designers need a deep knowledge of the IC, but they also need the floorplanning tool to be flexible enough to handle different use models and shapes (rectangular or rectilinear) for regions, while always respecting the logical hierarchy of the input netlist. Challenges in floorplanning for multi-Vdd designs lie in defining the voltage domains,

Figure 1. Sub-optimal IO placements can lead to long paths over macros. In the design shown, the IOs should be placed on the bottom left side to have better access to the logic pins. Changing the IO placements can be tedious, particularly if the problem is not discovered until later in the design flow.



creating multiple power grids, and in inserting the special cells such as switches, level shifters, retention registers, and always-on buffers. Poorly shaped regions and broken logical hierarchy contribute to delayed schedules and suboptimal timing, power, and area.

Once the regions are determined, the region/partition pins are assigned. The challenge is to create pin placements that satisfy any number of design criteria, but most importantly the timing requirements between blocks for all corner/mode scenarios. Typically, pin assignments are based on wire length only, as determined by Steiner-based estimations. Poor pin assignments can wreak havoc on inter-partition timing paths, and lead to costly ECOs between the block level and chip level late in the design cycle.

InaCCurate tImIng anD power estImatIons

Getting accurate estimations of timing, power, and area as quickly as possible is the goal of the floorplanning/prototyping stage. The timing analysis does not need to be sign-off accurate, but it should include as many corner cases as is feasible, and account for manufacturing variability. For example, if the timing signoff includes a dozen mode/corner combinations, the floorplanning timing estimations are needed for all the timing scenarios, and not just worst case and best case.

Power estimations at this stage need to correlate with more detailed analysis later in the flow. Inaccurate power estimates can allow errors in the power plans to derail block and top-level closure. Multi-Vdd designs also introduce additional power meshes, so the floorplanner must be capable of creating and connecting multiple power domains.

laCk oF tool CapaCIty, FlexIble use moDels, anD eCos

Design data sets are becoming ever larger, and EDA tool capacity hasnt been able to keep up. Capacity and runtimes are now interfering with design schedules for SoCs that can have hundreds of RAMs, 200 million gates, multiple modes, multiple corners, and many power islands. For the larger designs, floorplanning is often the only opportunity to view the entire design in a flat (vs. hierarchical) representation. This is essential to obtaining good early estimations of design constraints by being able to run global routing, extraction, and analysis.

While it is tempting to believe that the block implementations will advance independently of one another, the reality is that implementation requires at least some iterations and feedback loops at the chip-level, and there will probably be interactions among blocks as well. When the blocks can only be represented with abstractions at the top-level, optimizations are limited to top-level logic. This limitation usually occurs because a complete full-chip flat representation exceeds the data capacity of most tools.

Changes based on block-level work, such as modifications to block placement, incremental re-assignment of block pin locations, power routing, or block timing and power budgets, are usually difficult to incorporate at the chip-level. Without flexibility in use models and a robust engineering change order (ECO) capability, designers can be stuck with time-consuming and non-convergent iterations between levels of physical and logical hierarchy. This is particularly frustrating when faced with frequent file transfers between different point tools in the design flow.



the olympus-soC FloorplannIng solutIonTo complete floorplanning faster and with better quality, Olympus-SoC includes the following tool capabilities:

Flexible IO pad placement strategies

Automatic and assisted macro placement and alignment

Automatic region shaping, partitioning, and timing-driven pin assignment

Native multi-corner multi-mode (MCMM) timing and signal integrity analysis

Full UPF support and robust power planning for multi-Vdd designs

Fast and reliable chip assembly support

Highest tool capacity, compact memory footprint, and an intuitive, easy to use GUI

FlexIble, hIgh-qualIty Io paD plaCementOlympus-SoC has very flexible use models for IO pad placement. Olympus-SoC can implement a design with or without a pad ring or pin placement file from the package designer. In the absence of external IO pad constraints, users can perform quick full-chip, timing-driven global placement and global routing, to get the best logic clustering and timing estimations to meet design metrics, then assign the IO pads based on that. This is a quick way to get very fast feedback regarding the routability and timing of the design. A congestion map helps identify hot spots that can be fixed through further what-if analysis loops.

Olympus-SoC also supports initial IO pad placement, followed by quick iterations between prototype macro placement and IO pad refinement. Refinement can be done through automatic, iterative re-placements, or through manually specifying constraints through the intuitive graphical user interface.

Whether the IOs are placed before or after the standard cells and macros, designers must be able to easily add and edit IO constraints to configure the side and order for the pads, and the layer and pitch for the pins. Olympus-SoC provides the IO Constraint Editor, shown in Figure 2, which displays IOs graphically and allows the user to assign sides, orders, layers, and pitches for the IO pins. Olympus-SoC can also infer, or derive, constraints based on an existing IO pad (and partition pin) placement, providing a useful starting place for further constraint editing.

Figure 2. The IO Constraints Editor facilitates pin constraint editing with cross-probing, robust filtering, and flylines. IO ports can be automatically aligned, and Olympus-SoC can infer constraints based on current placements.



As the floorplan, or even the block implementation, progresses and more detailed information is available, designers often find that the pin assignments need adjustment. Rather than re-assigning all pins, Olympus-SoC supports incremental pin assignment. Designers can specify which pins to re-assign, while keeping the rest of the pins fixed.

After placing the IO signal pins, Olympus-SoC will place the IO filler cells and power/ground pads. The IO placements can then be written out in industry-standard formats for use by board, package, or top-level SoC planning purposes. This link between board, package, and SoC becomes more important at 45 nm and below because of tighter design constraints and more pad-limited designs.

automatIC maCro plaCement anD maCro reFInementOlympus-SoC automatically creates a seed macro placement that can be manually refined with the help of Olympus-SoCs macro alignment and spacing capabilities. Macros can be individually aligned with the region or other macros, or aligned and spaced as a group with the automated Matrix Assist. Multiple macros can easily be aligned on a single edge or on multiple edges in an array with specified spacing between each macro, as shown in Figure 3.

Figure 3. The large macros in this screen capture have already been aligned with just a few button clicks. Using the Matrix align and space capability, all the smaller macros can be instantly arranged into a matrix with specified spacing between them. Multiple macros can also be grouped and moved as a single object.

automatIC regIon shapIng, partItIonIng, anD pIn assIgnmentRegions constrain the physical placement of standard cells to particular areas. This is typically used to address timing and routability concerns, such as grouping clock generation logic, defining hierarchical implementation boundaries, and defining voltage domain boundaries. The Olympus-SoC floorplanner supports many different use models for region creation. Regions can be defined as hard or soft constraints for placement only, or for optimization and clock tree synthesis (CTS). Regions can be automatically created based on the designs logical



hierarchy, or manually shaped, facilitated by colorized logic groupings. Regions can also be manually moved, resized, reshaped, or split into smaller regions. Egresses (bumps) and ingresses (notches) are created by adding or deleting rectangles from the existing regions.

As regions are hardened into partitions, Olympus-SoCs fast timing-driven prototype placement and global routing predicts where routes will cross the partition boundaries, and assigns partition pins based on that. The placement and routing engines support multi-mode, multi-corner constraints, so pin assignments are optimized based on timing and wire length that will satisfy all mode/corner scenarios.

multI-moDe, multI-Corner tImIng analysIs anD optImIzatIonOlympus-SoC concurrently analyzes and optimizes for all design metrics across any number of mode/corner scenarios. Timing information for every circuit node is stored in a data structure called the timing graph, which is the fundamental component of any place-and-route software architecture. The core innovation in MCMM is an extremely concise vector-based timing graph structure that simultaneously captures timing information for an unlimited number of mode/corner combinations. Rather than merging timing files or performing sequential timing analysis for multiple scenarios, the Olympus-SoC system creates multiple timing graphs, and then stores them as a single representation. This enables all the timing scenarios to be accurately represented without added memory or runtime costs.

MCMM timing analysis performed during floorplaning produces better IO pad and block pin assignments, and generates more accurate timing estimations for paths that span blocks.

Complete support For multI-vDD DesIgnsOlympus-SoC fully supports Unified Power Format (UPF) directives. Power islands are created in the same manner as any partition, and Olympus-SoC automatically inserts and connects special cells such as switches, level shifters, always-on buffers, and retention registers. Olympus-SoC has a multi-Vdd browser that supports cross-probing with the layout window to facilitate analysis and debugging of the design, as shown in Figure 4.

Figure 4. With the Multi-Voltage browser, the power domains and the cells assigned to each domain can be easily navigated. Items selected in the browser are highlighted in the chip view for cross-probing operation.



Regardless of the number of voltage domains, Olympus-SoC can create and connect all power routing at block or top level. Rings, stripes, and vias are automatically generated based on user configuration and connected to follow pins. Users can manually choose which vias to use or let Olympus-SoC determine the correct vias, either from among defined LEF vias or by generating them using the default via generation rules in the LEF file. Users can also specify which kind of power connections to make: stripe-to-stripe, stripe-to-macro, and stripe-to-cell. Olympus-SoC has the ability to create multiple power networks for multi-vdd designs.

IntegrateD support For top-level optImIzatIon, ChIp assembly, anD eCosFor hierarchical designs, Olympus-SoC can maintain convergence between top and block levels during optimization at any stage of the design flow. If working with abstraction models for the partitions, some optimizations will require ECO iterations. One way Olympus-SoC improves the ECO flow is to allow users to mix different levels of hierarchy at the top-level. Users can choose to view some blocks flat, others as black-box models, and still others as traditional interface logic models ILMs. This conserves capacity, runtime, and resources.

For even more top-level flexibility, Olympus-SoC generates ILMs that contain the physical placement and routing information that is relevant to top-level optimizations. This allows for Olympus-SoC to access block-level resources when optimizing inter-block routes. For example, to fix an excessively long route between two blocks, Olympus-SoC can make adjustments to the blocks pin placements, iteratively re-routing the wires and using different layers if needed (Figure 5). This top-level wire straightening is automated and iterative, and the changes made to top-and block level logic are completely convergent.

Another option available in Olympus-SoC to stretch capacity and save on runtime is to selectively turn off some levels of logical hierarchy with regard to timing. That allows Olympus-SoC to access the relevant physical information, but not spend computational resources on extraction and timing of those modules. Olympus-SoC is unique in the level of flexibility offered in both flat and hierarchical flows. Olympus-SoC also offers capabilities like SyncOpt, which automatically updates all occurrences of a block when a change is made to any of its instances.

Many IC flows also call for some amount of automatic or manual detail routing and wire editing of critical nets. For manual editing, the Olympus-SoC wire editor provides a robust and intuitive environment, supporting automatic preferred-layer routing, via creation, and non-adjacent layer wire creation.

Olympus-SoC also provides real-time, interactive DRC, giving instant feedback for all objects being manipulated, as illustrated in Figure 6.

80% wire length on M3-M5

Many short jogs and layer changes

Before Layer Promotion

90% wire length on top metal layers

After Layer Promotion

Short jogs eliminated

Figure 5. Layer promotion is a technique used by Olympus-SoC to reduce resistance in top-level routing.



CapaCIty, runtIme, eFFICIenCyOlympus-SoC has the data capacity to load and process designs with 400 million of more gates to provide faster floorplanning turn-around-time. The fully multithreaded timing engine reduces analysis time, and the easy-to-use GUI greatly improves the efficiency of macro placement, IO pin constraints editing, wire editing, and power domain analysis. All engines within Olympus-SoC operate on a common database, so no time or memory are wasted in file transfers. Olympus-SoC supports all the standard inputs such as LEF, DEF, and Verilog, as well as UPF for power specifications.

ConClusIon Floorplanning is the foundation of a quality IC implementation. The decisions made regarding IO pad placement, macro placement, partitioning, pin assignment, and power planning ripple through the place-and-route flow. Designers need solutions that can handle extremely large data sets, design variability and complexity, in addition to enabling fast, high-quality floorplanning.

Olympus-SoC has a complete floorplanning solution with a flexible tool infrastructure and large capacity. It generates high-quality floorplans and accurate early estimations of design constraints based on MCMM timing. Flexible support for mixed-level hierarchy throughout the flow keeps ECOs to a minimum and maintains physical and logical convergences between top and block levels. Olympus-SoC is a complete, tapeout-proven, netlist-to-GDSII solution for very large, advanced-node SoCs.

Figure 6. Manual wire editing with interactive DRC checking gives instant feedback on common design rule violations as wires are drawn or moved.


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olympus soc advance research on floorplnning

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