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Operating System Approaches for

Dynamically Reconfigurable Hardware

Marco Platzner

Computer Engineering Group

University of Paderborn

platzner@upb.de

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Outline

� operating systems for reconfigurable hardware

� previous work ― XFORCES @ ETH Zurich

� planned work ― ReconOS @ University of Paderborn

� potential collaborations

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Operating Systems for Reconfigurables

� motivation

� increased productivity and portability

� predefined components, programming model

� utilization of dynamic and partial reconfiguration

� for dynamic and real-time task sets

task 1

task 2

task N

operating systemservices

TN

FPGA

T2

� services� task management

� load/remove/preempt/resume

� communication, synchronization

� scheduling

� resource management� logic array, I/O pins, …

� placement

� time management

� user managementT1

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Application Domains for Reconfigurable OS

custom computing

server

network subsystems(packet processors)

wearable computing

mobile systems

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Task Models

Ethernet MAC / minimal IP Stack

� structural qualities� area, shape

� relocatability

� transformability, spatial critical sections (eg carry-chains)

� timing qualities� execution cycles

� clock range

� timing critical sections(eg I/O protocols)

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Resource Models

T1 T3 T2 Tn

2D

1D

variable block-partitioned

b1 b3

b2 b4

b5

b6

b7

b1 b2 b3b4b5b6

T2

T3

Tn

T1 T1

T2

T3

Tn

T4

T1T3

Tn

� issues / challenges

� placement, scheduling

� device utilization

� communication

� reconfiguration

� feasibility on current FPGAsT2

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X-FORCES project @ ETH Zurich

� 2000-2004, funded by Swiss National Science Foundation

� online placement and scheduling

� 2D variable resource model

� fast online placement [WSP03]

� task footprint transforms [WP02]

� scheduling & placement of real-time tasks [SWPT03]

� 2D/1D variable resource model

� scheduling real-time tasks [SWP03], [SWP04]

� 1D block-partitioned model

� preemptive/non-preemptive scheduling,

modeling of the configuration/readback port [WP03a]

� os concepts, prototypes, and applications

� prototype partial reconfiguration, audio decoder [DPP02]

� application to wearable computing [PEW+03], [PEW+02]

� concepts and prototypes [WP03a], [WNP04], [WP04]

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Prototyping Environment I

� XESS XSV-800 board

� Xilinx Virtex XCV-800

� modified to allow for partial reconfiguration

� development tools

� Xilinx ISE

� Xilinx Modular Design

� MS Visual C++

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Networked Embedded System

DA

CDCDrv

LEDs

RS232

audio-

codec

PHY

PktDDEx

EthTX

LEDDrv

T

TT1

T5

T2

T4

T6T7

T3 T10

T9

Q1

Q3

Q2

Q5Q6

Q4

CRY(AES-1)

SW1

SW2

SW3

T8

PatG(a/b)

SW4

UDPPSnd

ARPICMPTCP

T

T

WavGen

T11

Q7

UART

EthRX

H

Hosts

EthernetEthernet

IP v4IP v4

R-FPGA

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Device Floorplan

LEDs

RS232

audio-

codec

SW1

SW2

SW3

SW4

EthernetEthernet

IP v4IP v4

H

S

EthRX

PHY

CDCDrv

DA

UART

LEDDrv

Hosts

OS Frames

Task Communication Bus

taskslot #1

taskslot #0

Standard

Task-Interface

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Floorplan Snapshot

PktD/DEx task

(in slot #0)AES-1 task

(in slot #1)

Ethernet

driver

FIFO

buffers

FIFO

buffers

codec

driver

UART

LEDdriver

FIFO

buffersOS-

bridge

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Prototyping Environment II

� XF-board (own development) � standalone system with MicroBlaze soft CPU core

� 2 Xilinx Virtex II, rich in I/O and memory

� fast partial reconfiguration

� development tools� Xilinx ISE, Modular Design, EDK

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Planned Work: ReconOS @ University of Paderborn

� current status

� quite some work done on execution models and related problems, egplacement, scheduling, on-chip networks, reconfiguration techniques

� first prototypes prove feasibility of hardware multitasking

� missing

� programming models for reconfigurable applications (coarse-grained functions)

� project goal: "From Programming To Execution Models"

� investigate and develop a programming model

� investigate and develop suitable execution models

� automatize and customize the generation of the runtime system

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ReconOS – Programming Model

� objects and object interactions must be...

� simple enough to allow for an efficient mapping to dynamically reconfigurable hardware

� expressive enough to capture realistic applications

→ follow programming models of standard embedded operating systems

A

C

B

task

semaphoretimer

task

task

buffer

queue

queue

� main work areas

� define task objects and services for task communication and synchronization

� investigate techniques for task-initiated preemption

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ReconOS – Execution Model

� the runtime system must be...

� simple enough to allow for an implementation on current FPGAs

� sophisticated enough to demonstrate benefits of dynamic reconfiguration

→ leverage a 1D (somewhat) variable area model

� main work areas

� partitioning of the runtime system between hardware and software

� dynamic hardware/software mapping of tasks

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ReconOS – Runtime System Generation

� automated generation of the runtime system

application

T1

T2

T2 T5T3

T4

T1

T1

T5

TaskWrapper 1(VHDL)

VHDL

VHDL

OS-Frame(VHDL)

*.pbit

*.pbit

OS-Frame.bit

TaskWrapper 5(VHDL)

system architecture

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ReconOS – Runtime System Generation

� customization of the runtime system

application

T1

T2

T2 T5T3

T4

T1

T1

T5

TaskWrapper 1(VHDL)

VHDL

VHDL

*.pbit

*.pbitTaskWrapper 5(VHDL)

used OS objects

S

T

system architecture

OS-Frame(VHDL)

OS-Frame.bit

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Potential Collaborations

A

C

B

task

semaphoretimer

task

task

buffer

queue

queue

� applications: eg networked embedded systems

� programming models:everything that can be efficientlymapped to cooperating hw/sw tasks

� execution models:runtime systems, online resource

management, architectures

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Relevant Own Publications (1)

[SWP04] C. Steiger, H. Walder, and M. Platzner. Operating Systems for Reconfigurable Embedded Platforms: Online

Scheduling of Real-time Tasks. IEEE Transactions on Computers. 53(11):1392-1407, November 2004.

[WP04]H. Walder and M. Platzner. A Runtime Environment for Reconfigurable Operating Systems. In Proceedings

Field-Programmable Logic and Applications (FPL), 2004. Springer.

[WNP04]H. Walder, S. Nobs and M. Platzner. XF-BOARD: A Prototyping Platform for Reconfigurable Hardware OperatingSystems. In Proceedings International Conference on Engineering of Reconfigurable Systems and Algorithms

(ERSA), 2004. CSREA Press.

[PEW+03]C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, and G. Tröster. The Case for Reconfigurable

Hardware in Wearable Computing. Personal and Ubiquitous Computing. pages 299-308, October 2003.

Springer-Verlag London.

[SWPT03]C. Steiger, H. Walder, M. Platzner, and L. Thiele. Online Scheduling and Placement of Real-time Tasks to PartiallyReconfigurable Devices In Proceedings IEEE International Real-Time Systems Symposium (RTSS), December

2003. IEEE CS Press.

[SWP03]C. Steiger, H. Walder, and M. Platzner. Heuristics for Online Scheduling Real-time Tasks to Partially

Reconfigurable Devices. In Proceedings International Conference on Field Programmable Logic and Applications

(FPL), September 2003. Springer. (nominated for the Best Paper Award)

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Relevant Own Publications (2)

[WP03b]H. Walder and M. Platzner. Reconfigurable Hardware Operating Systems: From Design Concepts to

Realizations. In Proceedings International Conference on Engineering of Reconfigurable Systems and

Algorithms (ERSA), June 2003. CSREA Press.

[WSP03]H. Walder, C. Steiger, and M. Platzner. Fast Online Task Placement on FPGAs: Free Space Partitioning and

2D-Hashing. In Proceedings of the Reconfigurable Architectures Workshop (RAW'03), Nice, France, April 2003.

IEEE CS Press.

[WP03a]H. Walder and M. Platzner. Online Scheduling for Block-partitioned Reconfigurable Devices. In Proceedings

Design Automation & Test in Europe (DATE'03), March 2003. IEEE CS Press.

[PEW+02]C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele. Reconfigurable Hardware in Wearable

Computing Nodes. In Proceedings International Symposium on Wearable Computers (ISWC'02), October 2002.

IEEE CS Press.

[DPP02]M. Dyer, C. Plessl, and M. Platzner. Partially Reconfigurable Cores for Xilinx Virtex. In Proceedings International

Conference on Field Programmable Logic and Application (FPL'02), September 2002. Springer.

[WP02]H. Walder and M. Platzner. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.

In Proceedings International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'02),

June 2002. CSREA Press.

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Outline →→→→ Summary

� operating systems for reconfigurable hardware

� previous work ― XFORCES @ ETH Zurich

� planned work ― ReconOS @ University of Paderborn

� potential collaborations