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Design-for-Test Methodologies

Mani Soma

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Acknowledgements

Some materials from various sourcesDr. Phil Nigh, IBM

“Principles of Testing Electronic Systems” byS. Mourad & Y. Zorian“Essentials of Electronic Testing” by M.L.Bushnell and V.D. Agrawal

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Outline

MotivationAd-hoc techniquesStructured techniquesConclusion

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Motivation

Reduce test generation difficulty, especiallyfor sequential circuitsReduce test costShorten test development timeFacilitate testing at system level

Chips to boards to systems

Improve overall product quality

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Ad-hoc DFT Techniques

Initialization facilitiesTest point insertion and multiplexersPartitioning large circuits into smallertestable blocksConstant-testability designs (C-testabledesigns)

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Initialization methods

Initialization of sequential circuitsat power-up

before test application to get to a known initialstateafter an operation to return to a known initialstate

reduce cost of long homing sequences

Asynchronous Set, Clear, Reset, Preset,etc.

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Test point insertion

Usually for observationcritical signals

Control test point breaks signal pathmultiplexersadditional delays

Insert based onsome measures of observability andcontrollabilitydesigner s experience

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Test point examples

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Test point examples (3)

Add internal probe pointsissues in testing and probe card design

CPUCPU RAMRAM

Chip

Inputs Chip

Outputs

Data busData bus CHIPCHIP

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Test point examples (2)

CPUCPU RAMRAM

Chip

InputsChip

Outputs

Data busData bus CHIPCHIP

CPUCPU RAMRAM

Data busData bus CHIPCHIPextraextra

inputinput

extraextra

outputoutput

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Partitioning for test

Divide-and-conquerTest application to specific blocks

known available test setpseudo-exhaustive test set

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Partitioning with MUX

(a) Circui t wit h par titio ning

Subcircuit

G1

MU X

M

U

X Subcircuit

G2

M

U

X

MU XOrigin al ci rcuit

Subcircuit

G1

Subcircuit

G2

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Normal and test modes

(b) Nor mal mod e

Subcircuit

G1

MU X

M

U

XSubcircuit

G2

M

U

X

MU X

(c) Tes t mode for subc ircu it G1

Subcircuit

G1

MU X

M

U

X Subcircuit

G2

M

U

X

MU X

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Pseudo-exhaustive test

Subsystems can be tested exhaustivelyConcatenation of test vectors to testseveral subsystems concurrentlySometimes might need partitioning usingMUX

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Circuit example

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Test set construction

1111118

1110117

1111016

1110015

0011104

1110103

1111002

1110001

yxhgfedcbaTest (c,d,e): exhaustivetest

f: sensitizes pathh: propagates to y

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Test set construction (2)

(a,b): exhaustive test

use rows where h=1to sensitizeg propagates to xadd two tests (9,10)to form (f,h)exhaustive test

01000010

0001109

11111111118

11111011017

11111101106

10101001005

0011104

1110103

1111002

1110001

yxhgfedcbaTest

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Test set construction (3)

Modify tests (4,9) toform (g,h) exhaustivetest

Total of 10 tests (vs.64 exhaustive tests)

01000010

00010110109

11111111118

11111011017

11111101106

10101001005

00001110004

1110103

1111002

1110001

yxhgfedcbaTest

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C-testable designs

Iterative Logic Arrays (ILA)structured designs using arrays of identicalcells

adders, multipliers, etc.RAMFPGAbit-slice processors

Array test set based on cell test setC-testable: array test set size is independent ofnumber of cells in array

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ILA structures

1-dimensional

i-1 i i+1

2-dimensional

i,j

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Full adder example

i+1 i i-1

Xi Yi

Co Ci

Si

6 tests with identical carryvalues2 alternate-cell tests withopposite carry values

total = 8 tests

11111

01011

01101

10001

01110

10010

10100

00000

SiCoCiYiXi

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Structured DFT Techniques

Scan dominates digital DFTClassical scan

Boundary scan

IDDQ design guidelinesBuilt-in Self Test (BIST) techniques

in other lectures

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Scan concept

Combinational circuit

X1

X2X3

Z1

Z2

Z3

CLK

D D DQ Q Q

X1

X2

X3

Combinational circuit

CLK

D D DQ Q

Q

SE

SISO

Z1

Z2Z3

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LSSD system diagram

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Scan latch design example

D: normal data in

CK: system clock

Q: normal latch output

SDI: scan data in

SCKA, SCKB: scan clocks

SDO: scan data out

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Typical scan chains

CC

HH

AA

II

NN

11

CC

HH

AA

II

NN

22

CC

HH

AA

II

NN

66

CC

HH

AA

II

NN

77

CC

HH

AA

II

NN

33

CC

HH

AA

II

NN

55

CC

HH

AA

II

NN

44

SO1SO1 SO2SO2 SO4SO4SO3SO3 SO5SO5 SO6SO6 SO7SO7

primaryprimaryinputsinputs

primaryprimaryoutputsoutputs

SI1SI1 SI2SI2 SI3SI3 SI5SI5 SI6SI6 SI7SI7SI4SI4

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Scan testing

Configure DFF into shift register and testGenerate tests for combinational logicApply tests using scan DFF to provide I/Oto combinational logic

easier and faster justificationeasier and faster propagation

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Typical scan chain tests

Initialization

Flush 0 / Flush 1 patterns of all chains in parallelScan in 001100110011… and scan out samedata, all chains in parallelApply a test (loop for each test vector)

scan in test 1 (contents of D FF)

set up inputs (combinational logic inputs for test 1)

exercise system clock once

scan out contents of D FF

check scan outputs

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PO strobe

PI stim

PI-PO delay test with scan

C1 system

clock

C2 system/scan

clock

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PO strobe

C1 system

clock

C2 system/scan

clock

PI stim

L2-PO delay test with scan

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PO strobe

PI stim

L2-L1 delay test with scan

C1 system

clock

C2 system/scan

clock

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Scan design rules

All latches must be scannable (full-scan)Every latch must be on a scan path

There may be multiple scan paths

Non-overlapping clocks

No gating between clocksAll clocks must be primary inputsSDI and SDO must be primary I/O

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Scan design advantages

Testable sequential systemsTest scan path using DFF tests

Ease of testing remaining combinationallogic

Access to internal nodes via scan

Fast test generation (all combinational)Ease of delay testing of combinationalblocks

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Scan design advantages (2)

Complete controllability of all registersComplete observability of all registersCombinational logic test generationUse cheaper test systems

Additional diagnostic capability

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Scan design cost

More complex designarea: 2 - 15%

Additional delayPossible to minimize by clever designs

More I/O required (1-3 pins)Recover cost as part of system test facilities

Slow test (not at speed)Time to scan long paths seriallyLarger wiring parasitics

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ATPG Example: S5378

Original

2,781

179 0

0.0% 4,603

35/49 70.0%

70.9% 5,533 s

414 414

Full-scan

2,781

0 179

15.66% 4,603

214/228

99.1% 100.0%

5 s 585

105,662

Number of combinational gatesNumber of non-scan flip-flops (10 gates each)

Number of scan flip-flops (14 gates each)Gate overhead

Number of faultsPI/PO for ATPG

Fault coverageFault efficiency

CPU time on SUN Ultra II, 200MHz processorNumber of ATPG vectors

Scan sequence length

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Scan varieties

Full-scan: increasing usepartitioning issues in multiple scan chainsoptimal placement of DFF in scan chain

Partial-scanRandom-access scan

Individual latch addressableHigh overhead

Level-Sensitive Scan DesignNo races and timing problems

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Partial Scan ExampleCircuit: TLC, 355 gates, 21 flip-flops

Scan Max. cycle Depth* ATPG Fault sim. Fault ATPG Test seq.

flip-flops length CPU s CPU s cov. vectors length

0 4 14 1,247 61 89.01% 805 805

4 2 10 157 11 95.90% 247 1,249

9 1 5 32 4 99.20% 136 1,382

10 1 3 13 4 100.00% 112 1,256

21 0 0 2 2 100.00% 52 1,190

* Cyclic paths ignored

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Test Length StatisticsCircuit: TLC

200

100

00 50 100 150 200 250

Num

ber

of

fault

s

200

100

00 5 10 15 20 25

Num

ber

of

fault

s

200

100

00 5 10 15 20 25

Num

ber

of

fault

s

Without scan

9 scan flip-flops

10 scan flip-flops

Test

length

Test

length

Test

length

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Partial vs. Full Scan: S5378

Original

2,781

179

0

0.0%

4,603 35/49

70.0% 70.9%

5,533 s

414 414

Full-scan

2,781

0

179

15.66%

4,603214/228

99.1% 100.0%

5 s

585105,662

Number of combinational gates

Number of non-scan flip-flops (10 gates each)

Number of scan flip-flops (14 gates each)

Gate overheadNumber of faults

PI/PO for ATPGFault coverage

Fault efficiencyCPU time on SUN Ultra II

200MHz processorNumber of ATPG vectors

Scan sequence length

Partial-scan

2,781

149

30

2.63% 4,603

65/79 93.7%

99.5% 727 s

1,117

34,691

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Motivation for board test

High-density boards / Multichip Modules(MCM) not testable using bed-of-nailsBoard failure modes:

stuck-at faultsopenshorts

incorrect components

Lack of test access

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Bed-of-nails testing

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Boundary Scan standard

IEEE 1149.1JTAG (Joint Test Activity Group)

First release: 1990under revisions

Facilities to test for board failuresoptional instructions for internal IC testingusable in system-level tests

Many ICs now incorporate 1149.1

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Boundary Scan topology

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Boundary Scan cell

At chip I/O onlyElectronic access to each chip pin

TDI

Update DR

TDO

Q

QSET

CLR

D

ClockDR

Mode

1

0

Q

QSET

CLR

D

0

1

Data_In

Q

QSET

CLR

D

Q

QSET

CLR

D1

2

ShiftDR

Data_Out

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Test access port (TAP)

Device ID. Register

Bypass Register

Instruction Register (IR)

TDI

TDO

Bo

un

dar

y

Scan

Reg

isters

Controller

TDM TDK

TMS

TCKTDITDO

optionalTRST(reset)

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TAP registers

Bypass registerremoves chip from boundary scan path

faster test application

Instruction registermandatory instruction: Bypass, Extest, Sample/ Preload

optional instruction: Intest, Idcode, RunBist,Clamp, HighZ

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TAP controller

Simple state machine

Load instructionLoad test dataExecute test

Unload (shift-out) testresultsInitialization

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Register operations

Instruction registersloaded serially for all ICs

captured in parallel to each IC

Data registers at chip pinsloaded serially, captured in parallel

test data and test results

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Instruction scan

TMS

TCK

Tes

t-L

ogic

-R

eset

Sele

ct-I

R--

Scan

Ru

n-T

est/

Idle

Sele

ct-D

R--

Scan

Cap

ture

-IR

Shif

t-IR

Exi

t1-I

R

Shif

t-IR

Pau

se-I

R

Exi

t2-I

R

Exi

t1-I

R

Up

dat

e-IR

Ru

n-T

est/

IdleController

State

Data inputto IR

TDI

IR shift-register

Paralleloutput of IR

Data inputto TDR

TDR shift-register

Paralleloutput of

TDR

Registerselected

TDO enable

TDO

Inactive Active Inactive Active Inactive

Instruction register

Old data

NewInstruction

IDCODE

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Data scan

TMS

TCK

Ru

n-T

est/

Idle

Shif

t-D

R

Sele

ct-D

R-

Scan

Cap

ture

-DR

Exi

t1-D

R

Pau

se-D

R

Exi

t2-D

R

Up

dat

e-D

R

Shif

t-D

R

Exi

t1-D

R

Ru

n-T

est/

Idle

Sele

ct-D

R-

Scan

Tes

t-L

ogic

-R

eset

ControllerState

Data inputto IR

TDI

IR shift-register

Paralleloutput of IR

Data inputto TDR

TDR shift-register

Paralleloutput of

TDR

InstructionRegister

TDO enable

TDO

Inactive Active Inactive Active Inactive

Test data register

New data

IDCODEInstruction

Sele

ct-I

R-

Scan

Old data

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EXTEST example (1)

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EXTEST example (2)

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Boundary Scan design tools

Boundary Scan Design LanguageBSDL

facilitates incorporation and checking of correctBS designs

Automatic synthesis of TAP controllerTools and automatic test generationavailable in most systems

supported by numerous testers

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Boundary Scan tradeoffs

Additional pins (at least 4)Additional delays (minimal)Additional power (minimal)Structured DFT technique for board test

extensible to internal IC test (privateinstructions and proprietary DFT methods)test access from system to IC pinscomputer-aided tools availableusable for debug and diagnosis

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IDDQ design guidelines

Structured DFT methodologyBuilt-in current sensor(BICS)

Circuit designsTest point selection: where to insert BICS

Fully static logic for low IDDQNo pull-ups, pull-downs, pass gatesNo internal drive conflictsNo floating nodes

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Built-In Current Sensors

AdvantagesIDDQ testing can be applied only for all non-analog circuitry onmixed-signal chips

Better low-current resolution (e.g. partition chip)

Much faster (e.g. four orders of magnitude)

Potential ApplicationsHigher quality chip testing

IDDQ testing at multiple levels of assembly

Circuit breaker & cheap chip test for wafer-level burn-in

Power-on, diagnostic or concurrent testing in system

Reconfigurable systems

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Built-In Current Testing

Designs have been experimentally verified (2001)Carnegie Mellon, Hewlett-Packard, Motorola,Japanese Universities, Auburn U, a few others

Speed: up to 20MHz

Low current resolution: <1uA

Area overhead: <1%

Circuit size: 2000 transistors

Apparently, not yet implemented in manufacturing

Long-term feasibility & effectiveness is not clear

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DFT examples

Add pins for observability/controllabilityAdd internal probe pointsLatch design with reset capabilityScan latch design (including level-sensitive scandesign)Boundary scan on signal IO pinsDesign for reduced pin count testingLayout modification for defect tolerance /avoidanceLogical design modification to defect tolerance /avoidance

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DFT examples (2)

Parity, error detection, error correctionBuilt-in self test of logicDesign for zero static currentInclusion of electrostatic discharge (ESD)diodes on all IO pinsMemory redundancy

Memory built-in self-test

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DFT rules of thumb

If possible, use full scan designUse JTAG 1149.1 boundary scan for openmarket partsImplement full IDDq testable designsAvoid logical redundancyFor sequential designs, try to avoid sequentialfeedback loops (e.g. large counters)For sequential designs, include reset operationon all latchesUse memory BIST for large memories

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DFT rules of thumb (2)

Include ESD protection diodesFor scan designs, minimize length oflongest scan chainUnderstand all testing requirements (e.g.board vs. MCM) when defining chip-leveltest strategies

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Conclusion

DFT is unavoidable at system levelBalance design and test tradeoffsStructured vs. ad-hoc DFTSystems-on-a-chip (SOC) DFT:

DFT per core (in core-based designs)test integration issues

core interface testmixed-signal DFT issues