Development of K- and Ka-band High-Power Amplifier GaN MMIC Fabrication Technology

K. Y. Osipov, S. A. Chevtchenko, R. Lossy, O. Bengtsson, P. Kurpas, N. Kemf, J. Würfl and G. Tränkle

Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik (FBH), Gustav-Kirchhoff-Str. 4, 12489 Berlin, Germany

e-mail: Konstantin.Osipov@fbh-berlin.de, Phone: +49 30 6392 2774, Fax: +49 30 6392 2685

Keywords: Ka-band, GaN HEMT, MMIC process

AbstractIn the present work, we compare two different

embedded-gate technologies used for the fabrication of 150 nm AlGaN/GaN HEMTs intended for K- and Ka-band satellite communication applications. DC performance of fabricated transistors has been similar for both technologies. Load-pull measurements at Vds = 28 V, Ids = 30 % Idsmax and tuned for the maximum Pout

showed more than 5.5 W/mm power density at 20 GHz operation for 4×75 µm devices, regardless of the gate technology. DIVA (pulsed I-V) measurements unveiled the first advantage of sputtered iridium gate technology – a significant reduction of gate lag. High-temperature reverse-bias test (HTRB) showed significant degradation of the Schottky barrier for all samples. At the same time, maximum drain current degradation and increase of drain pinch-off current for sputtered Ir gates was less pronounced as compared to e-beam evaporated Ir technology. High-temperature operation test (HTO) demonstrated Schottky barrier increase due to thermal annealing and the filling of deep donor traps on the metal/semiconductor interface by hot electrons generated during the transistor operation.

INTRODUCTION

The capability of high voltage operation in conjunction with high output power density allows GaN HEMTs to be operated at a much higher output impedance as compared to the conventional GaAs pHEMTs, for a given output power. This relaxes the matching conditions for GaN devices and significantly reduces losses, especially for high frequency applications. The first commercially available GaN devices with operation frequency up to 30 GHz have been already demonstrated [1]. Among many factors that are influencing transistor performance, one of the most important issues is

the gate fabrication technology, i.e. how the complex interface between gate metal, passivation and semiconductor is defined during device processing. FBH standard technology (Fig. 1) uses an e-beam evaporated Ir/Ti/Au metal stack. In contrast, the sputtered Ir gate technology relies on an Ir layer sputtered immediately after the gate trench etching into SiNx, followed by an e-beam evaporated Ti/Au/Ir metallization scheme (Fig. 2). As the sputter process provides a more robust and conformal gate trench coverage and no photolithography step is required between gate trench etching and gate metal deposition, reliability and performance of the latter transistors is expected to outperform standard technology [2].

EXPERIMENT

Epitaxial structures used for transistor fabrication were grown by low-pressure MOVPE on semi-insulating 4H-SiC substrates. The epitaxial structure consisted of an AlN nucleation layer followed by a Fe-doped 2 µm thick GaN buffer and a 10 nm thick Al0.32GaN barrier layer. A thin 2 nm GaN cap layer was added on top of the structure in order to prevent Al oxidation. Ohmic contact definition relies on a Ti/Al-based metallization. After rapid thermal annealing, an ohmic contact resistance of 0.5 Ω·mm has been obtained. PECVD deposition of 100 nm thick SiNx film follows ohmic contact formation. Afterwards the active transistor area is defined by implantation of 14N+ ions (isolation implantation). ZEP resist is used for the gate trench etch mask formation with subsequent thermal reflow and highly anisotropic ICP-etching in order to obtain slanted gate trench sidewalls [3]. Immediately after gate trench etching, the wafers intended for the test of the new technology module were covered with low-stress 50 nm Ir film using DC magnetron sputtering. Afterwards, a bilayer PMMA mask was applied on all wafers for lift-off deposition of the gate head metal. It consisted of e-beam evaporated Ti/Au/Ir and Ir/Ti/Au gate metals for the Ir sputtered and the standard process, respectively. For the Ir sputter gate technology a sacrificial Ir layer (evaporated) was deposited on top of the gate head metal stack in order to facilitate self-aligned back-etching of the sputtered Ir layer. Wafers processed using sputtered Ir technology were etched

Figure 1. Standard embedded gate fabrication process flow.

in Cl2/O2/He ICP plasma using the gate metal as an etch mask for the removal of the Ir film. After the gate formation transistors were encapsulated with 200 nm PECVD SiNx

film. The process was finished with galvanic deposition of the interconnection layer and the formation of air bridges.

Figure 4. Transfer characteristics and transconductance of 2x75 µm transistors (SG distance 0.5 µm, GD distance 2 µm)

DC AND LARGE-SIGNAL PERFORMANCE

DC, small and large-signal properties of the transistors were measured after completing the process. Fig. 3 and Fig. 4 show output and transfer characteristics. A maximum current of more than 1 A/mm, a maximum transconductance of about 460 mS/mm, a pinch-off voltage of typically -2.8 V and a breakdown voltage exceeding 100 V were obtained for all devices regardless of the gate technology used. In general, the 150 nm gate length devices did not show significant punch-through up to a drain voltage of 30 V. Fig. 5 presents gate lag measurement results. DIVA measurements were performed at two different quiescent bias points P1 (Vds = 0 V; Vgs = 0 V) and P2 (Vds = 0 V; Vgs

= -7 V). The drain current was extracted from the output characteristics at instantaneous bias points at Vds = 10 V and different Vgs. Gate lag was calculated as the percentage difference between instantaneous Ids at P1 and at P2. Devices fabricated by sputtered Ir gate technology provided

a dynamic Ids reduction (lagging) between 4 % and 24 %, depending on instantaneous Vgs. For standard gate technology, the average dynamic drop of Ids has been between 6 % and 40 %. The observed difference demonstrates that transistors fabricated using Ir sputtered gate technology are less affected by gate lag phenomena.

Figure 5. Gate lag measurement results for 2x125 µm transistors fabricated using standard technology and sputtered Ir approach

Figure 6. Load-pull measurement results of 4x75 µm devices performed at the following conditions: F = 20 GHz, Vds = 28 V, Ids = 10 % Idsmax, tune for maximum PAE.

Fig. 6 shows the results of load-pull measurements performed at 20 GHz. The large-signal performance of transistors fabricated using different technologies was found to be quite similar (variation between wafers and on-wafer variations were of the same range). A saturated output power density of 4 W/mm with a corresponding PAE > 40 % and 10 dB linear gain were achieved for 4x75 µm devices at Vds

= 28 V, Ids = 10 % Idsmax when tuned for maximum PAE. For the same drain voltage, Ids = 30 % Idsmax when tuned for maximum Pout yielded Pout_sat, PAE and gain values 5.5 W/mm, 35 % and 11 dB, respectively.

HIGH TEMPERATURE REVERSE BIAS TEST

In order to evaluate potential stability and reliability issues of the newly developed devices, HTRB and HTO tests were performed.

Figure 3. Output characteristics of 2x75µm transistors (SG distance 0.5 µm, GD distance 2 µm)

During the HTRB test, devices were heated to 150 °C and biased at Vgs = Vpo – 5 V. Drain voltage was increased from 0 to 80 V with 5 V steps during 14 hours. Fig. 7 shows the results of this test. For both technologies, a significant increase of drain and gate currents can be observed. In order to clarify the degradation mechanisms and estimate the damage due to the HTRB test, DC characterization of tested transistors was performed.

Figure 7. – HTRB test results (T = 150 °C, Vds step 5 V per hour)

Fig. 8 shows pinch-off voltage (extracted at Ids = 1 mA/mm) and maximum drain current (extracted at Vds = 10 V, Vgs = 2 V) before and after HTRB test. The following effects of the test on the DC properties of the transistors were observed:

- Decrease of Idsmax: 13 % – 17 % for standard gate technology and 1 % – 4 % for sputtered gates

- Shift of pinch-off voltage in negative direction related to significant increase of off-state drain current (much more pronounced for the standard technology)

- Significant increase of reverse and forward bias gate leakage currents due to degradation of Schottky barrier height (SBH) (~ 50 % SBH decrease for both technologies)

All observed effects can be explained by one degradation mechanism – generation of traps in the AlGaN barrier layer due to the reverse piezoelectric effect [4]. The Idsmax decrease and the significant increase in off-state current caused by defects generated in AlGaN layer were already reported [5, 6]. The difference in the amount of degradation between the two technologies can be related to the initial state of the Ir/GaN interface. As proposed by Jimenez et.al [7], chemical pitting at the gate metal /GaN/AlGaN interface may lead to premature on-set of AlGaN cracking (relaxation) due to the reverse piezoelectric effect. For the standard technology, different chemicals were used during the gate lithography step, and possible contamination could cause the initial pitting process. The second effect observed, the SBH

degradation was attributed to the well-known effect of Schottky barrier lowering due to increase of positive charges (newly generated donor-like traps) at the semiconductor/metal interface.

Figure 8. – Drain current and threshold voltage extracted before and after HTRB test

HIGH TEMPERATURE OPERATION TEST

A HTO testing was performed at 150 °C, in which the test transistors were biased at Vds = 28 V and Ids adjusted to have 2.5 W/mm DC dissipated power (Ids ~ 10 % Idsmax for measured devices). The results of the test are presented in Fig. 9. DC measurements of the transistors unveiled the following effects:

- No significant change of Idsmax after the test- Shift of pinch-off voltage in positive direction and

decrease of reverse and forward bias gate leakage currents due to the increase of SBH (~ 12 % increase for both technologies)

As can be seen from the results, no signs of device degradation were observed. The increase of the SBH can be attributed to the combination of two effects – Schottky contact annealing [8, 9] and filling of deep empty donor-like states existing in the AlGaN layer by hot electrons. The latter mechanism has the opposite effect as compared to the previously mentioned barrier lowering due to the positive charges located at the metal/semiconductor interface. HTO test conditions are responsible for appearance of large numbers of hot electrons [10]. These hot electrons may then be captured by deep donor-like traps in the AlGaN layer. The captured electrons neutralize positive charges that lower the SBH. The SBH increase also explains the decrease of the drain current observed during the HTO test.

CONCLUSIONS

Figure 10. – Drain current and threshold voltage extracted before and after HTO test

Two different gate technologies were used for fabrication of transistors intended for operation in K – and Ka – band MMICs. DC and RF measurements did not show a significant difference in transistor performance. Load-pull measurements at Vds = 28 V, Ids = 30 % Idsmax and tuning for maximum Pout showed a power density of more than 5.5 W/mm at 20 GHz operation for 4×75 µm devices. DIVA measurements demonstrated a reduced gate lag for sputtered Ir gates. The HTRB test showed that sputtered Ir gates technology causes less damage of the epitaxial structure by reverse piezoelectric effect compared to the standard gates. The HTO test revealed about 10 % increase of Schottky barrier height causing a positive shift of pinch-off voltage for both technologies. Summarizing the test results one concludes that Ir sputter gate technology provides a better quality of gate metal/semiconductor interface and consequently a better dynamic performance and increased robustness of the transistors.

Figure 9. – Idq stress test results (T = 150 °C, Pdiss = 2.5 W/mm)

ACKNOWLEDGEMENTSThe authors would like to thank the team of the

microwave department for the transistor measurements. Additionally, the support from the process technology department is appreciated. Authors also would like to acknowledge Frank Brunner from material department for wafer delivery and characterization. This work was supported by the “GaNSaT” project (EC – Contract nº 606981) in the7th Framework Program Research.

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ACRONYMSRF: Radio FrequencyDC: Direct CurrentHEMT: High Electron Mobility Transistor MMIC: Monolithic Microwave Integrated CircuitDIVA: Dynamic I-V AnalysisHTRB: High-temperature reverse-bias testHTO: High-temperature operation testSBH: Schottky Barrier HeightICP: Inductively Coupled PlasmaLg: Gate LengthVpo: Pinch-off VoltageVds: Drain-Source Voltage

Vgs: Gate-Source Voltage