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Simplex Solutions , Inc. 2001 All Rights Reserved 1 IEEE DATC EDP; Apr il 9 -10, 2001

Physical Design Methodology Best PracticesNANOMETER AND RTL-DOWN CLOSURE

Aurangzeb KhanSimplex Solutions, Inc.

IEEE DATC Electronic Design Processes WorkshopMonterey, CA

Apri l 9-10, 2001


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SOC design opportunities & challenges

u No market for a 2nd to marketu 3-months late = $500M loss

0

0.5

1

1.5

2

1 3 6 912

15

18

21

24

27

Time (Months)

Norm.#

'96 Mfg. Lifecycle

00 Mfg. Lifecyc le

n Limited design capacityu Competitive new products roadmap

u

Customize productsu Access new processes first

u Multiple sourcing

n First -to-Market & Volume SOCsBusiness Success

n Rapid increase in design complexity


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VLSI SOC: Rapid increase in design complexity

n 0.5um0.18umn 5x5 mm221.7x21.3 mm2

n ~0.8287.5M transistorsn 3LM 6LMn ~50150 MHz (#>500MHz)

#

*

#: Cirrus Logic, Inc. IC, 3Ci

*: Sony Computer Entertainment, Inc. &Sony Corporation Graphics

SynthesizerI-32. Copyright 2000Sony Computer Entertainment, Inc.ISSCC2001, 9.6

DataI/O

32 Mb

eDRAM

32 Mb

eDRAM

32 Mb

eDRAM

32 Mb

eDRAM

32 Mb

eDRAM

32 Mb

eDRAM

32 Mb

eDRAM

32 Mb

eDRAM

MicroprocessorInterface

Data I/O

Data I/O

Power

Distribution

Synthesized Blocks

Power

Distribution


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VLSI SOC: Hierarchical design approach

n Enable concurrent engineering

n Reduce development complexity

nSimplify program management

n Leverage proven IP blocks

u Improve TTM, TTV and quality

u Reduce technical, schedule risks

n Leverage platform infrastructure

u

Verification, Validation

SOC

VLSI

Digital

A

Conve

ntional

Metho

dology

Time-to-Market

9

Chip Development Time

12

Add

ition

alR

esou

rce

Higher Cost

15

Time-to-Volume

Enhan

cedMe

thodo

logy

IPRe

use

ChipDesignCom

plexity

1

10

100

1000

HigherLev

erage

0 6

Multip

lePro

ducts

n SOC Design = IP block creation + block integration


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Top-level SOC design methodology

n Black-box models

Top-level

Verification

SOC Functional Partitionin g

I/O, power, cl ock, test

Design Specs

Fnl., Si.

Design

Fnl.

Design

Analog FE

Design

uP porting,

optimization

PLL, Clock

Design

RAM, ROM

Ckt. Design

I/O Design,

S I

Fn.,GDS2

.subckt,GDS2

Top-level + HDC silicon d esign

.subckt,GDS2

.subckt,GDS2

Fn.,GDS2

ERC, DRC, LVS

Tape-out

Reqmts.

n Functional design hierarchical

n Electrical / physical design hierarchical

n IP leverage; Customer-specific design


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VHDL Design

Synthesis

Pre-layout Timi ng

Design Specs

Lib.+SWLMConstraints

P&R, testabilit y

Post-layout timing

ERC, DRC, LVS

Tape-out

Power, clo ck, SI, I/O

Fnl., pwr., SI ECO

Reqmts.

Floor-planningLib.+CWLM

Formal Synthesis

Block-level design methodology

nArchitectural optimization (timing)n Inter-group buses, bandwidth

nClock, SI, test; validation

n Top-, block-specific CWLM-based(or better)

nWith added constraints

n Full RC back-annotationnHierarchical black-box models

nCustom WLM (or better)n Power, clock, test reqmts. addednCritical blocks (e.g., ECC)

n Top, block clock designn I/O driver, padringdesignnNoise minimization, isolation

n Power distribution (Internal, I/O)n Board-level timing, SI

n Scan stitching, re-ordering


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Sony Computer Entertainment: GSI-32

n Performanceu eDRAMBandwidth = 48 GB/su Buses >2K bits wideu Render 75M polygons/s

n SOC integrationu 280M + 7.5M transistorsu 21.7 x 21.3 mm2

n Scaleu >400K components

l11 blocks, 31K-218K gatesl>68K flip-flops

u >500K signal netsl>2K nets >10 mm. long

n 0.18 um, 6-metal CMOS

DataI/O

eDRAMeDRAMeDRAM eDRAM

eDRAMeDRAMeDRAM eDRAM

Mi

croprocessorInterfa

ce

Data I/O

Data I/O

Power

Distribution

Power

Distribution

Synthesized Blocks

n Enhanced architecture: 8x higher eDRAM vs. PS

2 GS

ISSCC2001 9.6


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Design approach

n Fully-hierarchical design: Netlist to tape-out in 10 weeks

n Design challenges

uPower distribution

uClock architecture

uTiming designlLoad modeling

lDelay calculation

uSignal Integrity

lBuffer insertionlCrosstalkFP: Floorplan

S: SynthesisC: ClockP&R: Place-&-RouteSI: Signal IntegrityV: ERC, DRC, LVS

RTL, Synthesis

Parallel Verif ication (0...N)

Tape-out

Concurrent

Design

FP, S, C, P&R

Timing, SI, V

FP, S, C, P&R

Timing, SI, V


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Accurate fully-hierarchical delay calculation

n Signal paths traverse hierarchyu Block inputs with ~0 2 mm. metal RC delay

IC

BAL

Q

QSET

CLR

S

RQ

QSET

CLR

S

R

B1

C D A D

IC

B C

CL B1

n Fully-hierarchical block-based timing analysisuAnalyze large designs (scalable capacity)

uEnable concurrent design

uFaster timing convergence, verification (STA)

nModel block boundary pin input RC as CLn CL timing inaccuracies when RC significant


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nCL over-estimates RC delayu Latent hold time defects

u Setup overdriven

n ECSM (Ceff(50%)) fits SPICE at

threshold

n ECSM ~2% correlation toSPICE for complex topologies

Voltage(V)

CLB1RC

C eff(50%)

A B

Ceff(50%)

Time (ns)

IC

BA B1C D

CL

IC

BA B1'C D

1.46

1.481.50

1.52

1.54

1.56

1.43 1.48 1.53Delay (ns)

Dela

y(ns) +2%

SPICEECSM

Accurate fully-hierarchical t iming


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Signal integrity

A B

X/2 mm. X/2 mm.

A B

X mm.

n Insert buffers ~1.5 - 2.5 mm.u Bound timing uncertainty

u Reduce total delay

0

2

46

8

10

12

0.5 2.5Wire Length (mm.)

Delay

(0.5mm

.norm)

w/o buffer

w/ 1 buffer

n Address impact in Static Timing

Analysisu Reduce setup time margin

u Bounded hold time margin

3%

13%

23%

33%

0.5 1.5Wire Length (mm.)

Inc.Delay(%)

0.25

0.15


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IC design design methodology, technology

n Hierarchical (mixed-signal) designu Fully-hierarchical timing: Enhance concurrent design

n Power distribution

n Clocking architecture

n New design technology

u Nonlinear delay calculation technologyu Black-box, gray-box modeling

u Signal integrity

lRC transmission line effects

lCrosstalk management

lBuffer insertionn 0.15um 0.13um work

u Technology validation, signal integrity, RLC, substrate, others

n Focus on silicon engineering: First silicon success


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Related readingn A. Khan, et. al., A 150 MHz Graphics Rendering Processor with 256Mb Embedded

DRAM, Digest of Technical Papers, pp. 150-151, 442, International Solid State

Circuits Conference, February 5-7, 2001, San Francisco

n S. Nassif , Delay Variabili ty: Sources, Impacts and Trends, pp. 369-69, Digest of

Technical Papers, International Solid State Circuits Conference, February 2000

n A. Khan, Design Challenges in Cirrus Logic, Inc. 3Ci System-on-a-Chip

Development, SOC Design Seminar, Stanford University, May 1999

n S. Nemazie, A. Khan, et. al., 260 Mb/s Mixed-Signal Single-Chip Integrated SystemElectronics for Magnetic Hard Disk Drives, Digest of Technical Papers, pp. 42-43,

443, and Slide Supplement 1999 to the Digest of Techn ical Papers, pp. 44-45,

International Solid State Circuits Conference, February 15-17, 1999, San Francisco

n R. Baird, et. al., A Mixed-Signal 120Msample/s PRML Solution for DVD Systems,Digest of Technical Papers, pp. 38-39, 442, and Slide Supplement 1999 to the Digest

of Technical Papers, pp. 40-41, 378 International Solid State Circui ts Conference,February 15-17, 1999, San Francisco

n S. Naffziger, Design Methodologies for Interconnects in GHz+ ICs, InternationalSolid State Circuits Conference Short Course, February 1999

n Semiconductor Perspectives: Top Ten Stories of 1998," Intl . Data Corp., 1/99


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Acknowledgments; Copyright notice

nWe greatly appreciate the support of :uCirrus Logic, Inc.uSony Computer Entertainment, Inc.uSony Corporation Semiconductor Network Companyu

Sony Kihara Research Center, Inc.n Registered trademarks and copyright material ofCirrus Logic, Inc., Sony Computer Entertainment, Inc.and Sony Corporation used with permission

n All r ights are reserved by the respective companiesuNo part of this material may be used without the prior written

consent of Cirrus Logic, Inc., Sony Computer Entertainment,Inc., Sony Corporation and Simplex Solutions, Inc.

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