performance of programmable logic devices (plds) in read-out of high speed detectors
DESCRIPTION
Performance of Programmable Logic Devices (PLDs) in read-out of high speed detectors. Jack Fried INSTRUMENTATION DIVISION. PLD ? Muon Tracker PLD. What Is a PLD. PLD Building Blocks. Logic Block. Device Features. PLD Features (cont). I/O Protocols. Design Entry. Plug In Manager. - PowerPoint PPT PresentationTRANSCRIPT
Performance of Programmable Performance of Programmable Logic Devices (PLDs) in read-out Logic Devices (PLDs) in read-out
of high speed detectorsof high speed detectors
Jack FriedJack FriedINSTRUMENTATION DIVISIONINSTRUMENTATION DIVISION
PLD ?PLD ? Muon Tracker PLDMuon Tracker PLD
What Is a PLDWhat Is a PLD
PLD Building BlocksPLD Building Blocks
Logic BlockLogic Block
Device FeaturesDevice Features
PLD FeaturesPLD Features(cont)(cont)
I/O Protocols
Design EntryDesign Entry
Plug In ManagerPlug In Manager
Mega FunctionsMega Functions
Design VerificationDesign Verification
•Simulation
•Built in real time Logic analyzer
PLD Design FlowPLD Design Flow
PHENIX Muon TrackerPHENIX Muon Tracker
Muon Tracker CrateMuon Tracker Crate
Cathodes Read-Out Card Cathodes Read-Out Card (CROC)(CROC)
Design RequirementsDesign Requirements 64 Channel Readout per CROC 64 Channel Readout per CROC Less than 3125 electrons (RMS) Less than 3125 electrons (RMS)
noise for 10-150 pF of detector noise for 10-150 pF of detector capacitance (including 24” cable) capacitance (including 24” cable) ••
Less than 1% crosstalk between Less than 1% crosstalk between any channels on the boardany channels on the board
gain: 3.5mV/fCgain: 3.5mV/fC Digital/Analog isolationDigital/Analog isolation
Main ComponentsMain Components AMU-ADCAMU-ADC CPACPA digital
Analog Signal
Controller Card (CNTL)Controller Card (CNTL) Design RequirementsDesign Requirements
Control AMU/ADC data collection, Control AMU/ADC data collection, conversion and read-out conversion and read-out
Provide connection to 2 CROC Provide connection to 2 CROC boards boards
Provide connection to the outside Provide connection to the outside worldworld
Support the T&FC and DCM Support the T&FC and DCM interface interface
Provide data relay from remote Provide data relay from remote controller board to DCM controller board to DCM
Support ARCnet connectivity to Support ARCnet connectivity to serial configuration busserial configuration bus
FPGA - the brainFPGA - the brain developed by Jackdeveloped by Jack
work in progresswork in progress
CNTL Card
Muon Tracker Crate Muon Tracker Crate Block DiagramBlock Diagram
PLDEPF10K50
CROC #1
2 AMUADC's
CROC #1
2 AMUADC's
PLDEPF10K50
CROC #1
2 AMUADC's
CROC #1
2 AMUADC's
CNTL BOARD
GTM
DCM
ARCNET
RD WRcontrol
Analog in
RD WRcontrol
Analog in
DIGITALDATA
DIGITALDATA
AUXControl
GTM
ARCNET
RD WRcontrol
RD WRcontrol
DIGITALDATA
DIGITALDATA
Analog in
Analog in
CNTL BOARD
Requirements for Requirements for Muon tracker PLDMuon tracker PLD
Trigger rate 25KhzTrigger rate 25Khz 4 samples per pulse4 samples per pulse Sample new data on every beam crossingSample new data on every beam crossing Holds 5 eventsHolds 5 events 100ns between triggers (burst rate)100ns between triggers (burst rate) Control digital part of AMUADC -RD-WRControl digital part of AMUADC -RD-WR Send data to DCM Send data to DCM Allow for Master and slave modesAllow for Master and slave modes
Muon TrackerMuon TrackerPLD Programming PLD Programming
Difficulties Difficulties Board already designed Board already designed
PLD already chosen (FLEX10K50E)PLD already chosen (FLEX10K50E) Pins allocatedPins allocated PLD to smallPLD to small
Overlapping eventsOverlapping events AMUADC noise problemsAMUADC noise problems AMUADC requires special RD WR AMUADC requires special RD WR
sequencesequence
ALTERAALTERA10K5010K50
Memory RequirementsMemory Requirements
4 samples per event4 samples per event Need to be able to store 5 eventsNeed to be able to store 5 events Each sample is 11bitsEach sample is 11bits 32 channels per AMUADC 32 channels per AMUADC
4 AMUADC PER CNTL 128 channels4 AMUADC PER CNTL 128 channels
28160 BITS TOTAL
Memory ImplementationMemory Implementation
DUAL PORT RAM512kX44
6 - 512x8EABs
DUAL PORT RAM128kX44
3 - 256x16EABs
44 BITSDATA OUT
44 BITS DATA IN
WRITE ADDRESS(0..8)
READ ADDRESS(0..8)
READ ENABLE RA9
WRITE ENABLE WA9
READ ENABLE /RA9
WRITE ENABLE /WA9
SAMPLE1
SAMPLE2
SAMPLE3
SAMPLE4
SAMPLE5
SAMPLE6
SAMPLE7
SAMPLE8
SAMPLE9
SAMPLE10
SAMPLE11
SAMPLE12
SAMPLE13
SAMPLE14
SAMPLE15
SAMPLE16
SAMPLE17
SAMPLE18
SAMPLE19
SAMPLE20
20 POSSIBLE LOCATION TO STORE SAMPLES TO COVER 5EVENTS 4 SAMPLES WITH UNIQUE CELLS
SIMPLIFIED MEMORYBLOCK DIAGRAM
LOGICAL MEMORYBREAK UP
DATA STORAGE
•Used 9 EABs
•Only 1 EAB left for PLD algorithm
• Lost 8704 bits
AMUADC cellAMUADC cellWriting & ReadingWriting & Reading
SINGLE EVENT
|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|……|60|61|62|63|64|
|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|……|60|61|62|63|64|
STORES ANALOGVALUE
EVERY BEAM CLOCK
TRIGGERLVL1
|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|……|60|61|62|63|64|
SAMPLES 10 11 12 15
|1|2|3|4|5|6|7|8|9|13|14|16|17|18|19|20|……|60|61|62|63|64|AFTER CELLS SELECTED THEY ARE REMOVED TILL
CONVERTED AND STORED THEN THEY ARE PUT BACK
40 beam clocksback
Overlapping EventsOverlapping Events
OVERLAPPING EVENT
|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|……|60|61|62|63|64|
|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|……|60|61|62|63|64|
STORES ANALOG VALUEEVERY BEAM CLOCK
TRIGGERLVL1
|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|……|60|61|62|63|64|
SAMPLES 10 11 13 15
|1|2|3|4|5|6|7|8|9|12|16|18|20|……|60|61|62|63|64|AFTER CELLS SELECTED THEY ARE REMOVED TILL
CONVERTED AND STORED THEN THEY ARE PUT BACK
4 CLOCK LATER
SAMPLES 14 15 17 19
40 beam clocksback
MUON TRACKERMUON TRACKERPLDPLD
F P G A
T F C
D C M
A M U A D C D A T A
A M U A D CC O N T R O L A N D D A T A
A D D R E S S
A R C N E TA U X P O R T
A M U A D CR E A D W R I T E A D D R E S S
MUON TRACKERMUON TRACKERPLDPLD
T I M I N GL O G I C
D C M O U T P U TM A N A G E R A R C N E T S E R I A L S T R I N G
D A T A S T O R A G E
A M U A D CC O N T R O L L E R
D A T AR E A D O U TM A N A G E R
A M U A D CC E L L
M A N A G E R
T F C
D C M
A U X P O R T A R C N E T
A M U A D CD A T A
A M U A D CC O N T R O L
L I N E S
A M U A D CR E A D W R I T E
A D D R E S S
AMU Cell ManagerAMU Cell Manager
amu cell add
amu cell add
amu cell add
amu cell add
amu cell add
FIFO
6x21
DELAYTILL
CONVERSIONENDS
INSERTLOGIC
FIFO6x20
cell address
noyes
sample 43
sample 42
sample 41
sample 40
amu cell add
conversion list
used
used
used
used
used
next toconvert
MUX43 to 1
6 bit
MUX43 to 1
6 bit
MUX43 to 1
6 bit
MUX43 to 1
6 bit
next toconvert
sample 1
samp 1
samp 2
samp 3
samp 4
dflip
lev1clk
dflip
clk
dflip
clk
dflip
clk
count to 4counter.
start on level 1and sav = highwhen counting
lev1
lev1
lev1
lev1
clk
EVENTLISTIN
CORRECTORDER
TO DATAREADOUT
MANAGER
IN ORDER OFCONVERSION
data availablesignal
fifo empty
If conversion list fifo emptysignal is false (not empty)
than there is data thatneeds to be converted
After rest loadshift reg with a 0-64
counter
used
sample 39
lev1
lev1
lev1
lev1
lev1
lev1
SAV
AMUADC ControllerAMUADC Controller
COUNTER
CONTROLLOGIC
FSC
DATAAVAILABLE
4 x clk
logic
start
stop
logic
start
stop
logic
start
stop
COUNTERlogic
start
stop
logic
start
stop
logic
start
stop
logic
start
stop
logic
start
stop
logic
start
stop
CLK
AZ
ICS
AMP_RST
DB_RST
COMPRST
LOAD
CLK_EN
R_EN
AMU READADDRESS
ANDMEMORY
WRITE ADDRESS(4..0)
MEMORYLOCATIONCOUNTER
clk
NEXT LOGICALMEMORY LOCATION
(9..5)
Read Out ManagerRead Out Managerpart1part1
counter0-19
SAV
CLK
DECODE
5 to 20
5bits
6 bitdflip
From Cell ManagerCell Events listin correct order
6 bitdflip
6 bitdflip
6 bitdflip
6 bitdflip
6 bitdflip
6 bitdflip
0
1
2
3
4
18
19
event 1*xsample 1
event 1*xsample 2
event 1*xsample 3
event 1*xsample 4
event 2*xsample 1
event 5*xsample 3
event 5*xsample 4
CELL EVENT LIST
Read Out ManagerRead Out Managerpart2part2
MUX20 to 1
5 bit
DFLIP&
LOGIC
compare
1
memadd (4..0)
clk
mem add = logicalmemmory address wherethe cell just converted is
located
Cell Event list location 1
Cell just converted
DFLIP&
LOGIC
compare
1
memadd (4..0)
clk
Cell Event list location 2
Cell just converted
DFLIP&
LOGIC
compare
1
memadd (4..0)
clk
Cell Event list location 3
Cell just converted
DFLIP&
LOGIC
compare
1
memadd (4..0)
clk
Cell Event list location 4
Cell just converted
DFLIP&
LOGIC
compare
1
memadd (4..0)
clk
Cell Event list location 19
Cell just converted
mem rd add[9..5]
COUNTER0 to 19 sel
NEXT SAMPLE clk
Read Out ManagerRead Out ManagerPart3Part3
DUAL PORT RAM512kX44
6 - 512x8EABs
DUAL PORT RAM128kX44
3 - 256x16EABs
44 BITSDATA OUT
44 BITS DATA IN
WRITE ADDRESS(0..8)
READ ADDRESS(0..8)
READ ENABLE RA9
WRITE ENABLE WA9
READ ENABLE /RA9
WRITE ENABLE /WA9
SAMPLE1
SAMPLE2
SAMPLE3
SAMPLE4
SAMPLE5
SAMPLE6
SAMPLE7
SAMPLE8
SAMPLE9
SAMPLE10
SAMPLE11
SAMPLE12
SAMPLE13
SAMPLE14
SAMPLE15
SAMPLE16
SAMPLE17
SAMPLE18
SAMPLE19
SAMPLE20
20 POSSIBLE LOCATION TO STORE SAMPLES TO COVER 5EVENTS 4 SAMPLES WITH UNIQUE CELLS
SIMPLIFIED MEMORYBLOCK DIAGRAM
LOGICAL MEMORYBREAK UP
DATA STORAGE
DCM Output ManagerDCM Output Manager
DCMOUT
MUX21 to 116 bit
DATASELECT
MUX2 to 121 BIT
OUT TODCM
21 bittransiver
I/OAUX
PORT
0xFFFFDETECTOR IDEVENT NUMBER
MODULE ADDRESS FLAG WORD
FEM BEAM CNT
MUON DATA
AMU CELL2AMU CELL3AMU CELL4
AMU CELL1
USER WORD USER WORD USER WORD USER WORD USER WORD
0x00000x00000x0000
0x0000X-OR
Master Slave select
endat0or
endat1
DCM outcounter0 to 20
2xclk
endat0 or endat1start cnt
MUONDATA
Add outcounter0 to 512
counterstart, stop and hold
control
2xclk
Compilation Result Compilation Result
Current codeCurrent code
Muon FEEMuon FEE PLD - current codePLD - current code
store every beam store every beam crossingcrossing
4-sample per pulse 4-sample per pulse readout time 53uSreadout time 53uS hold 4 eventshold 4 events
Time
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