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nLINEARINTEGRATEDCIRCUITHANDBOOK

oPLESSEY

W Semiconductors

LINEARINTEGRATEDCIRCUITHANDBOOKPLESSEY

V Semiconductors'yiA/wwi/|

Designed and produced by Peter Wigens ConsultantsThe Plessey Company pic

March 1983Publication No. P.S. 1973

This publication is issued to provide outline information only and (unless specifically agreed tothe contrary by the Company in writing) is not to form part of any order or contract or beregarded as a representation relating to the products or services concerned. We reserve the rightto alter without notice the specification, design, price or conditions of supply of any product or

The name Plessey and the Plessey logo are registered trademarks of The Plessey Company pic.

ContentsPage

Product index 5Product list 8

Quality data 10

Ordering information 11

Screening to MIL-STD-883 13Semi-custom 14Technical data 17

Package outlines 193

Plessey Semiconductors World Wide 203

Product indexOPERATIONAL AMPLIFIERSSL541B High slew rate operational amplifier

TAB1042 Quad programmable operational amplifierTAB1043 Quad programmable operational amplifier

LINEAR RF AMPLIFIERS

SL541B High slew rate operational amplifier

SL550D & G Low noise wideband amplifier with external gain control

SL560C 300MHz low noise amplifierSL561B,C Ultra low noise preamplifiers

PHASE LOCKED LOOP CIRCUITSSL650B C Modulator/phase locked loop circuits for modemsSL651B,C Modulator/phase locked loop circuits for modemsSL652C Modulator/phase locked loop

LIMITING WIDEBAND AMPLIFIERSSL521A,B & C 140MHz wideband log amplifierSL523B,C & HB 120MHz dual wideband log amplifierSL525C Wideband log IF strip amplifier

SL531C 250MHz true log IF amplifierSL532C Low phase shift limiterSL565C 1GHz wideband amplifierSL1521A,C 300MHz wideband amplifierSL1523C 300MHz dual wideband amplifier

Page81185189

81859195

115115119

636771

757999129133

MATCHEDSL301KXSL360C,GSL362CSL2363CSL2364CSL3045CSL3046CSL3127CSL3145C.E

TRANSISTOR AND ARRAYSDual NPN transistorsHigh performance NPN dual transistor arraysHigh performance NPN dual transistor arraysVery high performance transistor arrayVery high performance transistor arrayGeneral purpose NPN transistor arrayGeneral purpose NPN transistor arrayHigh frequency NPN transistor array1.2GHz high frequency NPN transistor arrays

RADIO-COMMUNICATIONSSL610C RF amplifierSL611C RF amplifierSL612C IF amplifierSL621C AGC generatorSL623C AM detector/AGC amplifier/SSB demodulatorSL640C Double balanced modulatorsSL641C Double balanced modulatorsSL1613C Wideband log IF strip amplifierSL1621C AGC generatorSL6270C Gain controlled preamplifierSL6310C Switchable audio amplifierSL6601C Low power IF/AF PLL circuit for narrow band FMSL6440A.C High level mixerSL6691C Monolithic circuit for paging receiversSL6700A IF amplifier and AM detectorSL6700C IF amplifier and AM detector

192727145145147147149153

103103103107111113113137141157161169165173177181

POWER CONTROL CIRCUITSSL440 Power control circuit 29

SL441A Zero voltage switch 33

SL441C Zero voltage switch 37

SL443A Zero voltage switch 41

SL445A Zero voltage switch 5SL446A Zero voltage switch 55

Product listSL301K Dual NPN transistorsSL301L Dual NPN transistorsSL303L 400MHz tripple NPN transistorsSL360CG High performance NPN dual transistor arraysSL362C High performance NPN dual transistor arraysSL440 Power control circuitSL441A Zero voltage switchSL441C Zero voltage switchSL443A Zero voltage switchSL445A Zero voltage switchSL446A Zero voltage switchSL521A,B & C 140MHz wideband log amplifierSL523B.C & HB 120MHz dual wideband log amplifierSL525C Wideband log IF strip amplifierSL531C 250MHz true log IF amplifierSL532C Low phase shift limiterSL541B High slew rate operational amplifierSL550D & G Low noise wideband amplifier with external gain controlSL560C 300MHz low noise amplifierSL561B,C Ultra low noise preamplifiersSL565C 1 GHz wideband amplifierSL610C RF amplifierSL611C RF amplifierSL612C IF amplifierSL621C AGC generatorSL623C AM detector/AGC amplifier/SSB demodulatorSL640C Double balanced modulatorsSL641C Double balanced modulatorsSL650B,C Modulator/phase locked loop circuits for modemsSL651B,C Modulator/phase locked loop circuits for modemsSL652C Modulator/phase locked loopSL1521A,C 300MHz wideband amplifierSL1523C 300MHz dual wideband amplifierSL1613C Wideband log IF strip amplifierSL1621C AGC generator

Page191923272729333741

4555636771

757981

8591

9599103103103107111

113113115115119129133137141

SL2363C Very high performance transistor arraySL2364C Very high performance transistor arraySL3045C General purpose NPN transistor arraySL3046C General purpose NPN transistor arraySL3127C High frequency NPN transistor arraySL3145C,E 1 .2GHz high frequency NPN transistor arraysSL6270C Gain controlled preamplifierSL6310C Switchable audio amplifierSL6440A,C High level mixerSL6601C Low power IF/AF PLL circuit for narrow band FMSL6691C Monolithic circuit for paging receiversSL6700A IF amplifier and AM detectorSL6700C IF amplifier and AM detectorTAB1042 Quad programmable operational amplifierTAB1043 Quad programmable operational amplifier

145145147147149153157161

165169173177181

185189

Quality dataPlessey Semiconductors has Factory Approval to:-

BS9300 for semiconductor devices of Assessed Quality (BSI Certificate1053/M)BS9400 for integrated circuits of Assessed Quality (BSI Certificate1053/M)CECC 50000 Inspection Organisation to document level 1 (BS9300)M0020/CECC refersDEF STAN 05 21 QC System requirements for Industry (Equivalent toAQAP 1) Certificate 65752/1/01 refers

Devices are also manufactured and tested in accordance with the methods of MIL-STD-833, the US Military Standard; Test Methods and Procedures for Microcircuits,and MIL-M-38510, US Military Specification, Micro-electronics; GeneralSpecifications for.

10

Ordering informationAll Plessey Semiconductors integrated circuits are allocated type numbers whichmust be quoted when ordering. This number may or may not have a suffix (A, B, C,etc.) which denotes the precise electrical specification or temperature grade. Whenthere is a choice of packages the two-digit Pro-Electron code is used to identify thestyle required, according to the following table:

CM - Multilead TO-5DC - Ceramic Dual-in-Line (metal lid)DG - Ceramic Dual-in-LineGC - Ceramic Chip Cover

Within the UK, orders for quantities up to 99 will be referred to your local Distributor.

Quantities of 1000 and over must be ordered from:

Plessey Semiconductors LimitedCheney Manor

Swindon, Wiltshire SN2 2QWUnited Kingdom

Telephone: Swindon (0793) 36251Telex: 449637

A reciprocal arrangement exists with all Distributors, but it will expedite delivery oforder if buyers can direct orders as indicated above. Outside the UK, irrespective of

quantity, you are invited to contact your nearest Plessey Semiconductors SalesOutlet (see pages 203-207).

11

DELIVERED PRODUCT QUALITYIt is our policy to deliver a reliable quality product and to achieve this end all devicesundergo 100% electrical testing of every relevant AC and DC parameter prior toshipment. The devices are tested under conditions of level and frequency closelysimulating those of the typical application. Fully automatic Teradyne integratedcircuit test machines, acknowledged to be among the best computer controlled testmachines available, are employed.

Each and every stage of processing, assembly and testing is carefully audited byPlessey Semiconductors' independent Quality Assurance department.

Therefore we are able to guarantee the following Acceptable Quality Level (A.Q.L.) onall deliveries.

MECHANICALDefects of a mechanical nature including coding not being legible, deformed leads,dimensional tolerances being exceeded, wrong identification of pin 1 and pins notbeing solderable.

0.65% AQL.I.LII

ELECTRICALDefects of an electrical nature including device parameters being outside theacceptance specification limits, or those only stated as typical being grossly in error.

0.4% AQL.I.LII

The average delivered product quality is considerably better than this, the populationof imperfect devices being much smaller than that indicated by the AQL values.

12

Screening to MIL-STD-883The following Screening Procedures are available from Plessey Semiconductors

CLASSS

CLASSB

*STANDARDPRODUCTS

PRE CAPVISUAL

I

STABILIZATIONBAKE

TEMPERATURECYCLING

CENTRIFUGE

VISUALINSPECTION

I

HERMETICITY

P.I.N. D.

SERIALIZATION

RADIOGRAPHIC

INTERIMELECTRICAL TEST

BURN-INI

FINALELECTRICAL TEST

PRE CAPVISUAL

STABILIZATIONBAKE

TEMPERATURECYCLING

CENTRIFUGE

VISUALINSPECTION

HERMETICITY

PRE CAPVISUAL

VISUALINSPECTION

HERMETICITY(SAMPLE)

INTERIMELECTRICAL TEST

BURN-IN



QUALIFICATIONOR CONFORMANCE

TESTING AS REQUIRED

'Plessey Semiconductors reserve the right to change the Screening Procedure for Standard

Products.

13

Semi-custom designThe table outlines the essential parameters of our Semi-custom design

techniques, including typical timescales for the design and production of aSemi-custom IC.

NAME PARTNUMBER

TECHNOLOGY LOGICELEMENTS

TYP.GATEDELAY/POWER

SYSTEMCLOCKSPEED

Microcell

MJ 1XXX

MJ 1XXX

MV 1XXX

NMOS(Std)

NMOS(low power)

CMOS

Up to 3000equiv.gates



50ns at250a/W

200ns at4QuW20ns at

12a/W/MHz

2MHz

2MHz

8MHz

Microgate-C1000 Series

(CMOS Gate Array)

CLA 10XX

CLA 12XX

CLA 15XX

CMOS

CMOS

CMOS

560

960

1440

6ns at6*/W/MHz

6ns at6*/W/MHz

6ns atQuW/MHz

8MHz

8MHz

8MHz

Microgate-C2000 Series

(CMOS Gate Array)

CLA 21XX

CLA 23XX

CLA 25XX

CMOS

CMOS

CMOS

840

1440

2400

4ns attyW/MHz4ns at

3*/W/MHz

4ns at3//W/MHZ

14MHz

14MHz

14MHz

Microgate-E(ECL Gate Array)

SCD 1XXXSCD 2XXXH

SCD 2XXXM

SCD 2XXXL

ECL

ECL

ECL

ECL

75

300

300

300

550ps/900mW550ps/3.5W

1.5ns/1W

2ns/750mW

300MHz

300MHz

250MHz

100MHz

NAME PARTNUMBER TECHNOLOGY

COMPONENT COUNT

RESISTANCE TRANSISTORSNPN PNP

MicroNn(Analogue Array)

BAA1XXXBAA2XXX

Bipolar

Bipolar

1219kO

2757kO

81

163

28

58

'Design and test times given are typical. Actual times will depend on the complexity of the particularcircuit.

14

INPUT/OUTPUTELEMENTS

COMPATI-BILITY

MAX.PIN

COUNT

No. OFCUSTOMMASKS

TYPICAL TIMEFOR 1st SAMPLES

As required

As required

As required

TTL/CMOS

TTL/CMOS

TTL/CMOS

64

64

64

6

6

9

19 weeks*

38lorO

50lorO

60lorO

TTL/CMOS

TTL/CMOS

TTL/CMOS

40

64

64

1

1

1

16 weeks*

40lorO

52 1 or O

60 1 or O

TTL/CMOS

TTL/CMOS

TTL/CMOS

44

56

64

3

3

3

13 weeks*

25 1 or O361

20lorO361

20lorO361

20lorO

ECL 10K

ECL 10K

ECL 10K

ECL 10K

28

64

64

64

3

3

3

3

16 weeks*

It

(1mA 5V Vcc)STANDARD NPN

LVcco/BVcco

MAX.PIN

COUNT

No. OFCUSTOMMASKS

TYPICAL TIMEFOR 1st SAMPLES

470MHz

470MHz

20V/30V

20V/30V

24

24

1

1

15 weeks*

15

Technical Data

17

SL301K/SL301L

^^P' Semiconductors

,

SL301K, SL301L400MHz DUAL NPN TRANSISTOR

The SL301K and SL301L are dual monolithic NPNtransistors with close parameter matching and high ft. TheSL301K and SL301L have identical electrical specification.

FEATURES

Close Vbe MatchingOmVClosehfe Matching>0.9Good Frequency Response>400MHzGood Thermal TrackingWide Operating Current Range

APPLICATIONS

Differential Amplifier to Very High Frequencies

Comparators

Current Sources

Instrumentation

ABSOLUTE MAXIMUM RATINGS

All electrical ratings apply to individual transistors.Thermal ratings apply to the total package.The absolute maximum ratings are limiting values above

which operating life may be shortened or specified para-meters may be degraded.The isolation pin (substrate) must be connected to the

most negative point of the circuit to maintain electricalisolation between transistors.

Storage temperature -55C to +175C (CM8)Maximum junction temperature +175CThermal resistance: see Note 1

Chip-to-case 265 C/W (CM8)Chip-to-ambient 425 C/W (CM8)

Vcb = 20V Veb = 4.0V Vcer = 20V (see Fig.7)Vce = 12V Vci = 25V Ic = 20mA

NOTE:These figures are worst case, assuming all the power isdissipated in one transistor. If the power is equally shared

between the two transistors, both thermal resistance figurescan be reduced by 50C/watt.

CM8

CM8SL301K

Fig.1 Pin connections

19

SL301K/SL301L

ELECTRICAL CHARACTERISTICSTest conditions (unless otherwise stated):

Tamb = 22C2C

Characteristic SymbolValue

Units ConditionsMfn. Typ. Max.

Collector base breakdown BVcbo 20 V Ic = 10/yACollector emitter breakdown BVceo 12 V Ic = 10//ACollector emitter breakdown LVceo 12 V Ic = 5mAEmitter base leakage current Iebo 1 M Veb = 4VEmitter base leakage current Iebo 10 nA Veb = 2VCollector isolation breakdown BVcio 25 V Ic = 10/iAForward current transfer ratio Hfe 40

6050

70100

80 380V)

4.7nF

2.7nF

3.0k6.8k7.5k

12k

5.1W9.1W9.8W15.3W

2.SW4.5W4.9W7.6W

110V220V/24ov y380V )

4.7nF

2.7nF

3.0k6.8k7.5k

12k

5.1W9.1W9.8W15.3W

2.5W4.5W4.9W7.6W

110V220V/24ov y380V)

4.7nF

2.7nF

2.2k5.1k6.2k9.1k

7.0VV12.1W11.8W20.2W

3.5W6.0W5.9VV10.1W

110V220V/240V y380V)

4.7nF

2.7nF

.

*

2.2k4.7k5.1k8.2k

7.0W13.1W14.4W22.4VV

3.5W6.5W7.2VV

11.2W

110V220V/240V y380V )

4.7nF

2.7nF

54 Table 1 Value of RD (mains dropping resistor)

SL446A

^W Semiconductors

.

SL446AZERO VOLTAGE SWITCH

Intended for use in ON/OFF control of triacs, theSL446A incorporates zero voltage point triggering inorder to minimise radio frequency interference. Mainapplication areas are in switching resistive loads andreplacing mechanical thermostats in, for example,central heating systems, washing machine heaters,water heaters and smoothing irons.The SL446A is suitable for mains on-line operation

and requires minimal external components.

FUNCTIONS

1. Balanced zero voltage point crossing detector,spike filter and pulse generator for reliable triggering ofthe triac.2. A period pulse generator and bistable which arearranged to provide symmetrica/ burst control andeliminate half-wave firing (EN50,006/BS5406, 1976).3. A high input impedance differential amplifier toform part of a servo system. An internally definedlevel of hysteresis is incorporated in the amplifierwhich can limit the rate of correction of the loop tomeet the requirements of EN50,006/BS5406-1976,regarding flicker.4. Internal rectification and regulation of currentlimited AC supply provides power for the IC and asuitable supply for the resistance bridge.

COMMON ( -VE)[

AC INPUT [

POSITIVE LINE (Vcl [

TRIAC GATE DRIVE [

8 ] SERVO AMPLIFIER ^VE l/P

7 ] SERVO AMPLIFIER -VE IIP

6 ] PULSE DELAY CAPACITOR

5 ]REGULATEO OUTPUT

DP8

Fig. 1 Pin connections

5. A supply voltage sensing circuit which inhibitsfiring pulses when the supply is inadequate toguarantee proper circuit operation. This effectively

prevents firing pulses from being applied to the

triac which are incapable of causing complete bulkconduction (possible failure mechanism at switch-on).

APPLICATIONS

Pan Temperature Control

Water Heaters

Refrigerators

Panel Heaters

REGULATED OUTPUT 5

A/C INPUT 2 th STAGE

DC BLOCKING

Fig. 9 Suitable interstage tuned circuit

65

SL521A/B/CParasitic Feedback Parameters (Approximate)

The quotation of these parameters does not indicate thatelaborate decoupling arrangements are required; theamplifier has been designed specifically to avoid thisrequirement. The parameters have been given so that thenecessity or otherwise of further decoupling, may become amatter of calculation rather than guess-work.

I 4 RF current component from pin 4 C7 = rr^l 7~-

~ = 20 mmhosV6 Voltage at pin 6

(This figure allows for detector being forward biased bynoise signals)

Vg_

Effective voltage induced at pin 6V4 Voltage at pin 4

l 2 _ Current from pin 2V6 Voltage at pin 6

Voltage induced at pin 6[vaja Voltage at pin 2

Voltage at pin 2(pin 6 joined to pin 7 andfed from 300 ohms source)

6mmhos(f= 10MHz)

= 0.03(f= 10MHz)

~yfi~|_ Voltage induced at pin 6

Vjjb Voltage at pin 2Voltage at pin 2

(pin 7 decoupled)

= 0.01 (f = 10MHz)

V6 LVaJ a[v2J b decrease with frequency above 10MHzat 6 dB/octave.

66

SL523B/SL523C/SL523H

SL523 B,C&HDUAL WIDEBAND LOG AMPLIFIER

The SL523B and C are wideband amplifiers for use insuccessive detection logarithmic IF strips operating atcentre frequencies between 10 and 100MHz. They arepin-compatible with the SL521 series of logarithmicamplifiers and comprise two amplifiers, internallyconnected in cascade. Small signal voltage gain is24dB and an internal detector with an accuratelogarithmic characteristic over a 20dB range producesa maximum output of 2.1mA. A strip of SL523s can bedirectly coupled and decoupling is provided on eachamplifier. RF limiting occurs at an input voltage of25mV RMS but the device will withstand inputvoltages up to 1.8V RMS without damage.The SL523H is supplied in matched sets of eight devices.

The gain at 60MHz of the devices in the set is matched to0.75dB. In all other respects the device is identical to anSL523B. This selection enables very precise log strips tobe produced.

FEATURES

Small Size/WeightLower Power ConsumptionReadily CascadableAccurate Logarithmic DetectorCharacteristic

QUICK REFERENCE DATASmall Signal Voltage Gain 24dBDetector Output Current 2.1mANoise Figure 4dBFrequency Range 10- 100MHzSupply Voltage ^6VSupply Current 30mA

INPUT EARTH

VIDEO OUTPUT

CM8

Fig. 1 Pin connections (view from beneath)

ABSOLUTE MAXIMUM RATINGS(Non simultaneous)Storage temperature range 55 C to + 1 75 COperating temperature range 55C to +125 CMaximum instantaneous voltage at video output

+ 12VSupply voltage +9V

^rr*tc=b>i

riri;

mO EARTHEARTHFig. 2 Circuit diagram (one amplifier)

67


ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated) :Ambient temperature 22C 2CSupply voltage +6VDC connection between pins 6 and 7

Source impedance 10 fiLoad impedance 8pFFrequency 60MHz

Characteristic TypeValue

Units ConditionsMin. Typ. Max.

Small signal voltage gain B H 22.6 24 25.4 dB !C 22 24 26 dB / Freq. 30MHz

Small signal voltage gain B H 22 24 26 dB 1C 21.4 24 26.6 dB / Freq. 60 MHz

Gain variation (set of 8) H 0.5 0.75 dB Freq. = 60MHzUpper cut off frequency B C &H 120 150 MHzLower cut-off frequency B C & H 10 15 MHzPropagation delay B C & H 4 nsMaximum rectified videooutput current B H 1.9 2.1 2.3 mA |

C 1.8 2.1 2.4 mA / V in 0.5VRMSMaximum input signalbefore overload B C & H 1.8 1.9 VRMSNoise figure 4 5.25 dB Source impedance

450 QSupply current BH 25 30 36 mA

C 23 30 38 mAMaximum RF outputvoltage B C & H 1.2 Vp-p

Vin mVrmj

Fig. 3 Rectified output current v. input signal

OPERATING NOTESThe amplifier is designed to be directly coupled (see

Fig. 5)The fourth stage in an untuned cascade will give full

output on the broad band noise generated by the firststage.

Noise may be reduced by inserting a single tunedcircuit in the chain. As there is a large mismatch betweenstages a simple shunt or series circuit cannot be used.The network chosen must give unity voltage gain atresonance to avoid distorting the log law. The typicalvalue for input impedance is 500 ohms in parallel with5pF and the output impedance is typically 30 ohms.Although a 1nF supply line decoupling capacitor is

included in the can an extra capacitor is required whenthe amplifiers are cascaded. Minimum values for thiscapacitor are : 2 stages - 3nF, 3 or more stages - 30nF.

In cascades of 3 or more stages care must be taken toavoid oscillations caused either by inductance commonto the input and output earths of the strip or by feedback

68

24

\m 22 >

|I

\3 18< 16

o u

12

FREQUENCY MHz

Fig. 4 Voltage gain v. frequency

Frequency range : 10 to 100MHzLog.range: 45dBRF small signal gain : 48dBVideo output : 2Vpeak

Fig. 5 Simple log.IF strip

along the common video line. The use of a continuousearth plane will avoid earth inductance problems and acommon base amplifier in the video line isolating thefirst two stages as shown in Fig.6 will eliminate feed-back on the video line.


Frequency range : 10to90MHzLog.range: 80dBRF small signal gain : 72dBVideo output : 8mA peakLog.accuracy : 0.5dB (Typ.)

Fig. 6 Wide dynamic

TYPICAL PERFORMANCEUnselected SL523B devices were tested in a wide-

band logarithmic amplifier, described in RSRE Memo.No.3027 and shown in Fig. 7.The amplifier consists of six logarithmic stages and two'lift' stages, giving an overall dynamic range of greaterthan 80dB. The response and error curves were plottedon an RHG Log Test Set and bandwidth measurementswere made with a Telonic Sweeper and Tektronixoscilloscope.

Fig. 8 shows the dynamic range error curve andfrequency response obtained. The stage gains of theSL523 devices used were as shown in Table 1

.

Stages fo (MHz) Gain (dB)Max.

Deviation(dB)

1

23Lift

60606060

24.1 2324.08923.88824.086

1

0.235

Table 1 Stage gains of SL523 used in performance tests

The input v. output characteristic (Fig. 8a) is cali-brated at 10dB/cm in the X axis and 1V/cm in the Y

range log.IF strip

axis. 80dB of dynamic range was attained.The error characteristic (Fig. 8b) is calibrated at

10dB/cm in the X axis and 1dB/cm in the Y axis; thisshows the error between the log. input v. outputcharacteristic and a mean straight line and shows that adynamic range of 80dB was obtained with an accuracyof 0.5dB.As a comparison, the log amplifier of Fig. 7 was con-

structed with randomly selected SL521 Bs (twoSL521BS replacing each SL523B). Again, a dynamicresponse of 80dB was obtained (Fig. 9a) with anaccuracy of +0.75dB (Fig. 9b).

Bandwidth curves are shown in Figs. 8c and 9c,where the amplitude scale is 2dB/cm, with frequencymarkers at 10MHz intervals from 20 to 100MHz. UsingSL523Bs (Fig. 8c), the frequency response at 90MHz is4dB down on maximum and there is a fall-off in responseafter 50MHz. Fig. 9c shows that the frequency responseof the amplifier falls off more gradually after 40MHz butagain the response at 90MHz is 4dB down on maximum.

These tests show that the SL523 is a very successfuldual-stage log.amplifier element and, since it is pin-compatible with the SL521, enables retrofit to becarried out in existing log. amplifiers. It will be of greatestbenefit however, in the design of new log amplifiers,enabling very compact units to be realised with a muchshorter summation line.

Fig. 7 Wideband logarithmic amplifier 69


Fig. 8a Input/output

Fig. 8b Error curve

Fig.9a Input/output

Fig. 9b Error curve

Fig. 9c Frequency response, detected output

Fig. 8 Characteristics of circuit shown in Fig. 7 using SL523Bs Fig. 9 Characteristics of circuit shown in Fig. 7 using SL521Bs

70

SL525C

Semiconductors

SL525CT20MHZ WIDEBAND LOG IF STRIP AMPLIFIER

The SL525C is a bipolar monolithic integrated circuit

wideband amplifier, intended primarily for use in successive

detection logarithmic I.F. strips, operating at centre

frequencies between 10MHz and 60MHz. The devices

provide amplification, limiting and rectification, are

suitable for direct coupling and incorporate supply line

decoupling. The mid-band voltage gain of the SL525C is

typically 12dB.

FEATURES

Well-defined Gain

4dB Noise FigureHigh l/P ImpedanceLow 0/P Impedance150 MHz BandwidthOn-Chip Supply Decoupling

Low External Component Count

APPLICATIONS

Logarithmic IF strips with Gains up to 108 dBand Linearity Better Than 1 dB.

CM8



Storage temperature range

Operating Temperature range

Maximum instantaneous voltage atvideo output

Supply voltage

-55Cto+175C-20Cto+100C

+12V9V

20-0

14

a2 12z

S,.

o2 .0o

10

/./*/'""!["X\\v \\\\\T= t M0C XIw

]

FUEQUENC1 1u

MHil10* IM

Fig.3 Voltage gain v. frequency

Fig.2 Circuit diagram 71

SL525C

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise stated):-TA = +22C 2CSupply voltage = +6VDC connection between input and bias pins

ValueCharacteristic Unit* Conditions

Min. Typ. Max.

Voltage gain 10.5 13.5 dB f= 30MHz, Rs = 10ft, C L =8pF10.0 14.0 dB f = 60MHz, Rs = 10ft, C L = 8pF

Upper cut-off frequency (Fig. 3) 120 150 MHz Rs = 10ft, C L =8pFRs = 10ft, C L =8pF

Lower cut-off frequency (Fig. 3) 5 7 MHzPropagation delay 2 nsMax. rectified video outputcurrent (Figs. 4 and 5) 0.85 1.25 mA f = 60MHz, Vjn = 500mV rmsVariation of gain with supply voltage 0.7 dB/VVariation of maximum rectifiedoutput current with supply voltage 25 %/VMaximum l/P signal before overload 1.8 1.9 Vrms See note 1Noise figure (Fig. 6) 4 5.25 dB f = 60MHz, Rs = 450ftMaximum RF output voltage 1.2 Vp-pSupply current 15 mA

,.

NOTE1 Overload occurs when the input signal reaches a level sufficient to forward-bias the base-collector junction of TR1 on peak.

1

1

III^.

s* JOMMi

10 /s -t-1_ \'/s

M-e

t \

iI

1 1

1

30MHj_

1

r

1OMMi

1 1

INPUT = 0'5V RMS

SL525C

The 500pF supply decoupling capacitor hat a resistance

of, typically, 10 ohms. It is a junction type hawing a low

breakdown voltage and consequently the positive supply

current will increase rapidly if the supply voltage exceeds

7.5V (see ABSOLUTE MAXIMUM RATINGS).

AMBIENT TEMPERATURE ( C I

Fig. 5 Maximum rectified output current v. temperature

TEMPERATURE I'd

Fig. 6 Typical noise figure v. temperature

OPERATING NOTES

The amplifiers are intended for use directly -coupled, as

shown in Fig. 8The seventh stage in an untuned cascade will be giving

virtually full output on noise.

Noise may be reduced by inserting a single tuned circuit

in the chain. As there is a large mismatch between stages a

simple shunt or series circuit cannot be used. The choice of

network is also controlled by the need to avoid distorting

the logarithmic law; the network must give unity voltage

transfer at resonance. A suitable network is shown in Fig. 9.The value of C1 must be chosen so that at resonance its

admittance equals the total loss conductance across the

tuned circuit. Resistor R1 may be introduced to improve

the symmetry of filter response, providing other values are

adjusted for unity gain at resonance.A simple capacitor may not be suitable for decoupling

the output line if many stages and fast rises times are

required.Values of positive supply line decoupling capacitor

required for untuned cascades are given below. Smaller

values can be used in high frequency tuned cascades.

Number of stages

6 or more 5 4 3

Minimum capacitance 30nF 10nF 3nF 1nF

The amplifiers have been provided with two earth leads

to avoid the introduction of common earth lead inductance

between input and output circuits. The equipment designer

should take care to avoid the subsequent introduction of

such inductance.

~r~r i iovr the frqu*

I|

ncy ror 9*

1 11

1, JS'C,

I

1n 70 t0 K) 1 00

FREQUENCY (MHz)

Fig. 7 Input admittance with open-circuit output

SZ SUPPLY~T DECOUPLING

OC.v-TW^CONNECTION f * ^"V

O

4

1*6 2+V 5 4 3 /_J \ 5 4 1 i_J \ 5

1 \2 *T

\ DECOUPLING

Fig. 8 Direct coupled amplifiers

V tWAk PIN!

^DC ILOCKIN

TO (n.lltHSTAGC

CAPACITOR

Fig. 9 Suitable interstage tuned circuit

73

SL525C

Parasitic Feedback Parameters (Approximate)

The quotation of these parameters does not indicate thatelaborate decoupling arrangements are required; theamplifier has been designed specifically to avoid thisrequirement. The parameters have been given so that thenecessity or otherwise of further decoupling, may become amatter of calculation rather than guess-work.

[4 _ RF current component from pin 4..,.__ t ' z = 20 mmhos

6 voltage at pin 6

(This figure allows for detector being forward biased bynoise signals)

^6_

Effective voltage induced at pin 6V4 Voltage at pin 4

=

003

l 2 _ Current from pin 2V6

=

Voltage at pin 6= 6mmhos (f = 10MHz

[%- Voltage induced at pin 6= Voltage at pin 2 ' 03 (f = 10MHz >Voltage at pin 2

(pin 6 joined to pin 7 andfed from 300 ohms source)

fV6"l Voltage induced at pin 6 _

,

vfj b

V

o,tageatpin2 = 01 < f = 10MHz >

Voltage at pin 2(pin 7 decoupled)

Ve Lvd a\y2J b decrease with frequency above 10MHzat 6 dB/octave.

74

SL531C

K ^rLEwwC^Vr Semiconductors

,

SL531CTRUE LOG IF AMPLIFIER

The SL531C is a wide band amplifier designed for usein logarithmic IF amplifiers of the true log type. The input

and log output of a true log amplifier are at the same fre-

quency i e detection does not occur. In successive det-

ection log amplifiers (using SL521 , SL1 521 types) the log

output is detected.The small signal gain is 10dB and bandwidth is over

500MHz. At high signal levels the gain of a single stagedropstounity.Acascade ofsuch stagesgiveacloseapproxi-mation to a log characteristic at centre frequencies

between 10 and 200MHz.An important feature of the device is that the phase shift

is nearly constant with signal level. Thus any phase infor-

mation on the input signal is preserved through the strip.

INPUT EARTH

INPUT I . DECOUPLE\/"^~"\/ ILFONLYI

BIAS l-O 6 OH OUTPUT

CM8


FEATURES

Low Phase Shift vs Amplitude

On-Chip Supply Decoupling

Low External Components Count

APPLICATIONSTrue Log Strips with:

Log RangeCentre frequencies

Phase Shift

70 dB10-200 MHz 0.5 degrees/ 10 dB


Supply voltageStorage temperature rangeOperating temperature range

Max junction temperatureJunction ambient thermal resistanceJunction case thermal resistance

+ 15 volts-55Cto+ 150C-55Cto+125C

See operating notes

150C220C/Watt80C/Watt

CIRCUIT DESCRIPTION

The SL531 transfer characteristic has two regions. Forsmall input signals it has a nominal gain of 10 dB, at large

signals the gain falls to unity (see Fig 7). This is achieved byoperating a limiting amplifier and a unity gain amplifier inparallel (see Fig 3). Tr1 and Tr4 comprise the long tailedpair limiting amplifier, the tail current being supplied by Tr5,

see Fig 2. Tr2 and Tr3 form the unity gain amplifier the gain

of which is defined by the emitter resistors. The outputs ofboth stages are summed in the 300 ohm resistor and Tr7acts as an emitter follower output buffer. Important

features are the amplitude and phase linearity of the unity

gain stage which is achieved by the use of 5GHz transistorswith carefully optimised geometries.

Fig. 2 Circuit diagram

Fig. 3 Block diagram

75

SL531C


Test Conditions (unless otherwise stated):Test circuit Fig (4)Frequency 60 MHzSupply voltage 9 voltsAmbient temperature 22 2C

CharacteristicValue

Units ConditionsMin Typ Max

Small signal voltage gainHigh level slope gain

8-1

10 12+ 1

dBdB

Vin =-30dBm

Upper cut off frequency 250 500 MHzLower cut off frequencySupply current

317

10 MHz-3dBw.r.t. 60 MHz

Phase change with input amplitudeInput impedance

1.1 32.5pf parallel with 1k

degrees Vin 30 dBm to + 1 dBmOutput impedance 15Dseries with 25nh

L i

10- 200MHz

OPERATING NOTES

1

.

Supply Voltage Options

An on chip resistor is provided which can be used to dropthe supply voltage instead of the external 1 80 ohms shownin the test circuit. The extra dissipation in this resistor re-duces the maximum ambient operating temperature to100C. It is also possible to use a 6 volt supply connecteddirectly to pins 1 and 2. Problems with feedback on thesupply line etc may occur in this connection and RF chokesmay be required in the supply line between stages

2. Layout Precautions

The internal decoupling capacitors help prevent high fre-quency instability, however normal high frequency layoutprecautions are still necessary. Coupling capacitors shouldbe physically small and be connected with short leads. It ismost important that the ground connections are made withshort leads to a continuous ground plane.

3. Low Frequency Response

The LF response is determined by the on chip capacitors.It can be extended by extra external decoupling on pins 5and 1.

Fig. 4 Test circuit

I

J

V|N -40 Bn,

sC \^ \

.

-

Zl5 '^ \V-7"t " / / \ \/ I IT--55C

/T= 25

/+ 1?. c A

\\"

\^ i-

j \-

y;\ft J-

MHz K MHz 100MHz

76Fig. 5 Small signal frequency response

SL531C

Vin (dBm)

Fig. 6 Phase v. input

TYPICAL APPLICATION - 6 STAGE LOG STIP

Input log range OdBm to -70dBmLow level gain 60dB (-70dBm in)Output dynamic range 20dBPhase shift (over log range) 3Frequency range 10 200MHz

The circuit shown in Fig 9 is designed to illustrate the use

of the SL531 in a complete strip. The supply voltage is fed

to each stage via an external 180Q resistor to allow oper-ation to 125C ambient. If the ambient can be limited to

+ 1 00C then the internal resistor can be used to reducethe external component count. Interstage coupling is very

simple with just a capacitor to isolate bias levels being

necessary. No connection is necessary to pin 5 unless oper-ation below 10MHz is required. It is important to provideextra decoupling on pin 1 of the first stage to prevent posi-

tive feedback occuring down the supply line. An SL560 isused as a unity gain buffer, the output of the log strip being

attenuated before the SL560 to give a nominal OdBm out-put into 50D.

60 MHzVCC =9V

LOW LEVELGAIN10 dB

; // // ///i ji /l /l/

.

Vin VOLTS (rms)

Fig. 7 Transfer characteristics linear plot

60 MHzVCC 9VOLTS

V^ IN IdBm]

Fig. 8 Transfer characteristics logarithmic input scale

Fig. 9 Circuit diagram 6 stage strip

SL531C

to

//////

60 M z

1CO

g 0-6

3

0-2

-80-60

-40

INPUT (dBm)

< -2XO-

-3

-^

80-f

-4-20 c

INPUT (dBm)

Fig. 10 Transfer function' of log strip

78

SL532C

Semiconductors

SL532CLOW PHASE SHIFT LIMITER

The SL532C is a monolithic integrated circuit designedfor use in wide band limiting IF strips. It offers a bandwidth

of over 400MHz and very low phase shift with amplitude.The small signal gain is 12dB and the limited output is1volt peak to peak. The use of a 5GHz IC process hasproduced a circuit which gives less than 1 phase shift

when overdriven by 12dB. The amplifier has internaldecoupling capacitors to ease the construction of cas-

caded strips and the number of external componentsrequired has been minimised.

FEATURES

Low Phase Shift v. Amplitude

Wide BandwidthLow External Component Count

APPLICATIONS

Phase Recovery Strips in Radar and ECM Systems(e.g. Doppler)

Limiting Amps for SAW Pulse Compression SystemsPhase Monopulse Radars

Phased Array Radars

Low Noise Oscillators


Test conditions (unless otherwise stated):Temperature (Ambient) 25CFrequency 60MHzVcc = +9VRL =1kffl/2.5pF

INPUT GROUND

INPUT _!_ DECOUPLE OF 0NW

OUTPUT GROUND

CM8

Fig.1 Pin connections

"^rr FJt*Ww*

Fig.2 Circuit diagram

ValueConditions

CharacteristicMin. Typ. Max.

Small signal voltage gain 10 12 14 dB

Limited output voltage

Upper cut off frequency

Lower cut off frequency

0.9

200

1.2

4007.5

1.55

10

Vp-pMHzMHz

i -3dB. The lower frequency cut off can be

\ extended by the use of external capacitors

Supply current 8.5 11 mA

Phase variation with signal level 1 degree Vin=-30dBm to +10dBm

Input impedance 1kQ//2.5pF

Output impedance 30O

Max input signal before overload +20 dBmGain variation with temperature 1 dB 55Cto +125C

Noise figure 7 dB I400O source impedance atbUMHZ

79

SL532C

TYPICAL APPLICATIONFive stage strip

Input signal for full limiting

Limited output

300>V rms-57dBm1Vp-p

Phase shift (VIN -57 --MOdBm) 3typ.

H

The recommended output buffer amplifier to drive 50fi loads is the SL560C

Fig.3 Five stage IF strip

CIRCUIT DESCRIPTION ABSOLUTE MAXIMUM RATINGSThe SL532 uses a long-tailed pair limiting amplifier

which combines low phase shift with a symmetrical limit-ing characteristic. This is followed by a simple emitterfollower output stage. Each stage of a strip is capable ofdriving to full output a succeeding SL532 but a bufferamplifier is needed to drive lower impedance loads. Noexternal decoupling capacitors are normally required butfor use below 10MHz extra decoupling can be added onpins 1 and 5. Bias for the long-tailed pair is provided byconnecting the bias (pin 2) to the decoupled supply (pin 1).

Supply voltageStorage temperature rangeOperating temperature range

+ 15V-55Cto + 150C-55Cto + 125C

80

SL541B

V Semiconcluctors.

SL541BHIGH SLEW RATE OPERATIONAL AMPLIFIERS

The SL541 is a monolithic amplifier designed for optimumpulse response and applications requiring high slew rate

with fast settling time to high accuracy. The high open loopgain is stable with temperature, allowing the desired closed

loop gain to be achieved using standard operational

amplifier techniques. The device has been designed foroptimum response at a gain of 20dB when no compensationis required. The SL541B has a guaranteed input offset

voltage of 5mV maximum and replaces the SL541C.The SL541B is tested in two circuit applications (A and B).

FEATURES

High Slew Rate: 1 75V/ msFast Settling Time: 1% in 50nsOpen Loop Gain: 70dB (SL541 B)Wide Bandwidth: DC to 1 00MHz at 1 0dB GainVery Low Thermal Drift: 0.02dB/CTemperature Coefficient of Gain

Guaranteed 5mV input offset maximumFull Military Temperature Range (DIL Only)

Package: 10 Lead TO-51 4 Lead DIL Ceramic

APPLICATIONS

Wideband IF AmplificationWideband Video AmplificationFast Settling Pulse Amplifiers

High Speed IntegratorsD/A and A/D ConversionFast Multiplier Preamps


Supply voltage (V + to V -) 24VInput voltage (Inv. I/P to non inv. I/P)

o

9VStorage temperature 55C to +175CChip operating temperature +1 75COperating temperature

:

Thermal resistancesChip-to-ambient : TO-5

DILChip-to-case: TO-5

DIL

TO-5: -55Cto +85'DIL: -55Cto +125'

220C/W125C/W60C/W40C/W

(BOTTOM VIEW)

INPUT EMITTER DEGENERATION

(RESISTANCE COMPENSATION)

Vce SUPPLY

CASE (-VE SUPPLY)

COMPENSATION

+ V SUPPLY

*[1NC[ 2

VERTING I/P [ 3

EARTH[ *

-Vet SUPPIY [ 5

SUBSTRATE [

KC[7

TZ7-14 ]nc

13 ]Rc

CM10

] MW-MV.I/P

].Vcc SUPPLY

] COMPENSATION

]]0UTPUT

(TOP VIEW) DG14


Fig. 2 SL541 circuit diagram (TO-5 pin nos.)

81

SL541B


Tamb = 25 CRc =0fiTest circuits: see Fig.8

Characteristic CircuitValue

Units ConditionsMln. Typ. Max.

Static nominal supply current A,B 16 21 mAInput bias current A,B 7 25 /"AInput offset voltage A,B 5 mVDynamic open loop gain A 45 54 dB 600O load

B 60 71 dBOpen loop temperature coefficient A,B -0.02 dB/CClosed loop bandwidth (-3dB) A,B 100 MHz X10 gainSlew rate (4V peak) A,B 100 175 V///S X10 gainSettling time to 1 % A,B 50 100 nsMaximum output voltage

(+ve) A 5.5 5.7 V(-ve) A -1.9 -1.5 V(-We) B 2.5 3.0 V(-ve) B -3.0 -2.5 V

Maximum output current A,B 4 6.5 mAMaximum input voltage

(-tve) A 5 V(-ve) A -1 V Non-inverting(-We) B 3 V modes(-ve) B -3 V

Supply line rejection(-We) AB 54 66 dB(-ve) A,B 46 54 dB

Input offset current AB 9.85 l/ACommon mode rejection A,B 60.7 dBInput offset voltage drift A 25 AV/C

X3 NONINVERTING

.

SL541B

+-VE

\SLEW

' 10% T175 W

RATE O3 85% PI

ER \/ cc - pF

/\J \ -VE

Fig. 4 Slew rate - X10 non-inverting modeInput square wave 0.4V pip

a 4; ._*

A)pf

^ VE*

\l

J

\i-VE

\V

/OUT

// y V|N > \5 , / V

//

t(20ns/DIV)

Fig. 6 Output clipping levels - X10 non-inverting modeInput moderately overdriven, so that ouput goes intoclipping both sides

t (20ns/ DIV)

Fig. 5 Settling time - X10 non-inverting mode

INPUT SIIP

"

-VE

VE

Fig. 7 Output clippings levels -X10 non inverting mode.Output goes from clipping to zero volts. V, = 3V peakstep, offset +veor ve.

CIRCUIT A

+INPUT +15V

+MPUT +1JV

o SSiOp a

rrn ftn rrn

DYNAMIC TEST CIRCUITRC>22nCc-0pF

c'o. 8 Test circuits

83

SL541B

TEST CONDITIONS AND DEFINITIONSBoth slew rate and settling time are measures of an

amplifier's speed of response to an input. Slew rate is aninherent characteristic of the amplifier and is generallyless subject to misinterpretation than is settling time,which is often more dependent upon the test circuitthan the amplifier's ability to perform.Slew rate defines the maximum rate of change of

output voltage for a large step input change and isrelated to the full power frequency response (fp) by therelationship.

S = 2nfpEwhere E is the peak output voltage

Settling time is defined as the time elapsed fromthe application of a fast input step to the time when theamplifier output has entered and remained within aspecified error band that is symmetrical about the finalvalue. Settling time, therefore, is comprised of an initialpropagation delay, an additional time for the amplifierto slew to the vincinity of some value of output voltage,plus a period to recover from overload and settle within

Fig. 9 Non-saturating sense amplifier (30V/ \is for 5mV)Note: the output may be caught at a pre-determinedlevel. (10-5 pin nos.J

the given error band.The SL541 is tested for slew rate in a X10 gain

configuration.

"C = 15

C = 0^

R|_ " V* * 1

00a2V

TAMB " 25 C

;-^

SL550D/G

^^.r SemlcoiMluctoiY

Semlcomluctors

,

SL550 D & GLOW NOISE WIDEBAND AMPLIFIERWITH EXTERNAL GAIN CONTROL

The SL550 is a silicon integrated circuit designed foruse as a general -purpose wideband linear amplifierwith remote gain control. At a frequency of 60 MHz,the SL550C noise figure is 1-8dB (typ.) from a 200 ohmsource, giving good noise performance directly from amicrowave mixer. The SL550 has an external gaincontrol facility which can be used to obtain a sweptgain function and makes the amplifier ideal for useeither in a linear IF strip or as a low noise preamplifierin a logarithmic strip.

External gain control is performed in the feedback

loop of the main amplifier which is buffered on theinput and output, hence the noise figure and outputvoltage swing are only slightly degraded as the gain isreduced. The external gain control characteristic isspecified with an accuracy of 1dB, enabling a well-defined gain versus time law to be obtained.The input transistor can be connected in common

emitter or common base and the quiescent current ofthe output emitter follower can be increased to enablelow impedance loads to be driven.

CAPACITIVEDECOUPLE INPUT INPUT

jrf ?

output Voutput vcc

DC16

Fig. 1 Pin connections (top view)

FEATURES

200 MHz BandwidthLow Noise FigureWell- Defined Gain Control Characteristic

25dB Gain Control Range40dB GainOutput Voltage 0.8Vp-p (Typ.)

APPLICATIONS

Low Noise PreamplifiersSwept Gain Radar IFs

VARIABLE ATTENUATORTRACKMG WITH VARIABLE

GAIN AMP

Fig. 2 Functional diagram

ALL CAPACITORS Mnf (WEECON-

TYPE CAPACITORS >

R2 =30Q SEE OPERATING NOTE

Fig. 3 Test circuit

85

SL550D/G

ELECTRICAL CHARACTERISTICSTest Conditions (unless otherwise stated)

:

f = 30Hz Vs = +6V, Rl = 2000, Ic = 0, Ri = 7500, Tamb = +25C

Characteristic CircuitValue


Voltage gain SL550G 39 42 44 dBSL550D 35 40 45 dB

Gain control characteristic Both See note 1Gain reduction at mid-point SL550G 10 dB Ic = 0.24mA

SL550D 9 dB Ic = 0.2imAMax. gain reduction SL550G 20 25 dB Ic = 2.0mA

SL550D 25 dB Ic = 2.0mANoise figure SL550G 2.0 2.7 dB Rs = 200O

SL550G 3.5 dB Rs = 500SL550D 3.0 dB Rs 2000

Output voltage Both 0.15 Vrms Rl = ooBoth 0.3 Vrms Ri = 750 o

Supply current SL550G 11 13 mA Ri = ooSL550G 15 mA Ri = 750OSL550D 11 20 mA Ri = oo

Gain variation with supply voltage Both 0.2 dB/V Vs = 6 to 9VUpper cut-off frequency(3dB wrt 30MHz) Both 125 MHzGain variation with temperature(see note 2) Both 3 dB Tamb = 55 to +125C

NOTES1

.

The external gain control characteristic is specified in terms offrom zero to the specified current.

2. This can be reduced by using an alternative input configuratio

OPERATING NOTESInput Impedance

The input capacitance, which is typically 12pF at60MHz, is independent of frequency. The input resist-ance, which is approximately 1 .5k at 1 0MHz, decreaseswith frequency and is typically 500 ohms at 60MHz.

Control Input

Gain control is normally achieved by a current into pin2. Between pin 2 and ground is a forward biased diodeand so the voltage on pin 2 will vary between 600 mVat Ic = 1 (iA to 800 mV at Ic = 2 mA. The amplifier gainis varied by applying a voltage in this range to pin 3.To avoid problems associated with the sensitivity of thecontrol voltage and with operation over a widetemperature range the diode should be used to converta control current to a voltage which is applied to pin 3by linking pins 2 and 3.

Minimum Supply CurrentIf the full output swing is not required, or if high

impedance loads are being driven, the current con-sumption can be reduced by omitting Ri (Fig. 3). Thefunction of Ri is to increase the quiescent current of theoutput emitter follower.

High Output Impedance

A high impedance current output can be obtained bytaking the output from pin 6 (leaving pin 7 open-circuit). Maximum output current is 2 mA peak and theoutput impedance is 350Q.

Wide Temperature Range

The gain variation with temperature can be reducedat the expense of noise figure by including an internal

86

the gain reduction obtained when the control current (Ic) is increased

n (see operating note: 'Wide Temperature Range').

300 resistor in the emitter of the input transistor. This isachieved by decoupling pin 13 and leaving pin 12open-circuit. Gain variation is reduced from 3dB to1dB over the temperature range 55C to +125C(Figs. 6 and 7).

Low Input Impedance

A low input impedance (=*25Q) can be obtained byconnecting the input transistor in common base. This isachieved by decoupling pin 1 1 and applying the inputto pin 12 (pin 13 open-circuit).

High Frequency Stability

Care must be taken to keep all capacitor leads shortand a ground plane should be used to prevent any earthinductance common between the input and outputcircuits. The 30Q resistor (pin 14) shown in the testcircuit eliminates high frequency instabilities due to thestray capacitances and inductances which are un-avoidable in a plug-in test system. If the amplifier issoldered directly into a printed circuit board then the300 resistor can be reduced or omitted completely.

1h- vs S^3

Z 30 -20

1 = 120MHIISO*

20 ui so ao no no

TEMPERATURE

SL1523C

T = -55C"

"

T = +t5C

...

?"IH

ITO(n+Dh STAGE

-

I BIAS AND INPUTPINS LINKED)

XFig. 9 Suitable interstage tuned circuit

20 (0 60 M 100 120 U0 KO WO 200FREQUENCY (MHz]

Fig. 8 Input admittance with open circuit output

135

SL1523C

136

APLESSEYHP' Semiconductors

.

SL1613CWIDEBAND LOG IF STRIP AMPLIFIER

SL1613C

The SL1613C is a bipolar monolithic integrated circuitwideband amplifier intended primarily for use in succes-

sive detection logarithmic IF strips, operating at centre fre-

quencies between 10MHz and 60MHz. The devices pro-vide amplification, limiting and rectification, are suitable for

direct coupling and incorporate supply line decoupling.

The mid-band voltage gain of the SL1613C is typically12dB.

FEATURES

Well Defined Gain

4.5dB Noise Figure

High l/P ImpedanceLow O/P Impedance1 50MHz BandwidthOn-Chip Supply Decoupling

Low External Component Count

O/P EARTH [ 1

v[ 2RF OUTPUT [ 3

DET OUTPUT (Rl

8 ] O/P EARTH

7 ] BIAS

6 ] INPUT

S T l/P EARTH

DP8

Fig. 1 Pin connections (top)


Storage temperature rangeOperating temperature rangeMaximum instantaneous voltage

at video outputSupply voltage

-55Cto+l25C-30Cto+85C

+12V9V

APPLICATIONS

Logarithmic IF Strips with Gains up to 108dB andLinearity Better than 2dB

i

ft"j. rJ iti

"">

3 3k ilSp 2'

Fig. 2 Circuit diagram

"X

_

18-0

_

ISO

1 /U'O l/jn

m ttAr-2 12-0 I-\V3 100 > \\\\\5 80o

T=t1l0 L \\\\ _

_

_

_

_

20_

10 6C 100 2

FREQUENCY (MHz)

Fig. 3 Vortsge gain v. frequency

137

SL1613C


Test conditions (unless otherwise stated):Ta = +22C 2CSupply voltage = +6VDC connection between input and bias pins

Characteristic

Voltage gainUpper cut-off frequency (Fig. 3)Lower cut-off frequency (Fig. 3)Propagation delayMax. rectified video output current (Figs. 4 and 5)Variation of gain with supply voltageVariation of maximum rectified outputcurrent with supply voltageMaximum input signal before overloadNoise figure (Fig. 6)Maximum RF output voltageSupply current

Value

Min. Typ. Max

10

0.8

12150521

0.7

251.94.51.2

15

14

1.3

20

Units

dBMHzMHzns

mAdB/V

%VVrmsdBVp-pmA

Conditions

f=30MHz, Rs=10Q.C L=8pF

Rs=10O,CL=8pFRs=10O,CL=8pF

f=60MHz, Vin=500mV rms

See Note 1f=60MHz, R =450Q

Note 1 Overload occurs when the input signal reaches a level sufficient to forward bias the base collector junction of TR1 on peak

-I ^~ i ii-I J* . 10HN,-X~"-~iv jj "^ MMH.

I

1f

K

~\YlVlts^- ~i.~MA i^j ! TxH-J

hi ZjlJi

'III

w "T IV-- "] r~T~"y IA x

INPUT SIGNAL (Vrmil

Fig. 4 Rectified output current v. input signal

30 MHz

60 MHz

DMHz

INPUT. 05V RM

.

-so

AMBIENT TEMPERATURE ("CI

Fig. 5 Maximum rectified output current v. temperature

1 60l

SL1613C

TO In. 1|l" STAGE

Fig. 9 Su/iatofe interstage tuned circuit

Fig. 8 Direct coupled amplifiers

OPERATING NOTES

The amplifiers are intended for use directly coupled, asshown in Fig. 8.The seventh stage in an untuned cascade will be giving

virtually full output on noise.Noise may be reduced by inserting a single tuned circuit

in the chain. As there is a large mismatch between stages asimple shunt or series circuit cannot be used. The choice ofnetwork is also controlled by the need to avoid distortingthe logarithmic law; the network must give unity voltage

transfer at resonance. A suitable network is shown in Fig. 9.The value of C1 must be chosen so that at resonance itsadmittance equals the total loss conductance across the

tuned circuit. Resistor R1 may be introduced to improvethe symmetry of filter response, providing other values are

adjusted for unity gain at resonance.A simple capacitor may not be suitable for decoupling

the output line if many stages and fast rise times are re-quired.

Values of positive supply line decoupling capacitor re-

quired for untuned cascades are given below. Smaller

values can be used in high frequency tuned cascades.

The amplifiers have been provided with two earth leadsto avoid the introduction of common earth lead inductance

between input and output circuits. The equipment designershould take care to avoid the subsequent introduction of

such inductance.

Number of stages

6 or more 5 4 3

Minimum capacitance 30nf 10nF 3nF 1nF

The 500pF supply decoupling capacitor has a resistanceof, typically, 10Q. It is a junction type having a low break-down voltage and consequently the positive supply currentwill increase rapidly if the supply voltage exceeds 7.5V

(See Absolute Maximum Ratings).

Centre frequencyDynamic RangeVideo rise timeBandwidthOutput voltageTypical log accuracy

60MHz-75dBmto+15dBm

70nSecapprox. 20MHz

0-1.5V2dB

Fig. 10 Circuit diagram oflow cost strip

139

SL1613C

140

SL1621C

SL1621CAGC GENERATOR

The SL1621C is anAGC generator designedspecificallyfor use in SSB receivers in conjunction with the SL1610C,SL1611C and SL161 2CRF and IF amplifiers.ln common withother advanced systems it generates a suitable AGC voltagedirectly from the detected audio waveform, provides a hold'

period to maintain the AGC level during pauses in speech,and is immune to noise interference. In addition it willsmoothly follow the fading signals characteristic of HFcommunication.When used in a receiver comprising one SL16lOCana

one SL1612C amplifierand a suitabledetector.the SL1621Cwill maintain the output within a 4dB range for a 110dBrange of receiver input signal.

FEATURES

All Time Constants Set Externally

Easy Interfacing

Compatible with SL161 0/161 1/1612

APPLICATIONS

SSB ReceiversTest Equipment

QUICK REFERENCE DATA

Supply voltage: 6V

Supply current. 3mA


Tost conditions (unless otherwise stated):Supply voltage V

SL1621C

APPLICATION NOTES

The SL1621C consistsofan input AFamplifiercoupled toa DC output amplifier by means of two detectors havingshort and long rise and fall times respectively. The timeconstants of these detectors are set externally by capacitorson pins 5 (Ci ) and 3 (C2).The detected audio signal atthe input will rapidly establish

an AGC level via the 'fast' detector time in ti (see Fig. 3).Meanwhile the long time constant detector output will riseand after t3 will control the output because this detector ismore sensitive.

Input signals greater than approximately 4mV rms willactuate a trigger circuit whose output pulses provide adischarge current for C2.By this means the voltage on C2 can decay at a maximum

rate, which corresponds to a rise in receiver gain of 20dB/s.Therefore the AGC system will smoothly follow signalswhich are fading at this rate or slower. However should thereceiver input signals fade faster than this, or disappearcompletely as during pauses in speech, then the input tothe AGC generator will drop below the 4mV rms thresholdand the trigger will cease to operate. As C2 then has nodischarge path, it will hold its charge (and hence the outputAGC level ) at the last attained value. The output ofthe shorttime constant detector will drop to zero in time t2 after thedisappearance of the signal.

The trigger pulses also charge C3. When the triggerpulses cease, C3 discharges and after ts C2 is dischargedrapidly (in time U) and so full receiver gain is restored. Thehold time, ts is approximately one second with C3 = 1 OOuF.If signals reappear during ts, then C3 will recharge andnormal operation will continue. The C3 recharge time ismade long enough to prevent prolongation of the hold timeby noise pulses.

Fig. 3 shows how a noise burst superimposed on speechwill initiate rapid AGC action via the short time constantdetector while the long time constant detector effectivelyremembers the pre-noise AGC level.The various time constants quoted are for C-| = 50(iF and

C2 = C3 = 1 0OuF. These time constants may be altered byvarying the appropriate capacitors. C1 controls ti , t2; C2controls t3, t4; C3 controls ts.The supply must either have a source resistance of less

than 2Q at LF or be decoupled by at least 500>F so that it isnot affected by the current surge resulting from a suddeninput on pin 1

.

In a receiver for both AM and SSB using an SL1623Cdetector/carrier AGC generator, the AGC outputs of theSL1621CandSL1623Cmay be connectedtogetherprovidedthat no audio reaches the SL1621C inputwhilethe SL1623Cis controlling the system.AGC lines may require some RF decoupling but the total

capacitance on the output should not exceed 1 5000pF orthe impulse suppression will suffer.

NOISE BURST

AUDIOOUTPUTENVELOPE

L_

SHORT TIME CONSTANTDETECTOR OUTPUT (Cll

_LONG TIME CONSTANTDETECTOR OUTPUT IC2)

Fig. 3 Dynamic response of a system controlled by SL1621C AGC generator

142Fig. 4 SL1621C used to control SSB receiver

SL1621C

._.

BiNORMAL AGC

51161 .SLW12

...

/

INPUT (mVcms)

Fig. 5 Transfer characteristic of SL1621C {typical)

Under some conditions, overload of the AGC output mayoccur in a receiver. Possible solutions are shown in Figs.6and 7.

Fig.6 Fig.7

143

SL1621C

144

SL2363/SL2364

ffl Ar LCwwC*^P Semiconductoi

YSemiconductors

.

SL2363C & SL2364CVERY HIGH PERFORMANCE TRANSISTOR ARRAYS

The SL2363C and SL2364C are arrays of transistorsinternally connected to form a dual long-tailed pair with tail

transistors. They are monolithic integrated circuits manu-

factured on a very high speed bipolar process which has a

minimum useable fr of 2.5 GHz, (typically 5GHz).The SL2363 is in a 10 lead TO5 encapsulation.The SL2364 is in a 14 lead DIL plastic encapsulation.

FEATURES

Complete Dual Long-Tailed Pair in One Package.

Very High ft - Typically 5 GHzVery Good Matching Including Thermal Matching

APPLICATIONS

Wide Band Amplification Stages

1 40 and 560 MBit PCM SystemsFibre Optic Systems

High Performance Instrumentation

Radio and Satellite Communications


Test conditions (unless otherwise stated):

Tamb = 22C 2C

Characteristics

BVCBOLVCEObveboBVciOhFEfTAVbe (See note 1)avbe/tambCcBCCI

Value

Min.

1062.516202.5

Typ.

2095.0408052

-1.7

0.51.0

SL2363C CM10

SL2364C DP14

Fig. 1 Pin connections (top view)

Max.

0.81.5

Units

VVVV

GHzmV

mV/CPFPF

Conditions

Iq= 10uAIC = 5mAIE = 10uAIC= 10uAIC = 8mA, VcE = 2VIC (Tail) = 8mA, VCE=2VIC (Tail) = 8 mA, Vqe = 2VIC (Tail) = 8 mA, VcE = 2VVCB =VCI =0

NOTE 1 . AVBE applies to) VBEQ3 - VBEQ4J and | VBEQ5 - VBEQ6

1

145

SL2363/SL2364

TYPICAL CHARACTERISTICS

IC(mA)

Fig. 2 Collector current

ABSOLUTE MAXIMUM RATINGSMaximum individual transistor dissipation 200mW

fT NORMALISED AT .JOCCE IVIC - 4-5mA

TEMPERATURE (C)

Fig. 3 Chip temperature

Storage temperature 55C to + 1 50CMaximum junction temperature + 1 50CPackage thermal resistance (C/W):Chip to case 65 (CM 10)Chip to ambient 225(CM10) 175(DP14)VCBO = 10V. VEBO = 2.5V. VQEO = 6V. VciO = 15V, IC (any one transistor) = 20mA

The substrate should be connected to the most negativepoint of the circuit to maintain electrical isolation betweenthe transistors.

146

SL3045/SL3046

SL3045C SL3046CGENERAL PURPOSE NPN TRANSISTOR ARRAY

The SL3045C and SL3046C are monolithic arrays of fivegeneral purpose transistors arranged as a differential pair

and three isolated transistors. The arrays are available inceramic (SL3045C) or plastic (SL3046C) 14 lead DILpackages.

FEATURES

5 General Purpose Monolithic Transistors

Good Thermal TrackingWide Operating Current RangeSuitable for Operation from DC to VHFLow Noise Performance 35dB at 1 kHz.

!

tE"3V

,

lC (mA)

Fig. 2 Typical small signal currant gain {common emitter vs.collector current)

VCC-3V

lc(mA)

Fig. 3 Base current matching vs. collector current

14 13 12 11 10 8r-i r-i qi

r-tf

DG14DP14


vce = 3v

I

VK^/

/-//

4VBE /

IC

SL3045/SL3046


Tamb =22C2C

Characteristic SymbolValue


Static characteristics

Emitter base leakage Iebo 0.1 1 UK Veb = 6VCollector emitter breakdown LVceo 15 20 V Ic = 1mACollector-base breakdown BVcbo 20 50 V Ic = 10/yACollector-subtrate breakdown BVcio 20 70 V Ic = 1C|uACollector cut off current ICEO 0.5 M Vce = 10V, Ib =

ICBO 40 nA Vcb = 10V, Ib =Base emitter voltage Vbe(ON) 0.71 V Vce = 3V, Ic = 1mACollector-emitter saturation Vce(SAT) 0.23 V Ib = 1mA, Ic = 10mAStatic forward current-transistor

ratio Hfe

40120

100

50

Vce = 3V, Ic = 10mAVce =3V, Ic = 1mAVce = 3V, Ic = 1QuA

Input offset current differential pair ho 0.2 2 /iA Vce =3V, Ic = 1mAInput offset voltage differential pair AVbei 0.35 5 mV Vce =3V, Ic = 1mAInput offset voltage isolated

transistors AVBE2 0.45 5 mV Vce =3V, Ic = 1mATemperature coefficient of input dAVBE

offset voltage dT 2 /uVC Vce =3V, Ic = 1mATemperature coefficient of base dVBE(ON)

-1.8 mWC Vce =3V, Ic = 1mAemitter voltage dT

Dynamic characteristicsWideband noise figure NF 3.25 dB f = 10Hz to 10kHz

Vce = 3V, Ic = IOQuASource resistance = 1 kfi

Forward transfer admittance Yfe 31-J1.5 mmhoInput admittance Yie 0.3-J0.04 mmho f = 1 MHzOutput admittance Yoe 0.001 +J0.03 mmho Vce =3V, Ic = 1mAReverse transfer admittance Yre O.OOO-jO.003 mmhoForward current transfer ratio hfe 110Short circuit input impedance hie 3.5 kO.Open circuit output admittance hoe 15.6 A

SL3127

Semiconductors

SL3127CHIGH FREQUENCY NPN TRANSISTOR ARRAY

The SL3127C is a monolithic array of five high frequencylow current NPN transistors in a 16 lead DIL package. Thetransistors exhibit typical frs of 1.6GHz and wideband noise

figures of 3.6dB. The SL3127C is pin compatible with theCA3127.

FEATURES

fT Typically 1 .6 GHzWideband Noise Figure 3.6dB

VBE Matching Better Than 5mVDP16

Fig.1 Pin connections SL3127

APPLICATIONS

Wide Band Amplifiers

PCM RegeneratorsHigh Speed Interface Circuits

High Performance Instrumentation Amplifiers

High Speed Modems

10

_

X9. in

^^-

_

0-'

COLLECTOR CURRENT (mA)

Fig. 3 Transition frequency (rT ) v. collector current (VCB=2V,t=200MHz)

149

SL3127

ELECTRICAL CHARACTERISTICSTest cotfHIom (unless otrierwte* stated):T* =22C2C

Characteristic Symbol Value Units ConditionsMHn. Typ. Max.

SMic characteristicsCollector base breakdownCollector emitter breakdown

BVcboLVceo

2015

3018

VV

Ic = 10/iA, Ie =

Ic = 1mA, Ib =Ic = 10//A, Ir = Ie =

Ib = 10//A, Ic = Ie =

Vce = 6V, Ic = 1mA

Collector substrate breakdown (isolation) BVcra 20 55 VBase to isolation breakdownBase emitter voltage

BVbioVbe

100.64

200.74 0.84

VV

Collector emitter saturation voltage Vce(SAT) 0.26 0.5 V Ic = 10mA, Ib = 1mAEmitter base leakage current Iebo 0.1 1

VVeb = 4V

Base emitter saturation voltage Vbe(SAT) 0.95 Ic = 10mA, Ib = 1mABase emitter voltage difference, AVbe 0.45 5 mV Vce = 6V, Ic = 1mAall transistors

Input offset current

Temperature coefficient of AVbeAIbdAVBEdT

0.2

2.0

3

vv/cVce = 6V, Ic = 1mAVce = 6V, Ic = 1mA

Temperature coefficient of Vbe dVBEdT

-1.6 mV/C Vce =6V, Ic = 1mA

Static forward current ratio Hfe 3535

95100

Vce = 6V, Ic = 5mAVce = 6V, Ic = 0.1mA

Collector base leakage Icbo40 100

0.3 nAVce =6V, Ic = 1mAVcb = 16V

Collector isolation leakageICIO 0.6 nA Vci = 20V

Base isolation leakageI BIO 100 nA Vbi = 5V

Emitter base capacitance Ceb 0.4 PFPF

PF

Veb = 0VCollector base capacitance CCB 0.4 Vcb = 0VCollector isolation capacitance Cci 0.8 Va =0V

Dynamic characteristicsTransition frequency fT 1.6 GHz Vce = 6V, Ic = 5mAWideband noise figureKnee of 1/f noise curve

I

NF 3.61

dBkHz

f = 60MHz \ Vce = 6V[ Ic = 2mA) Rs =2000

ABSOLUTE MAXIMUM RATINGSThe absolute maximum ratings are limiting values above

which operating life maybe shortened or specified para-meters may be degraded.

All electrical ratings apply to individual transistors.Thermal ratings apply to the total package.The isolation pin (substrate) must be connected to the

most negative voltage applied to the package to maintainelectrical isolation.VC8 = 20voltVE8 = 4.0 voltVCE = 15voltVCI =20 voltIc = 20 mAMaximum individual transistor dissipation 200 mWattStorage temperature

-55C to 150CMax junction temperature 150C

Package thermal resistance (C/watt):-Package Type DG16 DP16Chip to case 40Chip to ambient 120 180

NOTE:If all the power is being dissipated in one transistor, thesethermal resistance figures should be increased bv100C/watt. '

150

SL3127

e 10

COLLECTOR BASE VOLTAGE (V)

Fig. 4 Transition frequency [tT) v. collector base voltage

(IC = 5mA,Frequency = 200MHz)

3-2

I

.,

2-4

VCB"V ic -s 5V20

XO 16 VCB 2Vlc 5mA

1-2 SOS

0-4

20 1 1680 60 40

TEMPERATURE (*C)

Fig. 5 Variation of transition frequency (fT ) *"ri temperature

151

SL3127

TO

SO

10

1 J | 1

100 nA A IOuA,100pA

COLLECTOR CURRENT

Fig. 6 DC current gain v. collector current

DO

10OMHz L

Fig. 7 Zfj (derived from scattering parameters) v. frequency {Zn -"-&$')

152

SL3145

^^P' SenriconductoiSemiconductors

.

SL3145C,E1.2GHz HIGH FREQUENCY NPN TRANSISTOR ARRAYS

The SL3145C is a monolithic array of five high frequencylow current NPN transistors. The SL3145C consists of 3isolated transistors and a differential pair in a 14 lead DILpackage. The transistors exhibit typical frs of 1.6GHz andwideband noise figures of 3.0dB. The device is pincompatible with the SL3045C. The SL3145E has guaranteedCcb and fr figures.

FEATURES

fj Typically 1 .6 GHzWideband Noise Figure 3.0dB

VBE Matching Better Than 5mV

APPLICATIONS

Wide Band AmplifiersPCM RegeneratorsHigh Speed Interface CircuitsHigh Performance Instrumentation Amplifiers

High Speed Modems

DG14DP14

Fig.1 Pin connections SL3145

Ordering Information

SL3145C-DG CeramicSL3145C-DP PlasticSL3145E-DP Plastic

10 n r 1

_.

_

IP. 1-0

-

to 10

COLLECTOR CURRENT

SL3145


Tamb =22C 2C

Characteristic Symbol Value Unite ConditionsMin. Typ. Max.

Static characteristics

Collector base breakdown BVcbo 20 30 V Ic = 10M,Ie =Collector emitter breakdown LVceo 15 18 V Ic = 1mA,lB =Collector substrate breakdown BVcio 20 55 V Ic = 1QuA,Ir = Ie =(isolation)

Base to isolation breakdown BVbio 10 20 V Ib = 10//A,lc = Ie =Base emitter voltage Vbe 0.64 0.74 0.84 V Vce =6V,lc = 1mACollector emitter saturation voltage Vce(SAT) 0.26 0.5 V Ic = 10mA,lB = 1mAEmitter base leakage current Iebo 0.1 1 //A Veb = 4VBase emitter saturation voltage Vbe(SAT) 0.95 V Ic = 10mA,lB = 1mABase emitter voltage difference, AVbe 0.45 5 mV Vce =6V,lc = 1mAall transistors except TR1.TR2Base emitter voltage difference AVbe 0.35 5 mV Vce = 6V,lc = 1mATR1, TR2Input offset current AIb 0.2 3 A/A Vce = 6V,lc = 1mA(except for TR1, TR2)Input offset current TR1, TR2 AIb 0.2 2 M Vce = 6V,lc = 1mATemperature coefficient of AVbe dAVBE 2.0 AfV/C

Temperature coefficient of Vbe dVBE -1.6 mV/C Vce = 6V,lc = 1mA

Static forward current ratio Hfe 40 100 Vce = 6V,lc = 1mACollector base leakage ICBO 0.3 nA Vcb = 16VCollector isolation leakage I CIO 0.6 nA Vci = 20VBase isolation leakage I BIO 100 nA Vbi =5VEmitter base capacitance Ceb 0.4 PF Veb = 0VCollector base capacitanceSL3145C CCB 0.4 PF Vcb. = 0VSL3145E 0.4 1.1 PF Vcb = 0VCollector isolation capacitance Cci 0.8 PF Vci =0VDynamic characteristicsTransition frequency

SL3145C fT 1.6 GHz Vce = 6V,lc = 5mASL3145E 1.2 GHz Vce = 6V,lc = 10mAWideband noise frequency NF 3.0 dB Vce = 2V,Rs = 1kO

Ic = 100/iA,f = 60MHzKnee of 1/f noise curve 1 kHz Vce = 6V,Rs = 200fi

Ic = 2mA


The absolute maximum ratings are limiting values abovewhich operating life maybe shortened or specified para-meters may be degraded.

All electrical ratings apply to individual transistors.Thermal ratings apply to the total package.The isolation pin (substrate) must be connected to the

most negative voltage applied to the package to maintainelectrical isolation.VCB = 20 voltVEB = 4.0 voltVCE = 15voltVcl =20 voltIc = 20 mAMaximum individual transistor dissipation 200 mWattStorage temperature 55C to 1 50CMax junction temperature 1 50C

154

Package thermal resistance (C/watt):-

PackageType DG14 DP14Chip to case 40Chip to ambient 125 180

NOTE:If all the power is being dissipated in one transistor, thesethermal resistance figures should be increased bv100C/watt.

SL3145

ctttttf

r

COLLECTOR BASE VOLTAGE (V)

Fig.3 Transition frequency (fr) v. collector base voltage (Ic = 5mA, frequency = 200MHz)

32

2-4

I *CB" 5VmA

XS 1 S VC8-2V

1C*5mA

^

I

80 W 40 20 40 SO 80 100 120 140 100TEMPERATURE (*C>

Fig.4 Variation of transition frequency (fr) with temperature

155

SL3145

10mA lOOpA

COLLECTOR CURRENT

Fig.5 DC current gain v. collector curent

'a 200

i..

tt10kQ

Voltage gam = g^Upper frequency response 10kQ/4.7nF = 3kHzLower frequency response 680Q/2.2|iF = 300Hz

Fig. 5 SL6270C frequency response

APPLICATION NOTESVoltage gain

The input to the SL6270C may be single ended ordifferential but must be capacitor coupled. In thesingle-ended mode the signal can be applied to eitherinput, the remaining input being decoupled to ground.Input signals of less than a few hundred microvoltsrms are amplified normally but as the input level isincreased the AGC begins to take effect and the outputis held almost constant at 90mV rms over an inputrange of 50dB.The dynamic range and sensitivity can be reduced by

reducing the main amplifier voltage gain. The connec-tion of a 1k resistor between pins 7 and 8 will reduceboth by approximately 20dB. Values less than 680Qare not advised.Frequency responseThe low frequency response of the SL6270C is

determined by the input, output and coupling capaci-tors. Normally the coupling capacitor between pins 2and 7 is chosen to give a 3dB point at 300Hz,

corresponding to 2.2jiF, and the other capacitors arechosen to give a response to 1 00Hz or less.The SL6270C has an open loop upper frequency

response of a few MHz and a capacitor should beconnected between pins 7 and 8 to give the requiredbandwidth.Attack and decay times

Normally the SL6270C is required to respondquickly by holding the output level almost constant asthe input is increased. This 'attack time', the time takenfor the output to return to within 10% of the originallevel following a 20dB increase in input level, will beapproximately 20ms with the circuit of Fig. 4. It isdetermined by the value of the capacitor connectedbetween pin 1 and ground and can be calculatedapproximately from the formula

:

Attack time = 0.4ms/uFThe decay time is determined by the discharge rate of

the capacitor and the recommended circuit gives adecay rate of 20dB/second. Other | values jof (resistancebetween pin 1 and ground can be used to obtaindifferent results.

158

SL6270C

100

II

SL6270C

160

SL6310C

SL6310CSWITCHABLE AUDIO AMPLIFIER

The SL6310C is a low power audio amplifier whichcan be switched off by applying a mute signal to theappropriate pin. Despite the low quiescent currentconsumption of 5mA (only 0.6mA when muted) aminimum output power of 400mW is available into an8Q load from a 9V supply.

FEATURES

Can be Muted with High or Low StateInputs

Operational Amplifier Configuration

Works Over Wide Voltage Range

APPLICATIONS

Audio Amplifier for Portable ReceiversPower Op. AmpHigh Level Active Filter

QUICK REFERENCE DATASupply Voltage : 4.5V to 1 3.6VVoltage Gain : 70dBOutput into 8Q on 9V Supply : 400mW

ABSOLUTE MAXIMUM RATINGSSupply voltage : 1 5VStorage temperature : 55C to +125C

MUTEB'

mm a- ^J|V^ N0 MV. MPUT

Kl-OC ( ) 20-1 INV INPUT

Vcc ^^-JL-^^N EARTHOUTPUT

CM8/S

Fig. 1 Pin connections, SL6310C CM (bottom view)

mmm wput[ 8 ]muteb'

wvmpur[ 2 7 ] MUTE A'

earth[ 3 6 ]output[ 5 ]Vcc

DP8

Fig. 2 Pin connections SL6310C DP (top view)

MUTE'B MOTE A'

11 I'

WOnINPUT O 1|-

I 8 7 6 S

rrTTrir^

-^r

Fig. 3 SL6310C test circuit

161

SL6310C

ELECTRICAL CHARACTERISTICSTest conditions (unless otherwise stated) :

Supply voltage Vcc : 9VIAmbient temperature : 30C to +85CMute facility: Pins 7 and 8 open circuit

CharacteristicValue


Supply current 5.0 1 7.5 mASupply current muted (A) 0.55 1 mA Pin 7 via 1 00k to earthSupply current muted (B) 0.6 0.9 mA Pin 8 VccInput offset voltage 2 20 mV Rssj10kInput offset current 50 500 nAInput bias current (Note 1) 0.2 1 uAVoltage gain 40 70 dBInput voltage range 2.1 V Vcc = 4.5V

10.6 V Vcc = 1 3VCMRR 40 60 dB Rs

SL6310C

FREQUENCY I Hz]

Fig. 6 Gain v frequency

VOLTAGE (V)

Fig. 7 Gain v. supply voltage

1500 / No input

Grade 3 105 120 kHz 390pF timing capacitor

)

Source impedance (pin 4) 25 40 kfJAF output impedance 4 10 kfiLock-in dynamic range 8 kHz 20/A/ to 1mV rms at pin 18External LO drive level 50 250 mV rms At pin 2CrystaTESR

|

25 o 10.8MHz

APPLICATION NOTES

IF Amplifiers and Mixer

The SL6601 can be operated either in a 'straight through'mode with a maximum recommended input frequency of800kHz or in a single conversion mode with an inputfrequency of 50MHz maximum and an IF of 100kHz or tentimes the peak deviation, whichever is the larger. The crystaloscillator frequency can be equal to either the sum ordifference of the two IF's; the exact frequency is not critical.The circuit is designed to use series resonant fundamental

crystals between 1 and 17MHz.When a suitable crystal frequency is not available a

fundamental crystal of one third of that frequency may beused, with some degradation in performance,recommended level is 70mV rms and the unused pin shouldbe left O/C. The input is AC coupled via a 0.01//F capacitor.A capacitor connected between pin 4 and ground will

shunt the mixer output and limit the frequency response ofthe mixer output and limit the frequency response of theinput signal to the second IF amplifier. A value of 33pF isadvised when the second IF frequency is 100kHz; 6.8pF isadvised for 455kHz.

Phase Locked Loop

The Phase Locked Loop detector features a voltagecontrolled oscillator with nominal frequency set by an

170

external capacitor according to the formula

SL6601

The AF output voltage depends upon the % deviation andso, for a given deviation, output is inversely proportional to

centre frequency. As the noise is constant, the signal to noise

ratio is also inversely proportional to centre frequency.

VCO Frequency GradingThe SL6601 is supplied in 3 selections of VCO centre

frequency. This frequency is measured with a 390pF timingcapacitor and no input signal.

Devices are coded 'SL6601C and a 7V, 72', 73' to indicatethe selection.Frequency tolerances are:/1 85 - 100kHz/2 95 -110kHz/3 105 - 120kHz

Note that orders cannot be accepted for any particularselection, but all devices in a tube will be the same selection.

Squelch Facility

When inputs to the product detector differ in phase a seriesof current pulses will flow out of pin 7. The feature can beused to adjust the VCO; when a 1mV unmodulated inputsignal is applied to pin 18 the VCO frequency should betrimmed to maximise the voltage on pin 7.The squelch level is adjusted by means of a preset variable

resistor between pin 7 and Vcc to set the output signal tonoise ratio at which it is required to mute the output. Thecapacitor between pin 7 and ground determines the squelchattack time. A value between 10nFand 10j/Fcan be chosen togive the required characteristics.

i-fi-ii-irSnr-ii-ii-iII IT W IS 14 13 12

Fig.3 Using an external PNP in the squelch circuit

TYPICAL CHARACTERISTICS

I "L

DEVPFM.TUTIONOOlkHANOW

1*

DTH1

i2n

FMAF

-M0 -1M -100 -00 -m -70 -SO -40 -30 -20 -10

INPUT LEVEL (dBm) AT PIN 18

INPUT VOLTAGE LEVEL (dBm) AT PIN 1*

Fig.5 Typical SINAD(signal + noise + distortion!noise + distortion)

Operation at signal to noise ratios outside the range 5-

18dB is not recommended. Where the 'front end' noise ishigh (because of very high front end gain) the squelch maywell never operate. This effect can be obviated by sensiblereceiver gain distribution.The load on the squelch output (pin 6) should not be less

than 250kO. Reduction of the load below this level leads tohysteresis problems in the squelch circuit.

The use of an external PNP transistor allows hysteresis tobe increased. See Fig.3. The use of capacitors greater than1000pF from pin 6 to ground is not recommended.

Outputs

High speed data outputs can be taken direct from pins 1

1

and 12 but normally for audio applications pin 8 is used. Afilter network will be needed to restrict the audio bandwidthand an RC network consisting of 4.7kO and 4.7nF may beused.

Layout Techniques and Alignment

The SL6601 is not critical in PCB layout requirementsexcept in the 'straight through' mode. In this mode, the inputcomponents and circuits should be isolated from the VCOcomponents, as otherwise the VCO will attempt to 'lock' toitself, and the ultimate signal to noise ratio will suffer.The recommended method of VCO adjustment is with a

frequency measurement system on pin 9. The impedancemust be high, and the VCO frequency is adjusted with noinput signal.

Fig.4 SL6601 application diagram(1st IF = 10.7MHz, 2nd IF = 100kHz)

[\I

L

SL6601

\

.,

I 85

GUARANTEEDOPERATIVE

AREA

J . TVPIOr MINIML LM

-30

VARIATION WITHTEMPERATURE

Vcc = 7V

sy

VARIATION WITSUPPLY VOLTA(

T = 2S'CJ^s*-^^^

jI

SUPPLY VOLTAGE (V)

Fig.7 Supply voltage v. temperature

Vco FREQUENCY DRIFT (%)Fig.8 Typical VCO characteristics

t

z \V-H LOC PFILTIATION

JDIkl

:R6Jk3kHz

2.2n

csS \

FM

zo

>

v3o(A \

^

INPLTT LEVEL (dBm) AT PIN 18

Fig.9 Typical squelch current v. input level

-10

-20

-40

-50

-60

-70

80

2I I

Ml IF = 100kH2za

_Oli

-W-

JZl

IF AMPLIFIERIF AMPLIFIER

07

V r%^rir

CCT

LJ3 Lil t

INTERSTAGECOUPLINGTERMINALS

OiorDELAYEO IF

AGC OUTPUTOUTPUT

TJi Cli O?MIXER MIXER LOCALINPUT OUTPUT OSC

Fig.2 SL6700A block diagram

177

SL6700A

ELECTRICAL CHARACTERISTICSTest conditions (unless otherwise stated):Tamb-55C to +125C Test circuit Fig.6. Modulation frequency 1kHz

CharacteristicValue

Units ConditionsMln. Typ. Max.

Supply voltage 4 7 V Optimum performance at 4.5VSupply current 3.5 7 mAS/N ratio 40 dB 1mV input 80% modulationTH distortion 3 5 % 1mV input 30% modulationSensitivity 10 5 AV 10dBS + N/N ratio, 30%Audio output level change 6 10 dB 10//Vto50mVinput80%AGC threshold 5 //VAGC range 80 dBAF output level 20 40 mV rms 30 % modulation 1mV inputDelayed AGC threshold 10 mV rms 80 % modulationDynamic range 100 dB Noise floor to overloadIF frequency response 15 25 MHz 3dB gain reductionIF amplifier gain 40 50 60 dB 10.7MHz (both amplifiers cascaded)Detector gain 40 46 55 dB 455kHz 80% AMDetector Zm pin 13 2 4 6.8 kfiIF amplifier Zm pin 18 1.8 3 4.5 kfiNoise blank level 4.0 V Logic 1

0.3 V LogicNoise blank duration 300 400 500 /JS C pin 12 = 30nF,R pin 12-11 = 18kMixer conversion gain 1.0R 1.2R 1.5R kfi R is load resistor in kfiMixer Zm (Signal) 2 3 5 kfiMixer Zm (L.O.) 3 5 8 kfiMixer L.O. injection 50 100 150 mV rms fc = 10.245MHzDetector output voltage change 6 8 8.2 dB 1 mV rms input, modulation increased

from 30% to 80%

OPERATING NOTES

The noise blank duration can be varied from the suggestedvalue of 30/js using the formula: Duration time = 0.7CR,where R is value of resistor between pins 1 1 and 1 2 and C isvalue of capacitor from pin 12 to ground.There is no squelch in the SL6700A and the delay in the

delayed AGC is too large to make this output suitable.Squelch is best obtained from a comparator on the AGCdecoupling point, pin 16.The IF amplifiers may be operated at 455kHz giving a

single conversion system.The mixer may also be used as a product detector. Further

application information is available on request.The mixer may also be used as a product detector. Further

application information is available on request in ApplicationNoteAN1001.

TYPICAL DC PIN VOLTAGES(Supply 4.5V, Input 1mV)

178

Pin Voltage Pin Voltage

1 2.25V 10 4.5V2 2.09V 11 3.7V3 3.68V 12 OV4 0.7V 13 0.77V5 0.6V 14 1.5V6 3.7V 15 1.0V7 1.5V 16 0.7V8 4.3V 17 OV9 1.5V 18 0.7V

10011""' m0"

^%

X

t 17 16 IS U 13 12 11 10

SL6700A

fl"

"Y10-245 M*

2U/MTAP AT 257.Ou* 75

Fig.3 SL6700A AM double conversion receiver with noise blanker

SL6700A

t

PIN 5 1 kA LOAD

1/

+ 40 + 60

INPUT (dBjjV RMS]

Fig.4 Typical delayed AGC output variation with input signal(f = 10.7MHz, 30% modulation)

m +50

o

30

5Z

+20

9 "

s

(

:

D "'

1 1

VSUPPLY = tivm too "

z

t

m

! 11 '

r^H t

0-23/0-41(0009/0-016)

17-62 (0-3)

14 LEAD PLASTIC DIL DP14

200

i

c'u u u u u u u u1

16

22 00/18-80

9^

t

7 1 MAX(0-280)

o

oinp

z

1

OO

o

zz

" (0-866/ 0740)o

jinnjinnrm \1 L_l

I7

|

I 1.1/M h\J-\)-\J-\J-\f-\ "

!1

38/0 61'"(0-015/0-024)

1

1

7 PITCHESNON ACCUMULATIVE

I '

23/0 41m1

(0 009/0016)"

7-63(0-3)

2 52/2 56(0-099/0101)

CRS NOM


3

fcfmroi(0-015/0-024)

8 PITCHESNON ACCUMULATIVE

2-52/2-56(0099/0-101)


201

PlesseySemiconductorsWorld Wide

203

Sales officesBELGIUM, NETHERLANDS, LUXEMBOURG

Plessey Semiconductors, Avenue de Tervuren 149, Box 2, Brussels 1 150, Belgium.Tel: 02 733 9730 Tx: 22100

FRANCE Plessey Semiconductors, Z.A. de Courtaboeuf, rue de Quebec,B.P. No. 142, 914 - Les Ulis Cedex.Tel: (6) 446-23-45 Tx: 692858F

ITALY Plessey Trading SpA, Corso Garibaldi 70, 201 21 Milan. Tel: 3452081Tx: 331347

NORTH AMERICA Plessey Semiconductors, 1641 Kaiser Avenue, Irvine, California 92714, USA.Tel: 714 540 9979 Twx: 910 595 1930Plessey Semiconductors, 2525 Oakton Street, Suite A-13, Arlington Heights,Illinois 60005 USA. Tel: (312) 437 1860 Twx: 910 687 1484Plessey Semiconductors, 89 Marcus Blvd., Hauppauge, N.Y., 1 1787 USA.Tel: 516 273 3060 Twx: 96 1419Plessey Semiconductors, 7094 Peachtree Industrial Blvd., Suite 295,Norcross, GA 30071 USA. Tel: 404 447 6910 Twx: 70 7309Plessey Semiconductors, 710 Lakeway, Suite 265, Sunnyvale, CA 94086 USA.Tel: 408 245 9890Plessey Semiconductors, 112 East High Street, Hicksville, Ohio 43526 USA.Twx: 810 490 2551

SOUTH AFRICA Plessey South Africa Ltd., Forum Building, Struben Street, P.O. Box 2416,Pretoria 0001, Transvaal. Tel: 3451 1 Tx: 53 0277

UNITED KINGDOM Plessey Semiconductors Ltd., Cheney Manor, Swindon, Wiltshire SN2 2QW.Tel: (0793) 36251 Tx: 449637

WEST GERMANY, AUSTRIA, SWITZERLANDPlessey GmbH, Altheimer Eck, 10, 8000 Munchen 2, West Germany.Tel: 089 23 62 1 Tx: 0522197

205

AgentsARGENTINA

AUSTRALIA

BRAZIL

EASTERN EUROPE

GREECE

INDIA

JAPAN

HONG KONG

KOREA

NEW ZEALAND

SINGAPORE

SPAIN

SWEDEN

TAIWAN

THAILAND

TURKEY

Electroimpex SA, Guatemala 5991, (1425)Buenos Aires.Tel: 771 -3773/772-9573Plessey Australia Pty Ltd., P.O. Box 2, Christina Road, Villawood,New South Wales 2163. Tel: Sydney 72 0133 Tx: AA20384Plessey Brazil, Rua Ferreira Viana 892, 04761 Sao Paulo, Brazil

plessey linearintegratedcircuithandbook text

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