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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 1
Rochester Institute of TechnologyMicroelectronic Engineering
ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING
PMOS Integrated Circuit Test Results
Dr. Lynn Fuller Microelectronic Engineering
Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041
Dr. Fuller’s Webpage: http://people.rit.edu/~lffeee Email: [email protected]
Dept Webpage: http://www.microe.rit.edu
11-16-2007 PMOS_IC_Test.ppt
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 2
Rochester Institute of TechnologyMicroelectronic Engineering
OUTLINE
IntroductionInverterNOR (2,3,4 input)XOR4:2 Encoder 4 input MultiplexerClocked Data LatchFull Adder1:4 Demultiplexer/DecoderJK Flip FlopAnalog MultiplexerBinary Counter
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 3
Rochester Institute of TechnologyMicroelectronic Engineering
INTRODUCTION
We have been making transistors and integrated circuits at RIT since 1977. We have used Metal Gate PMOS, Bipolar, NMOS, and CMOS technologies.
This document shows some test results for integrated circuits made in Metal Gate PMOS technology.
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 4
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS TEST CHIP FROM FEB 2007 SHORT COURSE
Full Adder
BinaryCounter
RC Oscillator
4 Input Mux
DeMux
JK Flip Flop
XOR
Encoder
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 5
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS INVERTER SPICE SIMULATION
1
2
V2=0to -10
+-
V1=-10+-
M1
Wu/Lu
7
Wd/Ld
Gain = Wd/LdWu/Lu
0.5
M2
Gain=1
Gain=2
Gain=3
Vin
Vout
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 6
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS INVERTER GAIN = 4
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 7
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS 2-INPUT NOR
Test for PMOS Two Input NOR, Gain = 4 or 8
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 8
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS 3-INPUT NOR
In PMOS logic low is 0 volts, logic high is approximately -Vdd
A
CB
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 9
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS 4-INPUT NOR
In PMOS logic low is 0 volts, logic high is approximately -Vdd
A
CB
D
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 10
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS 2 AND 3 INPUT NAND
2 Input NAND
3 Input NAND
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 11
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS 4-INPUT NAND
Note: NAND gates have problems with so many transistors in series between the supply and ground. Here 5 transistors each with Vt ~2 volts in series and a 10 volt supply
Build IC’s with NOR gates(2-input NAND works okay)
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 12
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS 2-INPUT XOR
In PMOS logic low is 0 volts, logic high is approximately -Vdd
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 13
Rochester Institute of TechnologyMicroelectronic Engineering
4:2 PMOS ENCODER
Q0Q1Q2
Qn
Coded OutputLines
Digital Encoder512 inputs can be coded into 9 lineswhich is a more dramatic benefit
A B C D Q1 Q21 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1
INPUTS OUTPUTS
AB
CD
Q1
Q2No Connection
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 14
Rochester Institute of TechnologyMicroelectronic Engineering
4:2 PMOS ENCODER
AB
C
D
Q1
Q2
In PMOS logic low is 0 volts, logic high is approximately -Vdd
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 15
Rochester Institute of TechnologyMicroelectronic Engineering
MUX LAYOUT AND GATE LEVEL SCHEMATIC
I0
I1I2
I3
Q
A
B
A’
B’
A’B’I0
A’BI1
AB’I2
ABI3
25 Transistors
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 16
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS 4-INPUT MULTIPLEXER
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 17
Rochester Institute of TechnologyMicroelectronic Engineering
MUX TEST RESULTS
ABI3I2I1I0
ABI3I2I1I0
In PMOS logic low is 0 volts, logic high is approximately -Vdd
A
B
I3
I2
I1
I0
A
B
I3
I2
I1
I0
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 18
Rochester Institute of TechnologyMicroelectronic Engineering
MUX TEST RESULTS
ABI3I2I1I0
ABI3I2I1I0
In PMOS logic low is 0 volts, logic high is approximately -Vdd
A
B
I3
I2
I1
I0
A
B
I3
I2
I1
I0
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 19
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS CLOCKED DATA LATCH
D FLIP FLOPQ
QBARDATACLOCK
RS FLIP FLOP
QBARS
R QQt+1S
0 0 Qt0 1 11 0 01 1 INDETERMINATE
R
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 20
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS CLOCKED DATA LATCH
In PMOS logic low is 0 volts, logic high is approximately -Vdd
PMOS D - FlipFLop
Clock
Data
Q
Q’
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 21
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS FULL ADDER
A CinB
SUM
COUT
SUM COUTBA
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
CIN
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 22
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS FULL ADDER
Error…. Inverters and Gate Gain is Too Low
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 23
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS FULL ADDER
SUM COUTBA
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
CIN SUM
COUT
A
B
CIN
In PMOS logic low is 0 volts, logic high is -Vcc
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 24
Rochester Institute of TechnologyMicroelectronic Engineering
VERSION 4
Missing contact cut
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 25
Rochester Institute of TechnologyMicroelectronic Engineering
TEST RESULTS FOR VERSION 4
SUM
COUT
A
B
CIN
ERROR
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 26
Rochester Institute of TechnologyMicroelectronic Engineering
TEST RESULTS FOR VERSION 5
SUM
COUT
A
B
CIN
SUM COUTBA0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
CIN
In PMOS logic low is 0 volts, logic high is approximately -Vdd
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 27
Rochester Institute of TechnologyMicroelectronic Engineering
1:4 DEMULTIPLEXER
A
B
I
Q0Q1Q2Q3
A B Q0 Q1 Q2 Q30 0 I 0 0 00 1 0 I 0 01 0 0 0 I 01 1 0 0 0 I
INPUTS OUTPUTS
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 28
Rochester Institute of TechnologyMicroelectronic Engineering
1:4 DEMULTIPLEXER
Q0Q1Q2Q3
A
B
I
Error
In PMOS logic low is 0 volts, logic high is -Vcc
Logic Design Mistake
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 29
Rochester Institute of TechnologyMicroelectronic Engineering
1:4 DEMULTIPLEXER (with error)
Error This should be A instead of A’
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 30
Rochester Institute of TechnologyMicroelectronic Engineering
1:4 DEMULTIPLEXER (version four)
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 31
Rochester Institute of TechnologyMicroelectronic Engineering
TEST RESULT 1:4 DEMULTIPLEXER (version four)
Q0Q1Q2Q3
A
B
I
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 32
Rochester Institute of TechnologyMicroelectronic Engineering
JK FLIP FLOP
Q
K
J
Q
CK
JK TRUTHTABLE
Qn+1K
0 0 Qn0 1 01 0 11 1 Qn
J Q
R
S
Q
Q
Q
CK
J
K
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 33
Rochester Institute of TechnologyMicroelectronic Engineering
JK FLIP FLOP
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 34
Rochester Institute of TechnologyMicroelectronic Engineering
JK FLIP FLOP
In PMOS logic low is 0 volts, logic high is -Vcc
Test ResultsQQbar
CJK
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 35
Rochester Institute of TechnologyMicroelectronic Engineering
BINARY COUNTER USING T TYPE FLIP FLOPS
TOGGEL FLIP FLOP
QQn-10 0 00 1 11 0 11 1 0
T
BA
0 0 0 0 0 1 0 0 10 0 1 0 1 0 0 1 10 1 0 0 1 1 0 0 10 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 11 0 1 1 1 0 0 1 11 1 0 1 1 1 0 0 11 1 1 0 0 0 1 1 1
C
State Table for Binary Counter
Present Next F-FState State Inputs
BA C TA TB TC
ABC 0 1
00
01
11
10
0
0
0
1 1
0
00
InputPulses
TA
ABC 0 1
00
01
11
10
0
1
0
1 1
1
00
TB
ABC 0 1
00
01
11
10
1
1
1
1 1
1
11
TC
A
A
TA
B
B
TB
C
C
Tc
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 36
Rochester Institute of TechnologyMicroelectronic Engineering
T-TYPE FILP-FLOP
RS FLIP FLOP
QBARS
R Q
TOGGEL FLIP FLOP
Q
QBAR
QS
0 0 Qn-10 1 11 0 01 1 INDETERMINATE
R
Q: TOGGELS HIGH AND LOW WITH EACH INPUT
QQn-10 0 00 1 11 0 11 1 0
T
T
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 37
Rochester Institute of TechnologyMicroelectronic Engineering
BINARY COUNTER
TA B
Version 3
Version 4
A T B
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 38
Rochester Institute of TechnologyMicroelectronic Engineering
BINARY COUNTER
Version 5
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 39
Rochester Institute of TechnologyMicroelectronic Engineering
BINARY COUNTER VERSION 3
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 40
Rochester Institute of TechnologyMicroelectronic Engineering
BINARY COUNTER VERSION 4
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 41
Rochester Institute of TechnologyMicroelectronic Engineering
RC OSCILLATOR, INVERTER WITH HYSTERESIS
3.0pF
1
2V19V
+-
M17
3
M3
M2
M4
C1
M5
M6
4M7 M8
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 42
Rochester Institute of TechnologyMicroelectronic Engineering
RC OSCILLATOR LAYOUT
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 43
Rochester Institute of TechnologyMicroelectronic Engineering
RC OSCILLATOR TEST RESULTS
Test Results
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 44
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS ANALOG MUX
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 45
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS ANALOG MUX
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 46
Rochester Institute of TechnologyMicroelectronic Engineering
PMOS ANALOG MUX
Test Results
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 47
Rochester Institute of TechnologyMicroelectronic Engineering
REFERENCES
1. CMOS Analog Circuit Design, Phillip E. Allen, Douglas R. Holberg, Holt, Rinehart and Winston, 1987.
2. Fundamentals of Logic Design, 2nd Edition, Charles H. Roth, Jr.,West Publishing Company, 1979.
3. Microelectronic Circuit Design, Richard C. Jaeger, McGraw-Hill, 1997.
4. Microelectronics, Jacob Millman, McGraw-Hill, 1979.
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© November 16, 2007 Dr. Lynn Fuller
PMOS Integrated Circuit Test Results
Page 48
Rochester Institute of TechnologyMicroelectronic Engineering
HOMEWORK
1. Redesign the XOR using only NOR gates.2. Redesign the Data Latch using only NOR gates.