pmos report

Stanford University

Department of Electrical Engineering

EE 410

INTEGRATED CIRCUIT

FABRICATION LABORATORY

Professor Krishna C. Saraswat

Final Project: CIS/CMOS-II Process and Device

Modeling/Fabrication/Characterization

Deji Akinwande (dejia)

Aaron Gibby (agibby)

Jinendra Raja Jain (jrjain)

Saeroonter Oh (sroonter)

Shiyu Sun (sysun)

Gloria Wong (gloriamt)

March 18, 2005

Contents

1 Introduction 1

2 Analytical Calculations 3

2.1 Field and Gate Oxide Thicknesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.2 Ion Implant Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.3 Junction Depths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.4 Sheet Resistivities of Junctions and Poly-Silicon Gates . . . . . . . . . . . . . . . . . 82.5 Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 TSUPREM-IV Simulation Results 13

3.1 Field and Gate Oxide Thicknesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2 Ion Implant Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Junction Depths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.4 Sheet Resistivities of Junctions and Poly-Silicon Gates . . . . . . . . . . . . . . . . . 143.5 Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Analysis/Simulation Results Comparison and Discussion 23

4.1 Field and Gate Oxide Thicknesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.2 Ion Implant Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.3 Junction Depths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.4 Sheet Resistances of Junctions and Poly-Silicon Gate . . . . . . . . . . . . . . . . . . 244.5 Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 MEDICI Simulation Results 26

5.1 pMOS Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Characterization 29

6.1 Device Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.1.1 nMOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.1.2 pMOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.1.3 MOSCAPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566.1.4 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.2 Process Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746.2.1 Sheet Resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746.2.2 Contact Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796.2.3 Contact Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836.2.4 Continuity and Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3 SEM Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

7 Discussion 97

7.1 Finding The Fault Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977.2 pMOSFET Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977.3 Comparison of Wafers B2 and B5: Gate Etch . . . . . . . . . . . . . . . . . . . . . . 987.4 Suggested Process Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

7.4.1 Wafer B1 Sheet Resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017.4.2 General Process Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8 Conclusions and Comments 103

9 Appendices 105

9.1 Appendix A: CIS/CMOS-II Process Flow by Cross-Section . . . . . . . . . . . . . . 1059.2 Appendix B: Analytical Calculations (Handwritten Notes) . . . . . . . . . . . . . . . 1079.3 Appendix C: MATLAB Simulation Code . . . . . . . . . . . . . . . . . . . . . . . . . 134

9.3.1 nMOS Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349.3.2 nMOS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359.3.3 pMOS Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379.3.4 pMOS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379.3.5 nMOS Metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389.3.6 nMOS Poly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409.3.7 pMOS Metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419.3.8 pMOS Poly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9.4 Appendix D: TSUPREM-IV Simulation Code . . . . . . . . . . . . . . . . . . . . . . 1449.4.1 Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449.4.2 Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449.4.3 Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459.4.4 nMOS Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469.4.5 pMOS Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479.4.6 nMOS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489.4.7 pMOS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499.4.8 nMOS Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509.4.9 nMOS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519.4.10 pMOS Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539.4.11 pMOS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559.4.12 nMOS Metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569.4.13 nMOS Poly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589.4.14 pMOS Metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609.4.15 pMOS Poly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

9.5 Appendix E: MEDICI Simulation Code . . . . . . . . . . . . . . . . . . . . . . . . . 1649.6 Appendix F: Individual Group Member Contributions . . . . . . . . . . . . . . . . . 173

References 174

List of Figures

1 CIS/CMOS-II Cross-Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Dopant Profiles for NMOS Cross-Sections . . . . . . . . . . . . . . . . . . . . . . . . 93 Dopant Profiles for PMOS Cross-Sections . . . . . . . . . . . . . . . . . . . . . . . . 104 Id vs. Vd, 100µm, pMOS Device Simulation . . . . . . . . . . . . . . . . . . . . . . . 265 Id vs. Vd, 20µm, pMOS Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . 276 log(Id) vs. Vg, 100µm, pMOS Device Simulation . . . . . . . . . . . . . . . . . . . . . 277 log(Id) vs. Vg, 20µm, pMOS Device Simulation . . . . . . . . . . . . . . . . . . . . . 288 Test Pad Configuration for nMOSFET Contacts . . . . . . . . . . . . . . . . . . . . 309 nMOS Short Channel Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010 nMOS Narrow Width Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3111 nMOS Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3212 nMOS Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3213 2µm x 2µm nMOS ID − VD Characteristics . . . . . . . . . . . . . . . . . . . . . . . 3414 2µm x 1.5µm nMOS ID − VD Characteristics . . . . . . . . . . . . . . . . . . . . . . 3415 1.5µm x 1.5µm nMOS ID − VD Characteristics . . . . . . . . . . . . . . . . . . . . . 3516 1.5µm x 1µm nMOS ID − VD Characteristics . . . . . . . . . . . . . . . . . . . . . . 3517 100µm x 100µm nMOS ID − VD Characteristics . . . . . . . . . . . . . . . . . . . . 3618 100µm x 100µm nMOS Gate-Drain Short ID − VD Characteristic . . . . . . . . . . . 3719 100µm x 20µm nMOS Gate-Source Short ID − VD Characteristic . . . . . . . . . . . 3820 100µm x 20µm Four-Node nMOS Short ID − VD Characteristic . . . . . . . . . . . . 3921 PMOS1 Id vs. Vd plot used in pMOS analysis . . . . . . . . . . . . . . . . . . . . . . 4122 PMOS1 Id vs. Vg Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4223 PMOS1 log(Id) vs. Vg Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4224 PMOS2 Id vs. Vd plot used in pMOS analysis . . . . . . . . . . . . . . . . . . . . . . 4325 PMOS2 Id vs. Vg Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4326 PMOS2 log(Id) vs. Vg Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4427 IV Characteristics of the smallest functioning device—a 1.5 x 1 µm device . . . . . . 4528 Vt Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4529 Vt Histogram, Wafer B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4630 Vt Histogram, Wafer B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4631 Vt Histogram, Wafer B3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4732 Single Transistor gm Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4733 gm Histogram, Wafer B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4834 Effect of Back Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4935 pMOS Subthreshold Slope Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . 5136 Breakdown Characteristics for 100x100 µm PMOS Device . . . . . . . . . . . . . . . 5437 pMOS SCE Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5538 pMOS NCE Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

39 Representative n+ Poly/p-Well Gate MOSCAP . . . . . . . . . . . . . . . . . . . . . 5940 Representative p+ Poly/n-Substrate Gate MOSCAP . . . . . . . . . . . . . . . . . . 5941 Representative Gate MOSCAP Periphery (BF) . . . . . . . . . . . . . . . . . . . . . 6042 Representative Gate MOSCAP Periphery (DF) . . . . . . . . . . . . . . . . . . . . . 6143 Wafer B5 (Center) - n+ Poly/FOX/p-Well MOSCAP . . . . . . . . . . . . . . . . . . 6144 Wafer B5 (Center) - p+ Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . . 6245 Wafer B2 (Center) - n+ Poly/FOX/p-Well MOSCAP . . . . . . . . . . . . . . . . . . 6246 Wafer B2 (Center) - p+ Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . . 6347 Wafer B1 (Center) - p+ Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . . 6448 Wafer B2 (center) - p+ Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . . 6449 Wafer B2 (Bottom) - p+ Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . 6550 Representative FOX MOSCAP Periphery (BF) . . . . . . . . . . . . . . . . . . . . . 6751 Representative FOX MOSCAP Periphery (DF) . . . . . . . . . . . . . . . . . . . . . 6752 Wafer B3 (Center) - Metal/FOX & LTO/p-Well MOSCAP . . . . . . . . . . . . . . 6853 Wafer B1 (Center) - Metal/FOX & LTO/n-Substrate MOSCAP . . . . . . . . . . . 6854 Wafer B5 (Center) - Metal/LTO/p+ Poly MOSCAP . . . . . . . . . . . . . . . . . . 7055 Wafer B5 (Center) - Metal/LTO/n+ Poly MOSCAP . . . . . . . . . . . . . . . . . . 7056 Representative poly-poly Diode IV Characteristic . . . . . . . . . . . . . . . . . . . . 7257 Poly-poly Diodes Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7258 Tunneling in a pn-Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7359 Four-Point Probe Test Pad Configuration . . . . . . . . . . . . . . . . . . . . . . . . 7460 Van der Pauw Test Pad Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7561 Representative (1µm x 30µm) 4-Point Probe IV . . . . . . . . . . . . . . . . . . . . 7762 Representative (P-well with Oxide) Van de Pauw IV . . . . . . . . . . . . . . . . . . 7763 4-Point Probe Sheet Resistance Wafer Comparison . . . . . . . . . . . . . . . . . . . 7864 Contact Chain Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7965 20 Contact (2µm x 2µm), p+ Poly IV Characteristic . . . . . . . . . . . . . . . . . . 8066 20 Contact (2µm x 2µm), n+ Poly IV Characteristic . . . . . . . . . . . . . . . . . . 8167 Kelvin Contact Resistance Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 8468 Kelvin Contact Resistance - Representative Schottky . . . . . . . . . . . . . . . . . . 8569 Kelvin Contact Resistance - Representative Ohmic . . . . . . . . . . . . . . . . . . . 8670 Kelvin Contact Resistance Representative Completely Linear . . . . . . . . . . . . . 8671 MS Contacts - Doping Dependence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8872 n+ Active Contact - VI Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . 8973 Current vs. Applied Voltage of Metal Lines . . . . . . . . . . . . . . . . . . . . . . . 8974 Cross-Section of 20 µm Gate Width Transistor . . . . . . . . . . . . . . . . . . . . . 9175 Magnified Cross-Section of 20 µm Gate Length Transistor . . . . . . . . . . . . . . . 9276 Surface of Width Series Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9377 Surface of Contact Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

78 Magnified Image of Link within Contact Chains . . . . . . . . . . . . . . . . . . . . . 9479 Surface Image of Continuity Structure: Metal over All Topography . . . . . . . . . . 9480 Magnified Image of Continuity Structure End . . . . . . . . . . . . . . . . . . . . . . 9581 Magnified Image of Continuity Structure Middle . . . . . . . . . . . . . . . . . . . . 9582 Cross-Section of Minimum Dimension Device . . . . . . . . . . . . . . . . . . . . . . 9683 Cross-Section of Wafer B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9984 Cross-Section of Wafer B5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10085 Cross-Section of Wafer B5, 20 µm Gate Length . . . . . . . . . . . . . . . . . . . . . 10086 B1/B2 Sheet Resistance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

List of Tables

1 CIS/CMOS-II Detailed Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Field Oxidation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Sacrificial/Gate Oxidation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Oxide Thickness Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Dopant Ion Implant Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PMOS Source (CS 1) Implant Diffusion Data . . . . . . . . . . . . . . . . . . . . . . 67 PMOS Channel (CS 2) Implant Diffusion Data . . . . . . . . . . . . . . . . . . . . . 68 PMOS Metal (CS 3) Implant Diffusion Data . . . . . . . . . . . . . . . . . . . . . . . 79 PMOS Poly (CS 4) Implant Diffusion Data . . . . . . . . . . . . . . . . . . . . . . . 710 NMOS Source (CS 5) Implant Diffusion Data . . . . . . . . . . . . . . . . . . . . . . 711 NMOS Channel (CS 6) Implant Diffusion Data . . . . . . . . . . . . . . . . . . . . . 712 NMOS Metal (CS 7) Implant Diffusion Data . . . . . . . . . . . . . . . . . . . . . . 713 NMOS Poly (CS 8) Implant Diffusion Data . . . . . . . . . . . . . . . . . . . . . . . 814 Junction Depth Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 NMOS and PMOS Source/Drain Sheet Resistivity Calculations . . . . . . . . . . . . 1116 NMOS and PMOS Poly Sheet Resistivity Calculations . . . . . . . . . . . . . . . . . 1117 Threshold Voltage Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218 Oxide Thickness Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319 Junction Depth Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1320 Sheet Resistivity Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421 Threshold Voltage Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 1422 Oxide Thickness Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2323 Junction Depth Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2424 Sheet Resistance Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425 Threshold Voltage Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2426 Simulated pMOS Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2827 Sample nMOS Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3628 nMOS Analysis, Simulation, and Electrical Characterization Results . . . . . . . . . 3929 HP4145 Setup, Low Vt Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4030 HP4145 Setup, High Vt Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4031 Body Effect Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4932 Extracted Nd values, pMOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5033 Values used in determining channel mobility and Values calculated from experimental

data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5234 Sun and Plummer Model Parameters. [7] . . . . . . . . . . . . . . . . . . . . . . . . 5335 Values used in determining λ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5336 MOS Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5737 MOSCAPs - Theoretical Values for Cox . . . . . . . . . . . . . . . . . . . . . . . . . 58

38 MOSCAP TSUPREM-IV-Extracted Vt . . . . . . . . . . . . . . . . . . . . . . . . . . 5839 n+ Poly/FOX/p-Well MOSCAP Data and Calculations . . . . . . . . . . . . . . . . 6540 n+ Poly/FOX/p-Well MOSCAP Data and Calculations . . . . . . . . . . . . . . . . 6641 Metal/FOX & LTO/p-Well MOSCAP Data and Calculations . . . . . . . . . . . . . 6942 Metal/FOX & LTO/p-Well MOSCAP Data and Calculations . . . . . . . . . . . . . 6943 Wafer B5 - Metal/LTO/Poly MOSCAPs . . . . . . . . . . . . . . . . . . . . . . . . . 7144 Average Sheet Resistivity Measurements for Wafers 2 and 3 . . . . . . . . . . . . . . 7645 Sheet Resistivity Analysis, Simulation, and Electrical Characterization Results . . . 7846 Contact Chains: Wafer-to-Wafer Variation . . . . . . . . . . . . . . . . . . . . . . . . 8147 Contact Chains: Intra-Wafer (B3) Variation . . . . . . . . . . . . . . . . . . . . . . . 8248 Kelvin Contact Resistance Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8549 Continuity Testing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9050 Modeled Process Flows for CIS/CMOS-II Cross-Sections . . . . . . . . . . . . . . . . 10651 Individual Group Member Contributions - Testing/Characterization . . . . . . . . . 17352 Individual Group Member Contributions - Report . . . . . . . . . . . . . . . . . . . 173

CIS/CMOS-II Modeling/Fabrication/Characterization 1 INTRODUCTION

1 Introduction

The CIS/CMOS-II chip is the result of a simplified 1.5µm CMOS process flow designed for theEE410 course at Stanford University. The process flow was executed in the Stanford Nanofabrica-tion Facility (SNF), part of the University’s Paul Allen Center for Integrated Systems.

The CIS/CMOS-II product involves n-type substrates, six (6) mask levels utilizing conventionaloptical lithography with positive photoresist, 40nm gate oxides and 500nm field oxides, dual-implantp-well formation, amorphous “poly’-’silicon gates, single-mask n+ and p+-Source/Drain definition,single-level aluminum/silicon metallization, 600nm PSG passivation, and non-silicided contacts.The dice measure 8mmx16mm in area and contain 1.5µm transistors, inverters, ring oscillators,and a variety of process test structures.

Over the course of ten weeks, the EE410 CIS/CMOS-II chip was simulated, fabricated, testedand characterized according to the prescribed EE410 process schedule [1]. Analytical calculationsof eight chip cross-sections were compared with simulations from TSUPREM-IV software. Outputfrom TSUPREM-IV was then used to model transistor characteristics using MEDICI software.Upon completion of six weeks of fabrication, the fabrication, process, device and SEM test struc-tures of CIS/CMOS-II were evaluated on five wafers, hereafter referred to as B1-B5, along with atest wafer. Those results, and comparisons with the calculations and simulations have been dis-cussed in this report.

Figure 1 presents the product chip with materials and cross-sections indicated [2]. The cross-sections are enumerated as follows: 1) PMOS Source/Drain; 2) PMOS Channel; 3) PMOS Metal;4) PMOS Poly; 5) NMOS Source/Drain; 6) NMOS Channel; 7) NMOS Metal; and 8) NMOS Poly.

Figure 1: CIS/CMOS-II Cross-Sections

Table 1 presents the most relevant features of the CIS/CMOS-II process, along with the pa-rameters for each step used in approximate analysis and TSUPREM-IV/MEDICI modeling.

Akinwande, Gibby, Jain, Oh, Sun, Wong 1

CIS/CMOS-II Modeling/Fabrication/Characterization 1 INTRODUCTION

Table 1: CIS/CMOS-II Detailed Process Flow

Step Specifications1. INITIALIZATION <100> Silicon, P Doping = 8 × 1014 cm−3 (ρ = 5-10 Ω-cm)2. BLANKET IMPLANT P31, Dose = 1.75 × 1012 cm−2, Energy = 100 keV, Tilt = 7

3. FIELD SiO2 (5000A) a. Time = 35 min, T.Start = 800C, T.Final = 1000C, Argonb. Time = 10 min, Temp. = 1000C, DryO2

c. Time = 100 min, Temp. = 1000C, Steamd. Time = 10 min, Temp. = 1000C, DryO2

e. Time = 35 min, T.Start = 1000C, T.Final = 800C, Argon4. PHOTOLITHOGRAPHY #1 Active Area5. ETCH SiO2 (all)6. SACRIFICIAL SiO2 (40 nm) a. Time = 20 min, T.Start = 800C, T.Final = 900C, Argon

b. Time = 5 min, Temp. = 900C, DryO2


e. Time = 15 min, T.Start = 900C, T.Final = 800C, Argon7. PHOTOLITHOGRAPHY #2 P-Well8. P-WELL DOUBLE IMPLANT a. B11, Dose = 5.0 × 1012 cm−2, Energy = 180 keV, Tilt = 7

b. B11, Dose = 1.4 × 1012 cm−2, Energy = 50 keV, Tilt = 7

9. P-WELL DRIVE-IN a. Time = 30 min, T.Start = 800C, T.Final = 1000C, Argonb. Time = 60 min, Temp = 1000C, Argonc. Time = 20 min, T.Start = 800C, T.Final = 1000C, Argon

10. ETCH Sacrificial SiO2 (40 nm + 50% overetch = 60 nm)11. GATE SiO2 (40 nm) a. Time = 20 min, T.Start = 800C, T.Final = 900C, Argon



e. Time = 15 min, T.Start = 900C, T.Final = 800C, Argon12. POLY-SI DEPOSITION (5000A) Poly-silicon13. PHOTOLITHOGRAPHY #3 Poly-silicon14. ETCH Poly-silicon (all)15. PHOTOLITHOGRAPHY #4 N-Select16. N-SOURCE/DRAIN IMPLANT As75, Dose = 5.0 × 1015 cm−2, Energy = 100 keV, Tilt = 7

17. BLANKET IMPLANT BF492 , Dose = 1.0 × 1015 cm−2, Energy = 80 keV, Tilt = 7

18. LTO DEPOSITION (6000A) Low-Temperature Oxide19. LTO DENSIFICATION a. Time = 30 min, T.Start = 800C, T.Final = 950C, Argon



e. Time = 20 min, T.Start = 950C, T.Final = 800C, Argon20. PHOTOLITHOGRAPHY # 5 Contact Holes21. ETCH SiO2 (all)22. AL/SI DEPOSITION (1µm) Al/Si (99%/1%) Alloy23. PHOTOLITHOGRAPHY #6 Metal24. ETCH Al/Si Alloy (all)


CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS

2 Analytical Calculations

2.1 Field and Gate Oxide Thicknesses

The linear-parabolic Deal-Grove model was used to estimate oxide thicknesses [3]. Since oxidesexceed 20nm in target thickness (sacrificial/gate oxides are 40nm thick), the failures of the modelfor thin layers are generally avoided in this analysis. Should oxides thinner than the 20nm limit beneeded, modifications to the Deal-Grove model, such as those provided by Massoud, Han & Helms,and others, would be appropriate. Equations 1-4 present the Deal-Grove model in brief.

x0 =A

2

(√1 +

t + τ

A2/4B− 1

)(1)

τ =x2

i + Axi

B(2)

where

B = C1e−E1

kT (3)B

A= C2e

−E2kT (4)

The constants C1 and C2, along with the activation energies E1 and E2, are defined in [3] and usedto calculate the rate coefficients A, and B

A .Model parameters for the Dry O2 and Steam ambients used during oxidations were calculated

and are provided in 9.2. Table 2 presents the Field Oxidation process in a cumulative fashion.

Table 2: Field Oxidation Process

Ambient Temperature (oC) Time (sec) x0 (µm) Si Consumed (µm)Dry O2 1000 600 0.0072 0.0033Steam 1000 6000 0.5450 0.2477Dry O2 1000 600 0.5463 0.2483

Table 3 presents the Sacrificial/Gate Oxidation process in a cumulative fashion.



Table 3: Sacrificial/Gate Oxidation Process

Ambient Temperature (oC) Time (sec) x0 (µm) Si Consumed (µm)Dry O2 900 300 7.8684E-4 3.5766E-4Steam 900 7200 0.0302 0.0137Dry O2 900 300 0.0309 0.0141

The final FOX thickness is 546.3nm, while the target thickness is 500nm. Since field oxide isgrown for device isolation, this variation is unimportant. However, the final Sacrificial/Gate oxidethickness is 30.0nm, compared to the target value of 40nm. This discrepancy is more importantfor device operation but its effects are not considered here.

Some of the oxidations in the CIS/CMOS-II process flow start with initial SiO2 surface layers.The processes shown in Tables 2 and 3 are given for oxidation of bare Silicon. Calculations forcontinued oxidations account for the decrease in species diffusions through pre-existing oxides.

Note: The actual process flow as performed in SNF incorporates an excess of O2 for the sake ofsafety [1]. Also, species flow rates presumed for the model and those cited in the run sheet differ.These, along with other discrepancies, account for some portion of the difference in calculated anddesired SiO2 thicknesses. It should also be noted that calculations of oxide thicknesses neglectoxidation of the Silicon surface during ramp steps. In most instances, this simplification resultsin negligible error in the hand analysis. TSUPREM-IV process runs were conducted to test theimportance of the ramp steps and verify appropriateness of the ramp omission. Also note that LTOand Thermal oxides are treated identically in this analysis.

Table 4 presents the final total oxide thickness values for each cross-section.

Table 4: Oxide Thickness Calculations

Cross-Section 1 2 3 4 5 6 7 8SiO2 Thickness (µm) N/A 0.0308 1.1588 0.5185 N/A 0.0308 1.1588 0.5185

2.2 Ion Implant Profiles

Implant profiles for both hand analysis and TSUPREM-IV simulations were modeled by symmetricGaussian profiles. The more accurate Pearson distribution is the default model in TSUPREM-IV,but Gaussian profiles are simpler to study. The model used for implantation is derived from [3].Equation 5 presents the Gaussian implant model.



C(x) =Q√

2π∆RP

e− (x−RP )2

2∆R2P (5)

Equation 6 presents the model used for dopant evolution due to annealing (temperature cycling).

C(x, t) =Q√

2π(∆R2P + 2

∑Dt)

e− (x−RP )2

2(∆R2P

+2P

Dt) (6)

Peak range and standard deviation statistics for dopants with different implant energies were takenfrom [3]. Table 5 presents the dopant implant data most immediately relevant.

Table 5: Dopant Ion Implant Calculations

Dopant/Region Energy (keV ) Dose (cm−2) RP (µm) ∆RP (µm)P/Blanket 100 1.75E12 0.127 0.0461B/P-Well 180 5E12 0.469 0.107B/P-Well 50 1.4E12 0.171 0.0628

As/N-Source/Drain 100 5E15 0.0692 0.0261BF2/Blanket 80 1E15 0.0746 0.0353

Note: As per TSUPREM-IV behavior, the BF2 implant was treated as a Boron implant withE′ = 0.2215E and Q′ = 3Q (for damage only) [4]. This correction results in appropriate range andstandard deviation statistics for the heavier implant species.

Attempts were made to include concentration-dependent diffusivities as well, but the complex-ity of dealing with enhanced portions of dopant profiles precluded a reasonable treatment. Thediffusivities and resulting diffusion lengths resulting from these attempts can be found throughoutthe hand analysis materials in 9.2.

Several points should be made with regard to the treatment of implant anneals in this work.Reflection at oxidizing Si surfaces was not considered. Any amount of dopant that diffused towardsthe Si-SiO2 interface was assumed integrated into the growing oxide. Accurately considering re-flection would require modeling of the rate of oxidation at the surface coupled with dopant flux atthe interface.

To consider masking effects, thicknesses of surface oxides and poly-Si layers were used as di-rect offsets in the calculation of implant peaks. Furthermore, individual dopant diffusivities andelectronic and nuclear stopping forces were assumed constant and equal across all material layers,



including poly-silicon and SiO2.Since the silicon surface changes location as a result of oxidation, its position was tracked

throughout the process flow for each cross section. This is necessary when considering the place-ment of dopant profiles relative to other dopants and material layers.

Finally, certain higher-order effects (e.g. dopant segregation, concentration-dependent diffusiv-ity, and oxidation-enhanced diffusion (OED)) were neglected. However, as mentioned, transient-enhanced diffusion (TED) was modeled throughout the process. For Arsenic implant and diffusion,the diffusivity enhancement was multiplied by a factor of 0.4 to account for vacancies-dominateddiffusion mechanism [3]. Equations 7 and 8 present the TED equations used during implant anneals.

CmaxI

C∗I

=1

4πa3C0I

e

“−Eb−EF

kT

”(7)

τenh =4πa3RpQ

d0I

eEb+Em

kT (8)

Tables 6-13 present the total Dt results for each cross section. The data include the final peaklocation for each dopant, considering the location of the top material surface at the time of implant.

Table 6: PMOS Source (CS 1) Implant Diffusion Data

Species Peak Location (µm) Final Dt (cm2)Blanket P 0.127 3.2273E-10

Blanket BF2 0.3201 2.1596E-10

Table 7: PMOS Channel (CS 2) Implant Diffusion Data


Blanket BF2 -0.1799 2.1596E-10



Table 8: PMOS Metal (CS 3) Implant Diffusion Data


Blanket BF2 -0.1809 2.1596E-10

Table 9: PMOS Poly (CS 4) Implant Diffusion Data


Blanket BF2 -0.6809 2.1596E-10

Table 10: NMOS Source (CS 5) Implant Diffusion Data


P-Well Deep Boron 0.7005 5.8879E-10P-Well Shallow Boron 0.4025 5.8879E-10N-Source/Drain As 0.3147 1.9271E-11

Blanket BF2 0.3201 5.3614E-10

Table 11: NMOS Channel (CS 6) Implant Diffusion Data


P-Well Deep Boron 0.7005 5.8879E-10P-Well Shallow Boron 0.4025 5.8879E-10N-Source/Drain As -0.1853 1.9271E-11

Blanket BF2 -0.1799 5.3614E-10

Table 12: NMOS Metal (CS 7) Implant Diffusion Data


P-Well Deep Boron 0.1624 5.8879E-10P-Well Shallow Boron -0.1356 5.8879E-10N-Source/Drain As -0.1863 1.9271E-11

Blanket BF2 -0.1809 5.3614E-10



Table 13: NMOS Poly (CS 8) Implant Diffusion Data


P-Well Deep Boron 0.1624 5.8879E-10P-Well Shallow Boron -0.1356 5.8879E-10N-Source/Drain As -0.6863 1.9271E-11

Blanket BF2 -0.6809 5.3614E-10

Figures 2 and 3 illustrate the final hand/MATLAB-simulated doping profiles for the nMOS andpMOS cross-sections, respectively.

2.3 Junction Depths

Junction depths are obtained directly from the MATLAB simulation output of Figures 2 and 3.Table 14 presents the junction data for each cross-section.

Table 14: Junction Depth Calculations

Cross-Section 1 2 3 4 5 6 7 8Junction Depth (µm) 1.2634 N/A N/A N/A 0.5934 1.7420 1.1725 1.1811

2.4 Sheet Resistivities of Junctions and Poly-Silicon Gates

The sheet resistivity of a diffused layer can be calculated according to Equation 9 [3].

ρS =1

σxj=

1q∫ xj

0 [n(x) − NB(x)] µ[n(x)]dx(9)

However, analytical/numerical integration of diffused profiles is more complicated than necessary



Figure 2: Dopant Profiles for NMOS Cross-Sections



Figure 3: Dopant Profiles for PMOS Cross-Sections



for hand analysis. Instead, Equations 10 and 11 yield a more tractable method for calculating sheetresistivity values for the CIS/CMOS-II process.

ρ =1

q (nµn + pµp)(10)

ρS =ρ

xj(11)

Assuming Gaussian implant distributions naturally leads to the use of Irvin’s Curves to calculateSource/Drain sheet resistivities. Granted, unavoidable error is present in this method, due to theincompleteness of the profiles’ extent into the diffused regions. However, applying Irvin’s Curvesyields acceptable approximations. Table 15 presents the resulting sheet resistivity values for theNMOS and PMOS Source/Drain Regions. NB , NA, and ND refer to the corresponding peakconcentration within the Source/Drain region. Effective conductivity values are obtain from Irvin’sCurves.

Table 15: NMOS and PMOS Source/Drain Sheet Resistivity Calculations

Cross-Section NB (cm−3) NA or ND (cm−3) σ(

1Ω−cm

)xj (cm) ρS

(Ωsq.

)NMOS S/D 6.7411E16 2.9207E20 280 0.5934E-4 60.1859PMOS S/D 2.1046E16 1.8923E19 200 1.2634E-4 39.5758

Sheet resistivity values for the n- and p-poly-silicon layers can be approximated by using Equa-tions 10 and 11 more directly. Grain boundaries in poly-silicon act as “fast diffusion paths” alongwhich atoms travel more rapidly than in bulk crystalline material [3]. Hence, a reasonable approx-imation for sheet resistivity calculation is the uniform doping of poly-silicon at the peak concen-tration. The treatment here assumes that charge carrier mobility in the poly material is half thatin crystalline Silicon [5]. Table 16 presents the resulting sheet resistivity data.

Table 16: NMOS and PMOS Poly Sheet Resistivity Calculations

Cross-Section NA or ND (cm−3) Dominant µ(

cm2

sec

)σ(

1Ω−cm

)xj (cm) ρS

(Ωsq.

)NMOS Poly 1E19 131.5 21.04 0.4721E-4 100.6747PMOS Poly 1E19 36 57.6 0.4271E-4 367.7422



2.5 Threshold Voltages

Equations 12-15 are used to calculate threshold voltages for the CIS/CMOS-II cross-sections.

Vt,n = φMS − QSS

Cox+ 2φF +

KS

Koxxox

√4qNB

KSε0(φF ) (12)

Vt,p = φMS − QSS

Cox+ 2φF − KS

Koxxox

√4qNB

KSε0(−φF ) (13)

φF,n =kT

qln

NA

ni(14)

φF,p = −kT

qln

ND

ni(15)

The doping concentration values at the Silicon surface are used to calculate the correspondingthreshold voltages. This introduces some error, since dopant distributions are non-uniform. QSS

is taken equal to 5E10 cm−2, the value used for TSUPREM-IV simulations. The aluminum workfunction, φM , is equal to 4.05eV, while the Silicon electron affinity, χ is 4.10eV. An intrinsiccarrier concentration, ni of 1.45E10 cm−3 is used. Table 17 presents the resulting threshold voltagecalculations.

Table 17: Threshold Voltage Calculations

Cross-Section Surface Doping (cm−3) Threshold Voltage (V )2 1.5E16 -0.82123 1.5E16 -31.23354 1.5E16 -14.99766 3E16 -0.53427 6E16 31.22038 6E16 22.3424

As expected, the parasitic MOSFETs have much larger threshold voltages than the “normal”devices.


CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS

3 TSUPREM-IV Simulation Results


Oxidation cycles were simulated using the Dry O2, Steam, Dry O2 procedure discussed earlier.Table 18 presents the final TSUPREM-simulated oxide thickness results.

Table 18: Oxide Thickness Simulation Results

Cross-Section 1 2 3 4 5 6 7 8SiO2 Thickness (µm) N/A 0.0366 1.1971 0.5543 N/A 0.0366 1.1971 0.5543


TSUPREM-simulated dopant implants and anneals were obtained using the PD.FULL Method.This Method includes TED (which was simulated by hand calculation), as well as OED and inter-face segregation. The following pages illustrate the TSUPREM results.

3.3 Junction Depths

Table 19 presents the TSUPREM-simulated junction depths for the appropriate cross sections.Aside from the PMOS Source/Drain , no other PMOS regions contain junctions. Additionally,TSUPREM yielded ostensibly poor results for the NMOS Poly and NMOS Metal regions, indicatingthat no P-Bulk existed. It was verified that this is a failing of TSUPREM and not of the processitself.

Table 19: Junction Depth Simulation Results

Cross-Section 1 2 3 4 5 6 7 8Junction Depth (µm) 0.69 N/A N/A N/A 0.23 0.9148 N/A N/A



3.4 Sheet Resistivities of Junctions and Poly-Silicon Gates

TSUPREM-simulated results for sheet resistivities are provided in Table 20.

Table 20: Sheet Resistivity Simulation Results

Cross-Section NMOS Poly NMOS Source PMOS Poly PMOS SourceSheet Resistivity ( Ω

sq.) 28 60 249 52


TSUPREM-simulated results for device threshold voltages are provided in Table 21. As mentionedabove, TSUPREM results indicated the lack of a P-Bulk region for the NMOS Poly and NMOSMetal regions. Hence, no reasonable or meaningful threshold voltage value was obtained for theseregions.

Table 21: Threshold Voltage Simulation Results

Cross-Section 2 3 4 6 7 8Threshold Voltage (V ) -1.032 -38.424 -17.135 0.172 N/A N/A



.


CIS/CMOS-II Modeling/Fabrication/Characterization4 ANALYSIS/SIMULATION RESULTS COMPARISON AND DISCUSSION

4 Analysis/Simulation Results Comparison and Discussion


Table 22 presents the analytical and simulated oxide thickness results.

Table 22: Oxide Thickness Results

Cross-Section 1 2 3 4 5 6 7 8SiO2 Thickness (µm) (calc.) N/A 0.0308 1.1588 0.5185 N/A 0.0308 1.1588 0.5185SiO2 Thickness (µm) (sim.) N/A 0.0366 1.1971 0.5543 N/A 0.0366 1.1971 0.5543

The analytical and TSUPREM-simulated oxide thickness results agree well, save gate oxida-tion. Generally, the hand analysis oxide results are thinner than the simulated values. This is alsoexpected, given the influence of ramp oxidations, variable flow rates, etc. However, both modelsmade use of Deal-Grove and therefore significantly underestimate the gate oxide thicknesses. Thisis likely due to the fact that the model fails for thin oxides. Discrepancies between hand analysisand simulation in this case could be due to modifications to Deal-Grove (e.g. Massoud) employedin TSUPREM to account for more rapid oxidation for thin layers.


As expected, the dopant concentration profiles vary widely between hand analysis results andTSUPREM-obtained curves. The discrepancies are an obvious consequence of neglecting concentration-dependent diffusivities, dopant segregation at interfaces (esp. SiO2 and Si), surface reflection, OED,variable dopant stopping mechanisms and powers among different materials, implant angles, andothers. The consideration of TED, however, likely reduced the error present in the hand analysis.

4.3 Junction Depths

Table 23 presents the analytical and simulated junction depth results.

Cross-Sections 1 and 5 yield relatively reasonable agreement between the hand analysis and sim-ulation results. Discrepancies in these and other junction depths depend largely on segregationeffects at the SiO2-Si interface. This is especially true for Boron, which has a strong tendency tosegregate into the oxide. The omission of B segregation is evident the MATLAB PMOS dopingplots, in which a large P-Type doping profile extends into the Si substrate.



Table 23: Junction Depth Results

Cross-Section 1 2 3 4 5 6 7 8Junction Depth (µm) (calc.) 1.2634 N/A N/A N/A 0.5934 1.7420 1.1725 1.1811Junction Depth (µm) (sim.) 0.69 N/A N/A N/A 0.23 0.9148 N/A N/A

4.4 Sheet Resistances of Junctions and Poly-Silicon Gate

Table 24 presents the analytical and simulated sheet resistance results.

Table 24: Sheet Resistance Results

Cross-Section NMOS Poly NMOS Source PMOS Poly PMOS SourceSheet Resistance ( Ω

sq.) (calc.) 100.6747 60.1859 367.7422 39.5758Sheet Resistance ( Ω

sq.) (sim.) 28 60 249 52

The Source/Drain results for hand analysis and TSUPREM simulations agree well. Thus, themethodology of using Irvin’s Curves ostensibly worked well. However, notable discrepancies existfor the Poly regions. This is likely due to the method of averaging used to approximate a uniformdistribution. Numerical integration would yield the most accurate results in this case.


Table 25 presents the analytical and simulated threshold voltage results.

Table 25: Threshold Voltage Results

Cross-Section 2 3 4 6 7 bf 8Threshold Voltage (V ) (calc.) -0.8212 -31.2335 -14.9976 -0.5342 31.2203 22.3424Threshold Voltage (V ) (sim.) -1.032 -19.010 -17.117 0.172 N/A N/A



PMOS threshold voltage results are in reasonable agreement for hand analysis and TSUPREMsimulations. Values for the parasitic devices are large in both models, while the PMOS Channelthreshold voltage values are acceptably-close. Due to the mentioned issue with TSUPREM’s treat-ment of the P-Bulk, a meaningful comparison cannot be carried out for the NMOS Poly and Metalregions. However, one notable difference regarding the NMOS Channel involves the simulation-obtained result of a depletion-mode device. The discrepancy between the weak enhancement-resultof hand analysis may be an artifact of second-order effects (e.g. segregation).

Generally, differences in threshold voltage values are inevitable given the treatment of surfaceconcentration. Dopant profiles are non-uniform and significant approximations were made in orderto arrive at meaningful values for the hand analysis. Differences in material thicknesses, bandcalculation variances, and the like would also contribute to disagreement between the hand resultsand simulation output.


CIS/CMOS-II Modeling/Fabrication/Characterization 5 MEDICI SIMULATION RESULTS

5 MEDICI Simulation Results

5.1 pMOS Simulation Results

As shown later in Section 6.1.2, fabricated pMOS devices displayed a wide range of characteristicparameters, varying with wafer, die, and transistor size. In order to define a realistic expecta-tion for device performance, pMOS transistors were simulated using Avant!’s 2-D device simulator,MEDICI. In particular, the longest and most common fabricated gate lengths—100 µm, and 20µm, respectively—were chosen as the simulated structures.

The complete script used in simulations can be seen in Section 9.5. Doping profiles were notsimulated using analytic profiles, rather the 1-D outputs from the TSUPREM simulations (see Sec-tion 3.2), were imported, with an approximate XY.RATIO set to .75 to account for lateral spreadingof implanted dopants.

Results of the pMOS simulations are seen in figures 4, 5, 6, and 7. Transistor parameters canbe seen in Table 26. As can be seen in the figures and in Table 26, Short Channel effects, includingDrain Induced Barrier Lowering (DIBL), are absent from the simulations.

Figure 4: Id vs. Vd, 100µm, pMOS Device Simulation



Figure 5: Id vs. Vd, 20µm, pMOS Device Simulation

Figure 6: log(Id) vs. Vg, 100µm, pMOS Device Simulation



Figure 7: log(Id) vs. Vg, 20µm, pMOS Device Simulation

Table 26: Simulated pMOS Parameters

Parameter 100 µm 20 µmVt, low Vd, (V) −1.049 −0.8864Vt, high Vd, (V) −1.059 −0.8757

Subthreshold Slope, (mv/dec) 87.18 88.69


CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION

6 Characterization

6.1 Device Test Structures

6.1.1 nMOSFETs

Introduction

Several nMOS devices were built on five separate wafers using the EE410 CMOS II process.Devices ranging from 100µm x 100µm to 1.5µm x 1µm were evaluated. Only wafer 5 had someworking nMOS devices. The other wafers showed no transistor behavior at all. The current hypoth-esis why the other wafers failed to show a working nMOS is due to over-etching of the source/drainregions using the Drytek plasma etch. Wafer 5 was etched using the P5000 machine with endpointdetection algorithm. A full explanation of this hypothesis is presented later in this section.

The nMOS devices were built in isolated p-wells and are meant to operate as enhancementmode devices. The following parameters were measured (or extracted from measurement):

• Threshold voltages (Vt)• Transconductance (gm)• Channel length modulation (λ)• Small signal output resistance (r0)• Channel doping (NA)• Body effect (γ)• Subthreshold slope (ξ)• Size of smallest functioning device• Small dimension effects - Vt as a function of L and W

Due to a sudden catastrophic failure of all nMOS devices on wafer 5 (after initial testing),additional testing could not be performed to obtain data for extraction of breakdown voltage.After much troubleshooting including wafer probe adjustment and re-calibration and prior years’nMOS device verification, a satisfactory reason for the sudden blowout of nMOS devices on wafer5 is yet to be determined. Furthermore, limited statistical analysis was performed as there wereonly a few working nMOS samples. All measurements are with the source and bulk grounded. Asummary of extracted parameters for several devices is presented at the end of this section. Apicture of the pad arrangement for contacting the transistors is shown in Figure 8.

Threshold Voltage (Vt) and Small Dimension Effects

The threshold voltages were obtained from graphs of ID −VG curves. Specifically, t is the x-axisintercept of the plot of Equation 16.



Figure 8: Test Pad Configuration for nMOSFET Contacts

√ID =

√β (VGS − Vt) (16)

where β = 12µCox

WL for a transistor biased in the saturation region. The threshold voltage

ranged from 0.67V for a 100µm x 100µm device to a minimum of 0.3V for a 100µm x 1.5µm

device. Figures 9 and 10 present the short-channel and narrow-width effects, respectively. Note:Only two data points (W = 1.5µm and W = 100µm) are available for narrow width effect.

Figure 9: nMOS Short Channel Effect

In addition, the subthreshold region was investigated, and the slope was extracted to be about44mv/dec for a 100µm x 100µm device.



Figure 10: nMOS Narrow Width Effect

Transconductance (gm)

The transconductance is a very important parameter for analog applications. It represents theintrinsic small signal gain of the transistor. It is measured as the slope of the ID − VG curve fora transistor biased in the saturation region. Formally gm for a long channel device is given byEquation 17

gm = µCoxW

L(VG − Vt) = 2β (VG − Vt) (17)

The transconductance is plotted in Figure 11 for different lengths with constant width W = 100µm.

The dramatic increase at very short lengths is due to short channel effects (reduction) on Vt

and additional multiplier in Equation 17 resulting from channel length modulation (finite λ).

Channel Length Modulation (λ) and Output Resistance (r0)

Channel length modulation is similarly of interest in analog applications. It models the de-pendence of the drain current on drain voltage. This dependence arises from an increase in thedepletion width around the drain region (as drain voltage increases) consequentially resulting in areduction of the channel length and an increase in drift current. For the popular common-sourceamplifier, r0 represents the intrinsic output resistance and together with gm defines the maximumsmall signal voltage gain. λ is measured by extrapolating VD to obtain the intercept from theID −VD curves, and is simply the inverse of the VD intercept. λ was measured to be 0.095V −1 and0.2V −1 for 100µm x 100µm and 100µm x 1.5µm devices, respectively. The output resistance wasobtained from the slope of the ID −VD curve for saturation biases. Figure 12 shows r0 for different



Figure 11: nMOS Transconductance

lengths (W = 100µm).

Figure 12: nMOS Output Resistance

Channel Doping (NA) and Body Effect (γ)

For a given threshold voltage, the surface channel doping (NA for nMOS devices) can be ex-tracted from Equation 18.



Vt = φms + 2φf − Qf

Cox± εSix0

εox

√4qNA (φf )

εSiε0(18)

where φf = kTq ln

(NAni

).

The workfunction is taken to be -1V [5], fixed oxide charge Qf = 5E11cm−2, and gate oxidethickness of 40nm is used. Equation 18 is a transcendental equation (since φf depends on NA) andmust be solved numerically or graphically. Using a graphical technique, NA was determined to beabout 1E17cm−3. The threshold voltage of the longest device (100µm x 100µm) was used in orderto minimize small-dimension effects.

Due to the sudden failure of nMOS devices on wafer 5, and the resulting inability to obtainback-gate bias data, γ was determined to be 2.1 from Equation 19 using the channel doping estimateand taking oxide thickness to be 40nm.

γ =1

Cox

√2qεSiε0NA (19)

Smallest Working nMOSFET

All the four minimum-sized transistors were found to be working on wafer 5. The ability to ob-tain channel lengths as small as 1µm is mostly due to the accurate anisotropic etching and end-pointdetection precision of the P5000 plasma etcher. The ID − VD curves for the four minimum-sizeddevices are shown in Figures 13-16.

Data for a 100µm x 100µm is shown in Figure 17.

Device Parameter Summary

A summary of some of the key electrical data for nMOS transistors are presented in Table 27for several devices ranging from the biggest to the smallest, with NA = 1E17cm−3, γ = 2.1, andξ = 44mV/dec. A discussion of bad nMOS devices now follows.

nMOS Device Failures

Many nMOS transistors were observed to function improperly, were shorted, or had no drain



Figure 13: 2µm x 2µm nMOS ID − VD Characteristics

Figure 14: 2µm x 1.5µm nMOS ID − VD Characteristics



Figure 15: 1.5µm x 1.5µm nMOS ID − VD Characteristics

Figure 16: 1.5µm x 1µm nMOS ID − VD Characteristics



Figure 17: 100µm x 100µm nMOS ID − VD Characteristics

Table 27: Sample nMOS Electrical Data

W/L Vt (V) gm (mS) λ (V −1)1.5/1 0.61 0.215 0.1362/1.25 0.61 0.296 0.1161.5/1.5 0.38 1.19 0.153100/1.5 0.3 23.8 0.2

2/2 0.42 1.16 0.147100/10 0.64 3.82 0.26/20 0.54 0.17 0.128

100/100 0.67 0.11 0.095



current. These failures are presented and explained below.

Gate-Drain Short. Figure 18 shows the ID − VD curves for a 100µm x 100µm transistor.

Figure 18: 100µm x 100µm nMOS Gate-Drain Short ID − VD Characteristic

As can be seen the data suggests that the gate and drain have been shorted leading to anID − VG curve instead. There are many reasons why this can happen. Two possible reasons are 1)possible aluminum shorting of the gate and drain region or 2) polysilicon shorting of the gate to thedrain. The latter can happen if there is insufficient etching of the gate polysilicon after depositionor an alignment error during gate definition lithography, such that the mask is shifted towards thedrain. As a result, part of the mask is blocking some of the drain region from been etched. Ifthis shift occurs, there may be a depletion region between the source and channel because there isno gate at that edge to control the surface charges. However, for very short depletion region (orbarrier), tunneling current can exist and therefore the behavior in Figure 18 can occur.

Gate-Source Short. If indeed there exists a reasonable probability of shorting of gate anddrain regions, one would likewise expect a reasonable probability of shorting between gate andsource regions. This shorting has been observed and is shown in Figure 19.

Such a shorted structure is essentially a pn diode with the bulk representing the p region andthe drain representing the n region. Current will then flow for negative drain biases resulting innegative current. The magnitude of the threshold voltage is estimated to be ≈0.8V. The 100mA



Figure 19: 100µm x 20µm nMOS Gate-Source Short ID − VD Characteristic

current limit is due to tester compliance.

Shorted nMOS. To complete the ”shorting trilogy,” we have also observed shorting of theentire nMOS, i.e., the source and drain are shorted to the gate. This can happen as a result ofinsufficient etching (under-etch) of the gate polysilicon in the source/drain regions. The resultingbehavior of the device would then be similar to a resistor. A graph of a 100µm x 20µm deviceshowing this failure is shown in Figure 20.

The current limit of 100mA is the current compliance of the tester. The effective resistance isabout 8Ω.

Faulty nMOS. The majority of the failures observed were devices that simply did not drawany current, as if the source and drain were not connected to the channel, thus resulting in anopen-circuit. As mentioned earlier, one explanation is over-etch of the source and drain regions.

nMOS Characterization and TSUPREM-IV Simulation Comparison

The values calculated, simulated and measured for the nMOS transistor are compared in Table28. The measured values are taken from the longest channel device.



Figure 20: 100µm x 20µm Four-Node nMOS Short ID − VD Characteristic

Table 28: nMOS Analysis, Simulation, and Electrical Characterization Results

Parameter Analytical TSUPREM-IV MeasuredVt (V) 0.75 0.69 0.67

NA (cm−3) 1.2E17 1.1E17 1E17



The common parameters are threshold voltage and channel doping. The surface depletion atthe channel surface predicted by TSUPREM-IV has been understood to be an artifact of a 1-Dsimulation. Taking the peak boron concentration to occur at the surface, the TSUPREM-IV sim-ulation values have thus been recalculated.

6.1.2 pMOSFETs

Like the nMOS Devices, pMOSFET transistors were characterized on a Hewlett-Packard HP4145BSemiconductor Parameter analyzer. Probes were used to contact individual pads for each devicecorresponding to Source, Drain, Gate and Substrate contacts. With the exception of tests run todetermine the body effect, the Substrate and Source contacts were held at ground. Drain and Gatevoltages were then varied while Drain current was measured. Specific values used on Wafers 1, and3–5 are shown in Table 29. Wafer 2 was shown to have a much wider distribution in thresholdvoltages, so Vg was swept through a greater range of values. The parameters for this setup areshown in Table 30.

Table 29: HP4145 Setup, Low Vt Transistors

Contact Begin V Step End VSource 0 const —Drain 0 −0.2 −5.0Gate 0 −0.5 −5.0

Substrate 0 const —

Table 30: HP4145 Setup, High Vt Transistors

Contact Begin V Step End VSource 0 const —Drain 0 −0.2 −5.0Gate 0 −3.0 −27.0

Substrate 0 const —

pMOS devices were tested on all five manufactured wafers on at least three dice in the centerof the wafer and two dice near the edge. In the event that no working devices were found on theinitial five dice, more dice were tested to find functioning devices. Despite exhaustive probing ofwafers B4 and B5, no working pMOS devices were found on those wafers. Wafers B1–B3, however,



had working devices, and data was generated for a total of 180 devices, 64 from wafer B1, and 95from B2. Only 21 working devices were found on wafer B3. This was probably due to a bad metaldeposition that plagued the whole process (See Section 7).

After measurement, data was converted to a PC-readable format and drain current was plottedas Id vs. Vd, Id vs. Vg, and log(Id) vs. Vg. Threshold voltages were then extracted from the linearId–Vg curves and subthreshold slopes were pulled from the logarithmic curves. In particular, onedevice of 100 µm channel length and another with a channel length of 20 µm were chosen for anal-ysis and comparison. These transistors were chosen because their threshold voltages and lengthswere similar to those simulated in MEDICI (See Section 5.1). Both devices were on wafer B1 andwill be referred to as PMOS1 for the 100 µm device and PMOS2 for the 20 µm device. PMOS1was in series D-5, on the die one column to the right of the center die, where the wafer flat is atthe bottom of the wafer. PMOS2 was from series D-5 one die to the left of center. Characteristicplots for PMOS1 are shown in Figures 21, 22, and 23, while plots for PMOS2 are shown in 24, 25,and 26. In the following sections, plots of characteristics from a single transistor are taken fromPMOS1, unless otherwise specified.

Figure 21: PMOS1 Id vs. Vd plot used in pMOS analysis

Though many devices were far from ideal—many displayed severe DIBL effects, as will be dis-cussed in Section 7—working devices were found at even the smallest dimensions on wafers B1–B3.As proof, an IV diagram of a 1.5 µm/1 µm W/L device is shown in Figure 27. This device was the



Figure 22: PMOS1 Id vs. Vg Plot

Figure 23: PMOS1 log(Id) vs. Vg Plot



Figure 24: PMOS2 Id vs. Vd plot used in pMOS analysis

Figure 25: PMOS2 Id vs. Vg Plot



Figure 26: PMOS2 log(Id) vs. Vg Plot

last of the D-8 series on the die just left of center on wafer B1. Transistor characteristics are obvi-ous from the figure, though DIBL causes an increase in Drain current with increasing drain voltage.

pMOSFET Threshold Voltages

A histogram of measured threshold voltages is displayed in Figure 28. From the figure, it isreadily apparent that a wide range of threshold voltages were measured. However, when comparingFigure 28 with Figures 29, 30, and 31, one sees that much of the threshold voltage variation existssolely on wafer B2. Also, wafer B2 shows a shifted mean threshold voltage that is not predictedby simulations. Wafers B1 and B3, on the other hand, have average threshold voltages that arewithin one standard deviation of the predicted value.

pMOSFET Transconductance

As shown in Figure 32 pMOS Transconductance was found to be a function of both Vg and Vd.In order to have a parameter to compare from one transistor to the next, gm was measured as theslope of the near-linear low Vd curve on the linear Id vs. Vg plots. The histogram of measured gm

values is shown in Figure 33.



Figure 27: IV Characteristics of the smallest functioning device—a 1.5 x 1 µm device

Figure 28: A plot of all measured Vt. Mean value = −3.03V . Standard Deviation = 2.92V



Figure 29: A plot of Vt measured on wafer B1. Mean value = −1.31V . Standard Deviation =0.94V

Figure 30: A plot of Vt measured on wafer B2. Mean value = −4.33V . Standard Deviation = 3.4V



Figure 31: A plot of Vt measured on wafer B3. Mean value = −2.42V . Standard Deviation =1.05V

Figure 32: A plot of gm for a transistor taken from a center die on wafer B1



Figure 33: A plot of gm measured on wafer B1. Mean value = 1.04 ∗ 10−5A/v. Standard Deviation= 2.00 ∗ 10−5A/V

pMOSFET Body Effect

An adjustment of the threshold voltage can also be accomplished by reverse biasing the backcontact of an MOS transistor. This causes inversion layer carriers to migrate into the source anddrain regions since these regions are now at a lower potential. Thus, the point at which inversionoccurs, and hence the threshold voltage, shifts according to the amount of back bias applied. Fora PMOS device, the effect of a positive back bias would be to increase the magnitude of the idealthreshold voltage. That is, with increasing positive back bias, the threshold voltage should becomemore negative. For pMOS devices, this can be described by the relation,

Vt = Vto + γ[√

VSB − 2Φf −√−2Φf ] (20)

where Vto is the threshold voltage under no gate bias, γ is the body effect coefficient and VSB

is the substrate bias. The results from the testing of a 100 µm by 100 µm PMOS device from thecenter die of wafer B1 are found in Figure 34 and the table of extracted threshold voltages is foundin Table 31. Solving for γ using the above expression gives an average value of -2.6. We wouldexpect γ to have a positive value, thus indicating an increase in the magnitude of threshold voltageas a function of substrate bias. Our results are contrary to predictions, as increasing the substratebias was seen to shift the threshold voltage values towards positive values. This may indicate thatthe inversion layer carriers are not being swept into the source and drain regions but instead remainin the channel region. This would cause the threshold voltage to decrease in magnitude.



-300x10-6

-200

-100

0

Id (

A)

-10 -5 0 5 10Vg (V)

Vsb = 0V Vsb = 1V Vsb = 2V Vsb = 3V Vsb = 4V

Figure 34: Effect of Back Bias

Table 31: Body Effect SummaryVSB (V) Vt (V) Vt-Vto (V)

0 -1.27 -1 -0.32 -0.952 0.84 -2.113 1.86 -3.124 2.63 -3.90



pMOSFET Channel Doping

Channel doping was determined from the measured threshold voltage on PMOS1 and PMOS2.In order to calculate the surface doping concentration, the formula,

Vt = ΦMS − Qf

Cox−√

2εsqNd(−2Φp)Cox

− 2Φp (21)

was used, where Qf = 5e10cm−2. Also,

ΦMS = 0.56 + Φp (22)

Φp =kT

qln

Nd

ni(23)

which assumes that the gate is degenerately doped, pinning the gate fermi level at the valence bandedge. From SEM images of our devices, the measured gate oxide thickness is close to the targetthickness of 400 A. Thus,

Cox =εox

xox=

8.85 ∗ 10−14 ∗ 3.9400 ∗ 10−8

= 8.63 ∗ 10−8F/cm (24)

Solving this system of equations numerically for Nd, using the measured values for Vt we get thevalues shown in Table 32.

Table 32: Extracted Nd values, pMOSFETs

Parameter PMOS1 PMOS2Channel Length 100 µm 20 µm

Vt −1.0V −0.9VNd 3.46E16 cm−3 2.93E16 cm−3

pMOSFET Subthreshold Behavior

Subthreshold slopes were taken as the inverse of the largest slope on the log Id vs. Vg curves.Data was obtained from wafers B1–B3, though the large ∆Vg used in measuring wafer B2 resultedin artificially large subthreshold slopes. Because of this, only the data from wafers B1 and B3 ispresented in Figure 35. A few devices can be seen to approach the ideal value from simulations of88 mV/dec, though these values could be artifacts of the experimental setup due to discontinuitiesin the log Id vs. Vg curves. In fact, the pA current resolution of the HP4145 prevented very accuratemeasurement of the subthreshold slope. The measured values for PMOS1 and PMOS2 were 162



and 127 mV/dec, respectively.

Figure 35: Subthreshold Slope Distribution for wafers B1 and B3. Mean = 214 mV/dec. StandardDeviation = 123 mV/dec.

pMOSFET Channel Mobility

Like channel doping, channel mobility was not directly measured; rather, it was derived frommeasured data. By taking the triode region current to be,

Id =µP Cox

2Weff

Leff[2(Vgs − Vt) − Vds] ∗ Vds (25)

this equation can be solved for µP :

µP =2Id

Cox

Leff

Weff

1[2(Vg − Vt) − Vd] ∗ Vd

(26)

For simplicity and given the relatively large size of the devices involved, Weff and Leff wereboth chosen to be identical to lithographic gate width, though the accuracy of this assumption willbe discussed later in this section. The values used in determining µP are shown in Table 33, as wellas the calculated mobilities.

Also shown in Table 33 are the surface mobilities calculated using the Sun & Plummer Model[6]. In this model, an effective electric field, Eeff between the semiconductor bulk and the gate is



Table 33: Values used in determining channel mobility and Values calculated from experimentaldata

Parameter [unit] PMOS1 PMOS2Vg [V] -2 -2Vd [V] -0.6 -0.6Vt [V] -1 -0.9

Leff [µm] 100 20Weff [µm] 100 100

Id [A] -9.05E-6 -2.39E-5Experimental µP [cm2/V*s] 216 105

Sun-Plummer Value [cm2/V*s] 135 134Burried Channel [cm2/V*s] 209 211

partially screened by the inversion layer such that,

Eeff =1εs

(12Cox [Vg − Vt] + Qbulk

)(27)

where

Qbulk =√

2εsqNd(−2Φp). (28)

and Nd values were determined above. The effective mobility is then calculated as a fraction of thelow field surface mobility, µP0:

µeff =µP0

1 +(

Eeff

E0

)ν . (29)

where the empirically fitted parameters, ν and E0 as well as µP0 are shown in Table 34. Notethat with this model, the surface mobility is never higher than the low field value, 160 cm2/Vs.However, our calculated value for PMOS1 was significantly higher than the surface low field holemobility. A possible explanation is that the carriers are traveling in a buried channel. This possibil-ity will be discussed further in Section 7. Applying the fitting parameters for a burred channel (seeTable 34), we arrive at the final row of Table 33, where values are very similar to those calculatedfrom experimental data for PMOS1.

pMOSFET Channel Length Modulation. The parameter that describes channel length mod-ulation, λ, can be defined such that,

IDSAT =µP Cox

2W

L(Vg − Vt)

2 (1 + λVd) (30)



Table 34: Sun and Plummer Model Parameters. [7]

Parameter [unit] Surface Channel Burried ChannelµP0 [cm2/Vs] 160 290E0 [MV/cm] 0.7 0.35

ν 1 1

where IDSAT is the saturation drain current. Taking the derivative with respect to Vd andsolving for λ, we get,

λ =2

µpCox

L

W

1(Vg − Vt)2

dIDSAT

dVd(31)

λ can therefore be determined from the measured data by taking a finite difference, ∆Id/∆Vd, ateach point on the Id vs. Vd curve. The resulting values for λ were then averaged to determine afinal value. Table 35 shows the parameters used and the average λ for PMOS1 and PMOS2. As canbe seen numerically in the table and graphically in Figures 21 and 24, channel length modulationis much more severe for the shorter channel device, as we would expect.

Table 35: Values used in determining λ

Parameter [unit] PMOS1 PMOS2Vg [V] -2 -2Vt [V] -1 -0.9L [µm] 100 20W [µm] 100 100λ [V−1] 0.027 0.263

pMOSFET Breakdown Voltage

There are two principal reasons for breakdown in MOSFETs. The first reason is punch-through,which is when the depletion region at the drain extends across the entire channel region and reachesthe source. Punch-through is very sensitive to channel length, but not largely affected by decreas-ing channel widths. As a result, it is expected that shorter channel lengths would have a lowerbreakdown voltage. The second mechanism for breakdown is the due to a parasitic BJT effect.Again, shorter channel lengths would cause breakdown to occur earlier. For the pMOS devices,breakdown characteristics were tested on a 100 by 100 µm device on wafer B1 and are shown in



Figure 36. In this case, the breakdown occurred when the drain voltage exceeded -10V. At lowervoltages, normal Id − Vd characteristics were obtained (but cannot be observed on due to the scaleof the figure). When the drain voltage went beyond -10V, the current dramatically increased.

-250x10-6

-200

-150

-100

-50

0

50

Id (

A)

-14 -12 -10 -8 -6 -4 -2 0Vd (V)

Figure 36: Breakdown Characteristics for 100x100 µm PMOS Device

pMOSFET Short Channel Effect

The Short Channel Effect (SCE) was observed statistically by taking all devices with a gatewidth of 100 µm (the most frequently occurring gate width) and plotting their threshold voltagesas a function of gate length. (See Figure 37) To show the decreasing trend, a logarithmic fit wasperformed and the curve is also plotted in Figure 37. The trend is obvious; however, due to statis-tical scatter in the measured points, the reverse short channel effect was not observed.

pMOSFET Narrow Channel Effect

When plotting Vt as a function of gate width for all 20 µm channel length devices, the plotunfortunately shows a similar trend to the SCE discussed above. Instead of the expected rise in|Vt| with decreasing width, |Vt| is found to decrease. This is shown in Figure 38.

pMOSFET Effective Channel Length, Leff

As we saw in the section dealing with channel length modulation, λ has a non-zero value andtherefore our assumption that Leff is equal to the lithographically defined gate length might beinaccurate. We now explore that possibility further.

If we assume that λ is entirely a result of a change in channel length, we can replace L inequation 30 with an effective channel length such that,



Figure 37: Plot of |Vt| as a function of gate length. Solid line is a simple logarithmic fit to the datapoints, indicating the downward trend with decreasing gate length.

Figure 38: Plot of |Vt| as a function of gate width.



λ(Vd − VDSAT )W

L=

W

Leff(32)

Leff = L + ∆L (33)

combining equations and solving for ∆L, we get,

∆L =L

λ(Vd − VDSAT )− L (34)

Now we revisit the assumptions that we made when discussing channel mobility in Section 6.1.2.By choosing VDSAT as the point where the first derivative of Id with respect to Vd approaches itsminimum, we find that VDSAT is -1V for both PMOS1 and PMOS2. Since Vd for both devices waschosen to be -0.6 V, the channel length modulation as we have discussed here does not come in toeffect.

One could also argue that L is effectively shortened by the source/drain depletion regions.Thus, Leff would be less than L because of encroachment of the drain depletion region into thechannel under increasing drain bias. Taking the worst-case simplification that the source depletionregion does not shrink as it is forward biased, and assuming a depletion region thickness, W , for astep-function doping profile, we find,

W =√

2εs

qNd(Vbi − Vd) (35)

Vbi = 0.56 +kT

qln

Nd

ni(36)

which assumes Na Nd, and that the drain is degenerately doped. Solving this system ofequations for the Nd values determined above, we find that under an applied bias of -0.6 V, W

is 0.241 µm for PMOS1 and 0.262 µm for PMOS2. Since these values are much less that thelithographic gate lengths, it is reasonable to make the simplifying assumption that Leff ≈ L whencalculating channel mobility.

6.1.3 MOSCAPs

Methodology

Eight (8) different MOS capacitors were tested as part of CIS/CMOS-II characterization. Table36 describes the general composition and geometry of each type of MOSCAP in brief.



Table 36: MOS Capacitors

Composition Area (µm2)n+ Poly/Gate SiO2/p-Well 300,000

p+ Poly/Gate SiO2/n-Substrate 300,000n+ Poly/Field SiO2/p-Well 300,000

p+ Poly/Field SiO2/n-Substrate 300,000Metal/Field SiO2 + LTO/p-Well 600,000

Metal/Field SiO2 + LTO/n-Substrate 600,000Metal/LTO/n+ Poly 300,000Metal/LTO/p+ Poly 300,000

CV curves were extracted using the HP4275A multi-frequency LCR meter. AC signal ampli-tude was set at 10mV with a high-frequency oscillation at 100kHz. Bidirectional voltage sweepswere executed with a step time of 0.1sec.

MOSCAP characterization started with inversion biasing in order to extract meaningful ap-proximations for Cmin and display deep depletion effects on return sweeps.

Theoretical Calculations

Capacitance. Equations 37-39 present the expressions describing MOSCAP capacitance un-der accumulation, depletion, and inversion (HF) conditions [5].

C(acc) = Cox =εoxA

tox(37)

C(depl) =Cox

1 + KoxWKStox

(38)

C(inv)|HF =Cox

1 + KoxWTKStox

(39)

With estimates for gate oxide, FOX, and LTO thickness as in Table 1, Table 37 presents theexpected ideal capacitance values for MOSCAPs with the different dielectric compositions of theCIS/CMOS-II chip.

SiO2 Dielectric Thickness. From Equation 37, assuming an SiO2 dielectric and given valuefor Cox, an estimate for dielectric thickness can be calculated as in Equation 40.



Table 37: MOSCAPs - Theoretical Values for Cox

Dielectric Dielectric Thickness (nm) Area (µm2) Cox (pF)Gate SiO2 40 300,000 258.8625Field SiO2 500 300,000 20.709

Field SiO2 + LTO 1100 600,000 18.8264LTO 600 300,000 17.2575

tox =εoxA

Cox(40)

Threshold Voltage. Table 21 presented TSUPREM-IV-based estimates of threshold voltagevalues. Vt expectations are reproduced according to MOSCAP type in Table 38. Note: Metal gateMOSCAPs were not simulated as part of the TSUPREM-IV exercise.

Table 38: MOSCAP TSUPREM-IV-Extracted Vt

Composition Area (µm2) TSUPREM-IV Vt

n+ Poly/Gate SiO2/p-Well 300,000 0.172p+ Poly/Gate SiO2/n-Substrate 300,000 -1.032

n+ Poly/Field SiO2/p-Well 300,000 N/Ap+ Poly/Field SiO2/n-Substrate 300,000 -17.135Metal/Field SiO2 + LTO/p-Well 600,000 N/A

Metal/Field SiO2 + LTO/n-Substrate 600,000 -38.424Metal/LTO/n+ Poly 300,000 N/AMetal/LTO/p+ Poly 300,000 N/A

Characterization Results

Gate MOSCAPs. 240 gate MOSCAPs (two per die, 24 off-edge dice per wafer, five wafers)were tested. Unfortunately, but not surprisingly, none of these capacitors yielded acceptable CV

curves. Figures 39 and 40 are representative curves for the n+ Poly/p-Well and p+ Poly/n-Substrategate capacitors, respectively.

The poor gate MOSCAP results are not entirely surprising in the light of poor Al/Si alloydeposition and relatively large step heights for contact to polysilicon gates from above the LTOlayer. Specifically, the step height involved for gate MOSCAPs is approximately 600nm, i.e. theLTO thickness. While this height does not seem so difficult to surmount by itself, the already-poorquality of metal coverage even on planar surfaces indicates potential difficulty for metal continuity



−5 −4 −3 −2 −1 0 1 2 3 4 58.55

8.6

8.65

8.7x 10

−13

Applied Voltage, VA (V)

Cap

acita

nce,

C (

F)

Wafer B1, Center Die, Gate SiO2, n+ Poly/ p−Well nMOSCAP

dV/dt > 0dV/dt < 0

Figure 39: Representative n+ Poly/p-Well Gate MOSCAP

−5 −4 −3 −2 −1 0 1 2 3 4 53.44

3.46

3.48

3.5

3.52

3.54

3.56

3.58

3.6

3.62

3.64x 10

−13


Cap

acita

nce,

C (

F)

Wafer B1, Center Die, Gate SiO2, p+ Poly/ n−Sub pMOSCAP

dV/dt > 0dV/dt < 0

Figure 40: Representative p+ Poly/n-Substrate Gate MOSCAP



over any surface topography whatsoever. Figures 41 and 42 present representative top-view imagesof the gate MOSCAP peripheries in bright- and dark-field, respectively. The images are taken fromthe center die of Wafer B2.

Figure 41: Representative Gate MOSCAP Periphery (BF)

Admittedly, conclusive statements regarding Al/Si step coverage cannot be made on the basisof such top-view images. However, several points are worth noting. In the Bright Field image ofFigure 41, considerable Si accumulation (presumable) is evident at the pad/MOSCAP step inter-face. Such accumulation represents severe nonuniformity, increased resistance, and likely poorercoverage at a crucial point in the metal layer. Also present in the BF image is an apparent break inthe Al/Si line at the top of the image, where the metal attempts to continue down a step onto thegate oxide. Inability of the optical microscope to resolve coverage over the step is a possibility, butthe Dark Field image of Figure 42 appears to support the hypothesis that the coverage is indeedpoor and thus the likely cause of the open-circuit measurement. SEM images, which are includedin Section 6.3, indicate the near ubiquity of poor metal coverage over such steps and additionallycorroborates the hypothesis.

FOX MOSCAPs. In contrast to the Gate MOSCAP results, FOX capacitors generally pro-vided attractive CV results, save p+ Poly/n-Substrate devices for wafers other than B5. Figures 44and 44 were obtained from the center die of Wafer B5 and present the best results for n+ Poly andp+ Poly FOX MOSCAPs, respectively. Given the increased anisotropy and edge-point detection ofthe P5000 used for B5 etching, these results are not surprising.

For the sake of comparison, Figures 45 and 46 present CV results for Wafer 2.The p+ Poly/FOX/n-Substrate result for Wafer B2 represents the best CV curve of the wafers



Figure 42: Representative Gate MOSCAP Periphery (DF)

−25 −20 −15 −10 −5 0 5 10 15 20 25

1.98

2

2.02

2.04

2.06

2.08

2.1

2.12

2.14

2.16x 10

−11


Cap

acita

nce,

C (

F)

Wafer B5, Center Die, FOX nMOSCAP

dV/dt > 0dV/dt < 0

Figure 43: Wafer B5 (Center) - n+ Poly/FOX/p-Well MOSCAP



−25 −20 −15 −10 −5 0 5 10 15 20 251.9

1.95

2

2.05

2.1

2.15

2.2x 10

−11


Cap

acita

nce,

C (

F)

Wafer B5, Center Die, FOX, p+ Poly/ n−Sub pMOSCAP

dV/dt > 0dV/dt < 0

Figure 44: Wafer B5 (Center) - p+ Poly/FOX/n-Substrate MOSCAP

−25 −20 −15 −10 −5 0 5 10 15 20 25

1.98

2

2.02

2.04

2.06

2.08

2.1

2.12

2.14x 10

−11


Cap

acita

nce,

C (

F)

Wafer B2, Center Die, FOX, n+ Poly/ p−Well nMOSCAP

dV/dt > 0dV/dt < 0

Figure 45: Wafer B2 (Center) - n+ Poly/FOX/p-Well MOSCAP



−25 −20 −15 −10 −5 0 5 10 15 20 254.2

4.22

4.24

4.26

4.28

4.3

4.32

4.34x 10

−12


Cap

acita

nce,

C (

F)


dV/dt > 0dV/dt < 0


etched using the standard prescribed Drytek etch process (not P5000). For the sake of completeness,Figures 47, 48, and 49 present the other p+ Poly/FOX/n-Substrate CV results from the centerdice of Wafers B1 and B3, and the bottom die of Wafer B3, respectively.

Figures 47-49 represent unusual results for MOSCAP characterization. The only known dif-ference between Wafers B1-B3 and Wafer B5 is the use of the P5000 etch for B5. A tentativeconclusion that smaller diffusivities for typical n-type dopants (P and As) may hinder their abilityto reestablish substrate doping continuity after overetching in the Drytek can be proposed [3]. Moredetailed explanation of this potential effect is provided in sections to follow.

Particular attention should be paid to Figure 47, which presents the CV plot for the p+

Poly/FOX/n-Substrate MOSCAP on the center die of Wafer B1. Although exhibiting the gener-ally expected order-of-magnitude for C, the curve indicates an nMOSCAP rather than the pMOSexpectation. Such a reversal of the CV curve suggests identification of the course staff-introducedfault wafer and its corresponding fault as an additional p-type or missed n-type substrate implant.However, a concrete argument regarding the fault cannot be made on the basis of one CV plot,especially given the widespread prevalence of device failures on all wafers and the lack of supportingtransistor data for this hypothesis. Sheet resistance results will indicate odd behavior on Wafer B1as well, but a conclusive argument is still unreasonable given the lack of unequivocal evidence.

Table 39 summarizes the n+ Poly/FOX/p-Well MOSCAP CV results and calculations forall center dice to present wafer-to-wafer variation. Variation data for p+ Poly/FOX/n-Substrate



−10 −8 −6 −4 −2 0 2 4 6 8 103.4

3.42

3.44

3.46

3.48

3.5

3.52

3.54x 10

−12


Cap

acita

nce,

C (

F)


dV/dt > 0dV/dt < 0


−25 −20 −15 −10 −5 0 5 10 15 20 253.97

3.98

3.99

4

4.01

4.02

4.03

4.04

4.05x 10

−12


Cap

acita

nce,

C (

F)


dV/dt > 0dV/dt < 0

Figure 48: Wafer B2 (center) - p+ Poly/FOX/n-Substrate MOSCAP



−25 −20 −15 −10 −5 0 5 10 15 20 252.5

3

3.5

4x 10

−12


Cap

acita

nce,

C (

F)

Wafer B3, Bottom Die, FOX, p+ Poly/ n−Sub pMOSCAP

dV/dt > 0dV/dt < 0

Figure 49: Wafer B2 (Bottom) - p+ Poly/FOX/n-Substrate MOSCAP

MOSCAPs are not presented due to their order-of-magnitude discrepancy with the expected result.

Table 39: n+ Poly/FOX/p-Well MOSCAP Data and Calculations

Wafer/Die Cox(acc) (pF) Cinv (pF) tox (nm)B1/Center 1 21.216 20.809 488.05B1/Center 2 21.319 19.867 485.69B2/Center 21.357 19.947 484.83B3/Center 21.287 19.896 486.42B5/Center 21.497 20.051 481.67Average 21.3552 20.1140 485.332

σ 0.1042 0.3948 2.3644

Little wafer-to-wafer variation plagues the n+ Poly/FOX/p-Well MOSCAP results. C(acc) =Cox, C(inv), and tox values are tightly distributed about their averages. Assuming the theoretical20.709pF Cox value provided in Table 37 and the target FOX thickness of 500nm, the average mea-sured value of oxide capacitance, 21.3552pF, differs by 3.1204%, while average measured tox differsby 2.9336%. Thus, the prescribed process flow for FOX growth is relatively accurate, especially forFOX thickness, which is noncritical above a threshold needed for isolation.



Table 40 presents the n+ Poly/FOX/p-Well MOSCAP CV results and calculations for WaferB3 for intra-wafer variation.

Table 40: n+ Poly/FOX/p-Well MOSCAP Data and Calculations

Die Cox(acc) (pF) Cinv (pF) tox (nm)Top 21.414 20.016 483.54Left 21.660 20.264 478.05

Center 21.287 19.896 486.42Right 21.275 19.907 486.70

Bottom 21.425 20.009 483.29Average 21.4122 20.0184 483.600

σ 0.1550 0.1482 3.4808

Intra-wafer variations are comparable to wafer-to-wafer variations. Specifically, variations in Cox

and tox across Wafer B3 are more severe than trans-wafer variations in the center dice. However,variation across B3 for C(inv) is less than that across wafers. Nevertheless, both wafer-to-waferand intra-wafer variations in FOX thickness are negligible, and the process flow seems reliable inthis regard.

For the sake of comparison with the Gate MOSCAPs, Figures 50 and 51 present the Bright Fieldand Dark Field images of the n+ Poly/p-Well FOX MOSCAP on the center die of Wafer B3. Thestep onto oxide, while visibly steeper for the Gate capacitors, is more gradual and better-coveredfor the thicker oxides. Open areas in the Al/Si alloy at boundaries are not apparent, supportingthe hypothesis that the poor metal coverage over relatively large steps played an important role inGate MOSCAP failures.

FOX/LTO MOSCAPs. As with the FOX MOSCAPs, FOX/LTO capacitors exhibit gen-erally attractive results for p-Well devices but less impressive n-Substrate results. Figures 52 and53 were obtained from the center dice of Wafers B3 and B1 and present the best results for p-Welland n-Substrate FOX/LTO MOSCAPs, respectively.

Table 41 summarizes the Metal/FOX & LTO/p-Well MOSCAP CV results and calculations forall center dice to present wafer-to-wafer variation. Wafer B5 is not included due to erroneous results,which would skew the statistics beyond meaning interpretation. Variation data for Metal/FOX &LTO/n-Substrate MOSCAPs are not presented due to their order-of-magnitude discrepancy withthe expected result.

As with FOX MOSCAPs, little wafer-to-wafer variation plagues the Metal/FOX & LTO/p-Well MOSCAP results. Assuming the theoretical 18.8264pF Cox value provided in Table 37 and



Figure 50: Representative FOX MOSCAP Periphery (BF)

Figure 51: Representative FOX MOSCAP Periphery (DF)



−25 −20 −15 −10 −5 0 5 10 15 20 25

1.98

2

2.02

2.04

2.06

2.08

2.1

2.12x 10

−11


Cap

acita

nce,

C (

F)

Wafer B3, Top Die, FOX & LTO, Metal/ p−Well nMOSCAP

dV/dt > 0dV/dt < 0

Figure 52: Wafer B3 (Center) - Metal/FOX & LTO/p-Well MOSCAP

−25 −20 −15 −10 −5 0 5 10 15 20 252.6

2.8

3

3.2

3.4

3.6

3.8

4x 10

−12


Cap

acita

nce,

C (

F)

Wafer B1, Center Die, FOX & LTO, Metal/ n−Sub pMOSCAP

dV/dt > 0dV/dt < 0

Figure 53: Wafer B1 (Center) - Metal/FOX & LTO/n-Substrate MOSCAP



Table 41: Metal/FOX & LTO/p-Well MOSCAP Data and Calculations

Wafer/Die Cox(acc) (pF) Cinv (pF) tox (nm)B1/Center 21.112 20.022 980.091B2/Center 21.874 20.662 946.74B3/Center 21.671 20.471 955.61Average 21.5523 20.3850 960.814

σ 0.3946 0.3286 17.2737

the target FOX+LTO thickness of 1100nm, the average measured value of oxide capacitance,21.5523pF, differs by 14.4791%, while average measured tox differs by 12.6533%. Unlike the casefor FOX MOSCAPs, the prescribed process flow for FOX growth followed by LTO depositionneeds some modification. However, since the FOX and LTO layers are noncritical past a thresholdthickness for isolation, the nearly 15% variation may be negligible. Table 40 presents theMetal/FOX & LTO/p-Well MOSCAP CV results and calculations for Wafer B3 for intra-wafervariation.

Table 42: Metal/FOX & LTO/p-Well MOSCAP Data and Calculations

Die Cox(acc) (pF) Cinv (pF) tox (nm)Top 21.111 20.006 980.96Left 21.969 20.766 942.6

Center 21.671 20.471 955.61Right 21.535 20.350 961.64

Bottom 21.863 20.635 947.22Average 21.6298 20.4456 957.616

σ 0.3351 0.2922 14.9768

Intra-wafer variations across B3 are smaller relative to wafer-to-wafer variations. Nevertheless,both wafer-to-wafer and intra-wafer variations in FOX thickness may be negligible so long as aminimum threshold for isolation is met.

LTO MOSCAPs. Only Wafer B5 exhibited moderately attractive results for Metal/LTO/PolyMOSCAPs. Figures 54 and 55 present the CV curves for Metal/LTO/p+ Poly and Metal/LTO/n+

Poly, respectively, on the center die of Wafer B5.While the curves themselves do not appear as expected, the extracted oxide thickness approxi-

mates the ideal value well. Table 43 summarizes the data for Wafer B5.



−10 −8 −6 −4 −2 0 2 4 6 8 10

1.7026

1.7028

1.703

1.7032

1.7034

1.7036

1.7038

1.704x 10

−11


Cap

acita

nce,

C (

F)

Wafer B5, Center Die, LTO, Metal/ n+ Poly pMOSCAP

dV/dt > 0dV/dt < 0

Figure 54: Wafer B5 (Center) - Metal/LTO/p+ Poly MOSCAP

−10 −8 −6 −4 −2 0 2 4 6 8 101.7596

1.7597

1.7598

1.7599

1.76

1.7601

1.7602

1.7603

1.7604

1.7605x 10

−11


Cap

acita

nce,

C (

F)

Wafer B5, Center Die, LTO, Metal/ p+ Poly nMOSCAP

dV/dt > 0dV/dt < 0

Figure 55: Wafer B5 (Center) - Metal/LTO/n+ Poly MOSCAP



Table 43: Wafer B5 - Metal/LTO/Poly MOSCAPs

Device Cox(acc) (pF) Cinv (pF) tox (nm)nMOSCAP 17.604 17.603 588.19pMOSCAP 17.037 17.033 607.78

Average 17.3205 17.3108 597.985σ 0.4009 0.4031 13.8522

Assuming the theoretical 17.2575pF Cox value provided in Table 37 and the target LTO thick-ness of 600nm, the average measured value of oxide capacitance, 17.3205pF, differs by 0.3651%,while average measured tox differs by 0.3358%. Thus, the LTO deposition process parameters seemwell-calibrated given the LTO MOSCAP results. Admittedly, two data points on a single wafer donot constitute a representative sample of all dice, so conclusive statements cannot be made withmuch confidence, especially given the failure (open) of LTO MOSCAPs on all other wafers besidesB5. As before, this indicates the need to use P5000 etch procedures to the exclusion of Drytek.

6.1.4 Diodes

Measurement Methodology

Although there are four pn junction diode configurations with area and edge components, onlythe poly-poly diodes gave acceptable IV characteristics. Other configurations didn’t output enoughcurrent for every die on every wafer. For poly diodes, voltage range of −10V to 10V is applied toone electrode and the current from that electrode is measured to output the IV characteristics.We obtained 8 results from Wafer B3, 4 from Wafers 1 and 2, and 1 result from B5.


Figure 56 is a representative IV characteristic derived from the poly diode measurements.

The turn-on voltage and the breakdown voltage are rather conspicuous. The turn-on voltageis extracted by extrapolating the linear part and taking the x-intercept point. Average values ofturn-on voltages and breakdown voltages for each wafer are given in Figure 57.

Note that there are only 4, 4, 8, 1 measurement results for wafer 1, 2, 3, 5 respectively. Turn-onvoltage is around 2 − 3V and the breakdown is near 5 − 6V.



Figure 56: Representative poly-poly Diode IV Characteristic

Figure 57: Poly-poly Diodes Electrical Characteristics



Discussion

As forward bias is applied, the potential barrier for both electrons in n+ and holes in p+ islowered. Once turned on the carrier concentration increases exponentially with linearly increasingbias. Therefore forward current is expected to increase exponentially with the applied voltage. Atreverse bias, the potential barrier is too high for any majority carrier to surmount. However p+side electrons and n+ side holes can still wander into the depletion region and get swept to theother side [5]. This is presented in Equation 41

I = I0

(e

qVAkT − 1

)(41)

From the fact that the breakdown voltage is relatively small and the process is very gradual, wecan say that the breakdown is due to tunneling. Other breakdown effects like avalanche breakdownusually occurs at 30 − 100V depending on the doping of the lightly doped side. Also, at avalanchebreakdown the reverse current effectively goes off to infinity very quickly [5].

Tunneling, namely the Zener process, is a phenomenon where a carrier has enough energy topass through a barrier to an empty state of the same energy (Figure 58).

Figure 58: Tunneling in a pn-Diode

One important thing is that the barrier thickness must be thin enough for the carrier to tunnelthrough. This is only achieved when both sides of the pn diode is highly doped, which is just thecase for the n+ poly p+ poly diode. As reverse bias increases in magnitude, two things happen.One, the carriers in the filled state increase and two, the barrier thickness gets even thinner. This



tunneling phenomenon plays a significant role to the breakdown process where the breakdown volt-age is less than 6EG

q ≈ 6.7V [5].

6.2 Process Test Structures

6.2.1 Sheet Resistivity

Introduction

Resistivity, which is related to the free electron or hole concentration, is defined as in Equation10, reproduced as Equation 42.

ρ =1

q (nµn + pµp)Ω − cm (42)

Generally, only one of the two terms is important because n p or p n under most con-ditions. The resistivity is thus a measure of the product of the mobility and the majority carrierconcentration. A measurement of ρ thus provides n or p, provided the mobility is known [3].

The most common method of measuring the wafer resistivity is the four-point probe illustratedin Figure 59.

Figure 59: Four-Point Probe Test Pad Configuration



We basically seek to measure the sample resistance by measuring the current that flows for agiven applied voltage. This could be done with just two probes. However, in that case, contact resis-tance associated with the probes and current spreading problems around the probes are importantand are not easily accounted for in the analysis. Using four probes allows us to force the currentthrough two pads and measure the voltage drop with the two inner probes using a high-impedancevoltmeter. Problems with probe contacts are thus eliminated in the voltage measurement since nocurrent flows through these contacts. In the 4-point probe structure shown in Figure 59 a currentIFORCE is forced through the I-1 FORCE and I-2 FORCE pads, resulting in a voltage VSENSEacross the V-1 SENSE and V-2 SENSE pads. The sheet resistivity can then be obtained usingEquation 43 where W and L are the dimensions of the thin-film structure to be probed.

Rsheet = Rmeasured

(W

L

)=

Vsense

Iforce

(W

L

)(43)

Another common method for obtaining sheet resistance is by using the Van der Pauw technique,illustrated in Figure 60.

Figure 60: Van der Pauw Test Pad Configuration

Van der Pauw shows that the resistivity can be measured for an arbitrary shape provided thatseveral conditions are met. The Van der Pauw structures consist of four contacts (labeled VDP-1,VDP-2, VDP-3 and VDP-4 in counterclockwise sense) symmetrically arranged around an octagonal



area. The sheet resistance can be obtained by forcing a current across two adjacent terminals andmeasuring the resulting voltage developed across the other two adjacent terminals and subsequentlyapplying Equation 44 [8].

Rsheet =π

ln 2Rmeasured =

π

ln 2V12

I43(44)

Measurement Results

At least one die from wafers B1, B2, B3, and B5 has been measured for the sheet resistanceby both 4-point probe and Van der Pauw techniques. B4 was not evaluated because of poor metaldeposition. For each die, all the 16 structures (for 4-point probe) and 7 structures (for Van derPauw) have been measured. Wafers 2 and 3 had the most consistent numbers and generally showeda larger number of working test structures. The average sheet resistance of wafers 2 and 3 arepresented in Table 44.

Table 44: Average Sheet Resistivity Measurements for Wafers 2 and 3

Wafer N+ P+ N+ poly P+ poly P-well 1 P-well 2 P-well 3 MetalWafer 2 6.3 26.5 7.8 8.1 412.5 155.8 6666.7 0.00046Wafer 3 3.8 25.4 3.4 2.5 420.0 163.8 8750.0 0.00052

Typical measurement curves for 4-point probe and Van der Pauw are shown in Figures 61 and60. The sheet resistivity is measured to be about 5Ω/sq..

A chart of average sheet resistance measurement results for Wafers B2 and B3 by 4-point probeis given in Figure 63

For the 4-point probe technique, wafers B2 and B3 give pretty consistent results and wafer B5also gives comparable values. However, B1 data are not very good. The data shows us that for theP+ active, N+ active, P+ poly, N+ poly, the sheet resistance by the 4-point probe method is around5-20Ω, and that of P-Well 1 (gate oxide and poly on top) and P-Well 2 (gate oxide with N+ pinch)is about 150-500Ω. Sheet resistance of P-Well 3 (field oxide on top) is very large, above 5000Ω, andthat of metal is very small, around 0.1mΩ. That is correct, since metal has small resistivity andoxide has large resistivity. However, the sheet resistance measured by the Van der Pauw techniqueis not consistent with that of 4-point probe.



Figure 61: Representative (1µm x 30µm) 4-Point Probe IV

Figure 62: Representative (P-well with Oxide) Van de Pauw IV



Figure 63: 4-Point Probe Sheet Resistance Wafer Comparison

Comparison with Simulation Results

The sheet resistance depends upon the junction depth and can be calculated from the dopantprofile. It can be solved as shown in Equation 9 and reproduced in Equation 45.

ρS =1

σxj=

1q∫ xj

0 [n(x) − NB(x)] µ[n(x)]dx(45)

where q is the electronic charge, µ is the carrier mobility, NB is the background or impurityconcentration, and n(x) is the profile of the diffused dopant.

In the case of the polysilicon sections, the value has to be calculated by numerical integration.However, as the mobility of the polysilicon is highly varied, an approximate value of 1

2 that ofcrystalline Silicon was used. Analytical, TSUPREM-IV simulation, and physical characterizationresults are summarized in Table 45.

Table 45: Sheet Resistivity Analysis, Simulation, and Electrical Characterization Results

Material Analytical TSUPREM-IV MeasurednMOS Source 60.2 60 8.3nMOS Poly 100.1 28 10

pMOS Source 39.6 52 30.8pMOS Poly 367.7 249 10.8



The measured sheet resistance is relatively small compared with simulation results. The dis-crepancies are greatest for the polysilicon regions. This is to be expected since the actual mobilityand diffusivity in the poly material is heavily fabrication-dependent, which cannot be predictedeither by calculation or by simulation.

6.2.2 Contact Chains

Methodology

A contact chain goes through active/poly regions to contact holes to metal and back to ac-tive/poly regions, as in Figure 64. Since the resistance of aluminum is very small, the resistance ofa contact chain consists of the resistance of the diffused region and the contacts.

Figure 64: Contact Chain Schematic Diagram

Contact chains are used to test the contact integrity. In one measurement, 20 to up to 1000contacts are tested. Since these contacts are connected in series, one fault will make the wholechain an open circuit. In this respect, contact chains can also be used to figure out the yield or thereliability of the contacts.

Although contact chains are not a good structure to measure contact resistances, we can con-firm a linear relationship in the resistance to the chain length, namely the number of contacts.By applying a voltage to the ends of the chain and measuring the current, the resistance of thecontact chain can be evaluated. We obtain an IV plot by sweeping the voltage, and calculate the re-sistance from the data of both active and poly regions for 4µm x 4µm and 2µm x 2µm contact areas.


Both reliability and the straightforward linear dependency of the resistance to the number ofcontact units were obtained from the poly contact chains. However, only negligible current on theorder of pA were observed from almost every contact chain on the active regions. The computedresistance approached that of air, which suggests that the contact chain is poorly connected andcan be considered an open circuit.



P+ poly contact chains gave nice clean IV plots as shown in Figure 65, where n+ poly contactchains gave nonlinear plots shown in Figure 66. But as the number of contact units increase, thecurrent of the n+ poly contact chain becomes linear to applied voltage. We’ll discuss these obser-vations in the following sections. Since the n+ poly contact chain for small contact unit numberhas a resistance that falls off at high biases, we take the data point near zero bias as the resistanceof the total chain. The singularity of the resistance at zero bias is due to zero current; we’ll ignorethis point hereafter.

Figure 65: 20 Contact (2µm x 2µm), p+ Poly IV Characteristic

The resistance of one contact unit, which is composed of a metal, two contact holes and the(poly) silicon region, is calculated and presented for wafers B1, B2 and B3 in Table 46. The metalresistance is assumed to be small and will be neglected. The resistance given in Table 46 is basically:2RC + Rpoly. Center dice of each wafer were measured.

∗Both the IV and contacts (#)-dependent resistance are nonlinear. This means that the re-sistance of each chain unit is not uniform throughout the structure. So the recorded values maydiverge from the actual resistance of one contact chain unit.

Resistances are in units of Ω, and blanks mean that the contact chain was broken, giving a high



Figure 66: 20 Contact (2µm x 2µm), n+ Poly IV Characteristic

Table 46: Contact Chains: Wafer-to-Wafer Variation

p+ Poly n+ PolyWafer 4µm x 4µm 2µm x 2µm 4µm x 4µm 2µm x 2µm

B1 224 Linear 453 Linear - - - -B2 175.5 Linear 257.5 Linear 1.41k Nonlinear∗ 6.42k Nonlinear∗

B3 183.5 Linear 274.5 Linear 4.49k Nonlinear∗ 19.3k Nonlinear∗



resistance. N+ poly strangely has huge resistance values. Since the contacts and metal were madeat the same time for both n+ and p+, the cause should be Rpoly.

Wafer variations for p+ poly B2 and B3 are small compared to that of B1. Wafer B1 seems tohave higher p+ poly chain unit resistance. This can be due to thinner poly deposition and morecurrent crowding, or process variations. The n+ poly values seem to be varying from structure tostructure. Effects happening in the n+ poly contact chain will be discussed in the next subsection.

Now to find out on-wafer variations, we choose wafer B3 which has the finest results, presentedin Table 47. Since the periphery of the wafer might have been subject to external damage ornon-uniformity in the process, we measured the second-most die of top, bottom (flat), left, right.

Table 47: Contact Chains: Intra-Wafer (B3) Variation

p+ Poly n+ PolyDie 4µm x 4µm 2µm x 2µm 4µm x 4µm 2µm x 2µm

Top - - 689 Linear - - 876k NonlinearLeft - - 276 Linear - - 10.7k Nonlinear

Right - - 275.5 Linear - - 29.74k NonlinearBottom 193 Linear 267.8 Linear 849.5 Nonlinear∗ 579.9 Nonlinear∗

The 4µm x 4µm contacts show that they are not reliable. Resistance values fall as we movefrom top to bottom. Since these are not the results of every die on every wafer, they can be due tojust contingent statistical variations. Poly deposition thickness can be thicker on the bottom andthinner on the top. Also, etching of the poly might have been incomplete in some areas of the wafer.

Discussion

As mentioned before, the IV plot of the n+ poly chains have a strong nonlinearity, while thep+ poly does not. But even in n+ poly, as contact chain units increase, the voltage applied to eachunit decreases, making this nonlinearity disappear. When a high voltage is applied to a single unit,the current goes up. It is thought that a high resistance parallel current path is turning on. It canbe pictured as multiple resistances in parallel competing with each other. A more detailed pictureof the cross section of the chain must be known to figure out the exact parallel path in concern.One possibility is current crowding. The current density is nonuniform across a contact, and thecurrent is higher at the front edge of the planar metal contact. This is because the current doesn’tflow through the whole poly layer but relatively through the conductive top side, which has higherdoping and also the shortest path between contacts. As more voltage is applied along a contact,current can start to flow through additional paths other than along the surface of the poly, sincethe polysilicon layer is not thin. In thin layers, current crowding is inevitable. If more current is



flowing through the whole contact the resistance becomes lower, like Figure 66.Then why would this effect occur only in the n+ poly? This may due to the high resistance

measured in the n+ poly chain. High conductivity in the p+ poly chain would have less effect ofcompeting resistances. If it were that the contact resistances are roughly on the same scale forboth cases (contact resistances presented in next section), then the high resistance is mostly due tothe n+ polysilicon layer, as referred already before. There can be many causes of high resistancein polysilicon. The dose of the n+ source/drain implant may have been too low. By TUSPREM4simulations, if the dose were the same as the boron blanket implant (1E15cm−2), the sheet resis-tance increases by approximately a factor of 10.

The 4µm x 4µm case has lower resistance than the 2µm x 2µm case, explaining that larger areacollects more current since the polysilicon layer is not thin to make current crowding severe. Butwe’ve obtained more results from the smaller 2µm x 2µm contact size than from the 4µm x 4µm,which is counterintuitive. It can be thought that since the contact area is bigger there is a higherprobability for a lateral metal break (refer to the SEM picture section) or other faults. One breakwill make the whole chain open.

There were no results from the active regions. The active regions are further down from thetop of the LTO where the metal is deposited. It is evident that the metal step coverage is poor,and the deeper the step is, the harder for the metal to get down to the diffusive regions. Qualityof the metal step coverage will be shown through SEM images to follow.

6.2.3 Contact Resistance

Contact Configurations

Kelvin contact structures are used to measure the contact resistances of various contacts. Inthe process, there are four kinds of contacts introduced; contacts to N+ active, P+ active, N+ polyand P+ poly. All of these are measured for four different contact areas; from 1.5µm x 1.5µm to4µm x 4µm.

Testing Methodology

The Kelvin structure used for contact resistance extraction is presented in Figure 67The resistance through the current path 2 to 4 is: 2RC + Ractive/poly + Rparasitic; resistance of

the metal regions can be neglected. To get an isolated contact resistance, the voltage across thecontact only is required. Basically the Kelvin structure forces a current through pads 2 and 4 andmeasures the voltage between 1 and 3. The contact resistance is calculated as in Equation 46

RC =V13

I24(46)



Figure 67: Kelvin Contact Resistance Schematic

Since there is very small current flowing between pads 1 and 3, the voltage drop across the ac-tive/poly region from pad to contact is negligible. For a more accurate measurement, we canrepeat the procedure above and get R′

C = V24I13

. The average of the two resistances will give acontact resistance taking into account possible asymmetries of the structure [9].


To compare contact size, 4µm x 4µm and 1.5µm x 1.5µm are measured for all contact figura-tions. Among the data measured, only the center die is reported. There are several plot shapesthat occur frequently. We will classify them as Schottky, ohmic and completely linear. Some of theresults are in-between Schottky and ohmic form. For linear IV plots, the resistance extraction isstraightforward. On the other hand, extraction of resistance is more difficult for nonlinear plots.For Schottky behavior contacts, the turn-on voltage and the differential resistance (slope of the V I

plot) after turn-on are listed in Table 48, where ∗ indicates near-perfect Schottky behavior.

Figures 68-70 present representative Schottky, Ohmic, and Completely Linear contact resistancecurves, respectively. Figure 68 describes a 1.5µm x 1.5µm p+ active contact on the center die ofWafer B1. Figure 69 describes a 4µm x 4µm n+ poly contact on the center die of Wafer B3. Figure70 describes a 1.5µm x 1.5µm p+ poly contact on the center die of Wafer B2.

There are two kinds of Schottky contact plots that have been measured, one with small os-cillation and one without it. The Schottky contacts that have oscillating noise have a differential



Table 48: Kelvin Contact Resistance Results

Wafer Region 4µm x 4µm 1.5µm x 1.5µm

B1 n+ active Schottky Rd = 18.2kΩ, Vt = 1.22V Schottky Rd = 19.2kΩ, Vt = 0.55 Vp+ active In-between - Schottky∗ Rd = 2.54kΩ, Vt = 0.36Vn+ poly Schottky Rd = 17.4kΩ, Vt0.71V Schottky Rd = 32.9kΩ, Vt = 0.97Vp+ poly - - Schottky∗ Rd = 3.35kΩ, Vt = 0.2V

B2 n+ active Schottky Rd = 14.2kΩ, Vt = 0.95V Schottky Rd = 10.3kΩ, VB = 1.10Vp+ active Linear R = 85Ω Ohmic -n+ poly Schottky Rd = 14.8kΩ, Vt = 0.82V Ohmic -p+ poly - - Linear 685Ω

B3 n+ active Schottky Rd = 18.2kΩ, Vt = 1.22V Odd Rd = 11.2kΩ, VB = 1.48Vp+ active Linear 85Ω Ohmic -n+ poly Ohmic - - -p+ poly Linear 20Ω Linear 732Ω

B5 n+ active - - Linear 262Ωp+ active Linear 58Ω Ohmic -n+ poly - - Ohmic -p+ poly Odd - Linear 770Ω

Figure 68: Kelvin Contact Resistance - Representative Schottky



Figure 69: Kelvin Contact Resistance - Representative Ohmic

Figure 70: Kelvin Contact Resistance Representative Completely Linear



resistance around 17kΩ and a turn-on voltage that ranges from 0.7 to 1.1V. The clean Schottky con-tact behavior contacts have both a lower differential resistance (around 3kΩ) and turn-on voltage(around 0.3V). The perfect Schottky contacts were only observed in B1 p+ diffusive. For carriersin the metal to get into the silicon, the barrier height is φB = φM −χ, where φM is the metal workfunction and χ is the silicon electron affinity. For carriers in the semiconductor to get into the metalthey must surmount a barrier whose height is Vbi = [φB−(EC−EF )]

q = 1q (φM − φS). From Fermi-level

pinning (discussed in next section), Vbi = 23EG−(EC − EF ) for n-type and Vbi = 1

3EG−(EF − EV )for p-type. The difference in turn-on voltage for contacts to n+ and p+ can be explained by thisbarrier height difference.

Ohmic contacts have a differential resistance of 10kΩ around zero bias. As current increasesat high biases the resistance reduces to a few kilo-ohms (2.5kΩ). An ohmic-like behavior showsthat there is no barrier from semiconductor to metal at zero bias. So even a small positive voltagewill result in large currents. Under negative bias, a small barrier for the majority carriers from themetal to the semiconductor exists. Since the barrier is small, the barrier vanishes at few tenths ofa volt [5].

Linear plots have very small contact resistance below 1kΩ, with an average of 85Ω. Plots thatare linear indicate a contact resistance that is independent of the current.

Discussion

N+-type semiconductor regions that have doping dependent workfunctions smaller than themetal workfunction will show a Schottky nature in the contacts. Contrarily, if the semiconductorworkfunction is smaller than the metal workfunction, the electrical nature of the MS contact willbe ohmic, and vice-versa for p+-type silicon. The workfunctions of n+ silicon, p+ silicon andaluminum are roughly 4.05eV, 5.25eV, 4.1eV, respectively.

So by only looking at the workfunction differences, both contacts to n+ and p+ silicon shouldbe rectifying. But in practice, surface states usually dominate the characteristics above. Due toa large density of surface traps the Fermi-level gets pinned at the trap level. Experimentally, it isfound that the surface states show a pronounced peak at 1

3EG. Thus, fabrication of an ohmic isdifficult since both material properties and practical technological issues are involved [10].

Choosing appropriate materials with the desired workfunctions won’t work due to the Fermi-level pinning. Another way is to dope the semiconductor heavily enough so that tunneling ispossible. Figure 71 shows the dependence of the contact behavior to level of doping.

Lastly, Figure 72 presents the V I curve for a 1.5µm x 1.5µm contact to n+ active on the centerdie of Wafer B3. This can be either a Schottky contact with a sharp turn-on voltage or a linearplot with a voltage barrier at transition from negative to positive bias. One possibility is that avery thin native oxide grew on top of silicon before the contact holes were formed. This will makea voltage barrier that will be overcome only at sufficiently large voltages where the carriers can



Figure 71: MS Contacts - Doping Dependence

surmount the barrier.

6.2.4 Continuity and Isolation

In order to evaluate the integrity of the interconnects within a given layer, continuity and isolationstructures were fabricated and tested. For continuity, the test structure is a continuous line thatsnakes back and forth. The lines are made of different materials (poly-Si or metal for example)and are in either 2 or 4 µm widths. One key structure is the metal line over the features of thesurface, from which quality of metal step coverage over sharp edges can be evaluated. These resultsare discussed in the following section. The isolation test structure consists of two interpenetratingcombs of 30-300 µm stripes of metal which cover various surface features. The spacing between thelines varies between 2 to 4 µm.

To test these structures, a voltage was applied across terminals A and B and the resultingcurrent was measured. For continuity measurements, a high resistance indicates the presence of anunwanted open circuit in the line. This could be due to poor definition of the lines or poor materialquality. For wafer B2, the continuity measurement of the 2 µm metal lines is shown in Figure 73.The high current measured indicates low resistance in the line, and thus a working metal line. Asummary of all the continuity testing is found in Table 49.



Figure 72: n+ Active Contact - VI Characteristic

-20x10-3

-10

0

10

20

Cur

rent

(A

)

-4 -2 0 2 4Voltage (V)

200

150

100

50

0

Resistance (Ω

)

Figure 73: Current vs. Applied Voltage of Metal Lines



Table 49: Continuity Testing SummaryWafer 1 Wafer 2 Wafer 3 Wafer 5

Width (µm): 2 4 2 4 2 4 2 4N+ Snake × × × × × × √ √P+ Snake

√ √ √ √ √ √ √ √P+ Poly Snake × × × × × × × ×N+ Poly Snake × √ × × × √ × ×N+ Poly Snake over Active Steps × √ × × × √ × ×P+ Poly Snake over Active Steps × √ × × × × × ×Metal × √ × √ √ √ √ √Metal over Parallel N+ and Poly Stripes Tilted at 5 Degrees × × × × × × × ×Metal over All Topography, Horizontal × × × × × × × ×Metal over All Topography, Vertical × × × × × × × ×P-well in Active Region

√ √ √ √ √ √ √ √P-well in Field Region

√ √ √ √ √ √ √ √*Wafer 4 was not tested due to poor metal quality

With the exception of the P+ snake, the N+ and P+ lines show inconsistent results from waferto wafer. This may be due to differences in etching (for example, different electrode position duringetching). The results for wafers B1 and B3 showed differences between the 2 and 4 µm line widths,thus possibly indicating the quality of the alignments of each masking layer. This is consistentwith observations during fabrication, where the fabrication test structures of wafer B2 showed analignment problem. For the metal lines, the continuity results are consistent with our observationsduring fabrication and testing in that metal quality was poor and thus not expected to yield a highpercentage of working devices. For the larger metal lines, the metal itself showed no open circuits,but once measured over features, the metal lines no longer appear continuous. This is confirmed inthe SEM images, found in section 6.3. Finally, the p-wells show continuity in both active and fieldregions for all of the wafers tested.

The isolation structures were tested similarly to the continuity structures to detect any unde-sirable short circuits, which could due to stringers caused by inadequate etching, or the presenceof a particle that would cause the metal combs to come into contact. In the case of isolation, if alarge resistance (small current) is measured, then the structure is adequately isolated.

In our isolation testing, we found that the majority of the structures were well isolated fromone another. In testing the metal lines and the metal over active and poly stripes, all resultedin very low current values (on the order of pico amperes). One unexpected result was ohmic orconducting behavior in the P+ active region for the 4 µm line spacing in all the wafers we tested.This could indicate that one etch step in the process is inadequate. However, all 2 µm spacingsfor the same region yielded isolated structures. On wafer B5, the N+ active region yielded a lowresistance. This may indicate an etching problem that was isolated to this one wafer.



6.3 SEM Test Structures

SEM images were taken of wafers B2 and B5. The wafer was carefully cleaved to isolate the centerdie, then cleaved again to reveal the SEM cross-section structures on each die. The sample wasthen mounted at a 45o angle and inserted into the microscope. The 45o orientation offers twoadvantages. First, images of the sample surface can be taken simultaneously without the need toimage an additional sample. Secondly, when oriented at 90o, the electron interaction with the edgeof the sample can obscure the contrast from the structure itself. By tilting the sample to 45o, wecan minimize this effect to get the best images possible.

In Figure 74, the cross-section of a 20 µm width transistor is imaged. In the figure, the alu-minum contact, the bright feature on the left, and the gate electrode can be clearly seen. Thethin bright line below the gate electrode is the gate oxide. In this image, two distinct layers ontop of the gate electrode can be seen. The layer directly on top of the gate appears to have thesame degree of contrast to that of the gate oxide. It reasonable that some thermal oxide couldhave grown on top of the polysilicon gate, as during the LTO densification step [1], there is 30minreflow which is carried out in steam at a temperature of 950oC. In addition, this steam reflowis bracketed by dry oxidations. Under these conditions, thermal oxidation of the silicon woulddefinitely be reasonable. Oxide growth would occur in all areas of exposed silicon. There is evi-dence of oxide (a layer of lighter color) in the region between the gate and aluminum contact as well.

Figure 74: Cross-Section of 20 µm Gate Width Transistor



A magnified image of the gate electrode and gate oxide is shown in Figure 75. The thicker,darker gate electrode layer shows a fracture surface consistent with that of silicon. The gate oxideis very uniform across the entire image. Since the cleaved edge is oriented at 45o in the SEM,the thicknesses of the layers can not be determined directly from the scale bar (thicknesses fromimage must be multiplied by

√2). From this estimation, the gate oxide is found to be very close

to the 40 nm predicted by analytical calculations and simulations. However, the polysilicon gate isapproximately 380 nm, far from the 500 nm that was deposited. If thermal oxide was indeed grownduring the LTO reflow, then a decreased gate thickness would be reasonable, as the underlyingsilicon would be consumed during oxidation.

Figure 75: Magnified Cross-Section of 20 µm Gate Length Transistor

A large fabrication problem that was encountered during processing was the poor quality of thealuminum metallization. As this was a critical step in forming the contacts to the devices, it wasessential that aluminum depositions be well done. Unfortunately this was not the case. Figure 76shows the surface of the width series transistors. The poor quality of the aluminum is apparentwith the presence of pits and voids on the surface. The aluminum became a problem for otherstructures on the die as well. A surface view of the contact chains is shown in Figure 77, with amagnified image of the region in between the chain links in Figure 78. A continuity test structure,a metal line over all topographical features, is shown in Figure 79. Magnified images of this metalline are found in Figures 80 and 81.

For the metal continuity line, there are distinct regions of metal discontinuity. For example, onthe left side of Figure 79 the aluminum appears as an island, completely isolated from the otherend of the metal line. In the middle of the metal line, Figure 81 there is a section of ”patchy”



Figure 76: Surface of Width Series Transistors

Figure 77: Surface of Contact Chains



Figure 78: Magnified Image of Link within Contact Chains

Figure 79: Surface Image of Continuity Structure: Metal over All Topography



Figure 80: Magnified Image of Continuity Structure End

Figure 81: Magnified Image of Continuity Structure Middle



metal, where the metal uniformity is poor. The regions were there is little or no metal seem tocorrespond to regions of higher topography. If we consider the lithography step, we recall thatthe wafer was coated with photoresist to define the metal lines. Reviewing the process run sheet[1] reveals that for the aluminum lithography, the program on the automated photoresist coater(program 7) was designed to coat the wafer with 1 µm of resist. This was the same program usedat the beginning of the process, where there were no topographical features yet, just blanket oxide.By the end of the processing, features such as the 500 nm poly gate had been patterned onto thewafer. If we consider the thermal oxide formed on top of the poly gate, its effective thickness wouldbe even greater than 500 nm. So, if 1 µm of resist was coated, but would have been spun to leavea flat surface, then regions with higher surface features (such as the poly gate) would have beencoated with less resist. Thus, during etching, it may have been possible for the etching to havegone through the photoresist and start to etch the aluminum. Coupled with the fact that visualobservations of the wafers showed areas with little to no aluminum coverage, it is not surprisingthat metal lines over topographical features failed the continuity testing.

Finally, out of all the devices that were tested, the smallest working transistor was the 1.5 by1.5 µm device, which was also the smallest transistor fabricated on each die. A cross-section of thisdevice is shown in figure 82. Our process successfully patterned this device, the dimensions of whichare roughly twice the minimum feature size possible using conventional lithography techniques inthe Stanford Nanofabrication Facility.

Figure 82: Cross-Section of Minimum Dimension Device


CIS/CMOS-II Modeling/Fabrication/Characterization 7 DISCUSSION

7 Discussion

7.1 Finding The Fault Wafer

As mentioned in Sections 6.1.3 and 6.2.1, Wafer B1 exhibited particularly unusual behavior. Fig-ure 47 indicated a reversal in the p+/FOX/n-Substrate CV curve to indicate nMOS behavior.This could be the result of an additional p-type or an omitted n-type substrate implant. How-ever, MOSFET results do not corroborate this hypothesis. Rather, transistor results suggest somefailure in Wafer B2 based on a much larger Vt range relative to B1 and B3. Given the lack ofsufficient unequivocal evidence supporting either hypothesis, particularly suboptimal Al/Si alloydeposition/coverage, and the prevalence of unexpected device and process characterization results,a conclusive statement regarding the identity of the fault wafer (between B1 and B2) and its cor-responding fault cannot be made confidently.

7.2 pMOSFET Results

For devices with matching threshold voltages (specifically, PMOS1 and PMOS2), simulated resultscoincided remarkably well with fabricated devices. In comparing Figures 4 and 5 with 21 and 24,one can see the similarity, remembering that the simulated figures are two-dimensional and mustbe multiplied by gate width (100 µm in both cases) to mimic the real device characteristics. Thenotable difference is in the non-zero slope of the PMOS2 curve, caused by channel length modula-tion or possibly DIBL. The increase in drain current with increasing drain voltage was a commonproblem seen in many devices, even with a Vg of 0 V.

Also, when comparing simulated subthreshold slopes with those of fabricated devices, we findthe measured values are far worse than those expected. In particular, leakage current under Vg = 0Vand Vd = −0.2V bias conditions could be as high as 1E-10 A for long-channel devices, where thesimulated result was around 1E-14 A for a 100 µm gate width device.

Of particular concern was the wide range of observed threshold voltages. Even on the betterwafers, the standard deviation was slightly less than one volt, which equates to a six-sigma variationof almost six volts!

A possible explanation for these problems is hinted at in the channel mobility calculations.While PMOS2 shows a realistic µP (105 cm2/Vs) for a surface channel device, the value of 216cm2/Vs measured for PMOS1 was much larger than even the low-field surface mobility (160cm2/Vs). However, when using a buried channel model, the calculated value (209 cm2/Vs) ap-proaches the measured value.

It is therefore reasonable to hypothesize that some of the pMOS devices have unintentionally in-troduced buried channels. This could be caused by the introduction of p-type dopants—specificallyBoron—to the surface of the semiconductor. Improper management of thermal budget, a low-quality gate oxide, or an uncontrolled gate deposition that resulted in a columnar crystal structurecould all assist in the gate dopant diffusing through the gate oxide.



In small quantities, Boron would compensate the substrate doping altering the threshold voltage.This would also reduce the drain/channel barrier height, increasing leakage current. In addition,the effectively reduced substrate doping would cause the drain/channel depletion region to reachfurther into the channel at a given drain bias, leading to enhanced DIBL effects. In these quan-tities, the additional introduction of dopants would reduce mobility from the expected value dueto increased impurity scattering. In larger quantities, the introduced dopant could cause a buriedchannel effect, allowing increased hole mobility.

Diffusion of Boron through the gate oxide can explain the positive shift in threshold voltage.However, the negative shifts observed in threshold voltage—especially on wafer B2, where Vt couldbe as large as -14 V—need another explanation. In general, this could be caused by an increasein gate capacitance, or an increase in surface doping. A change in Qf or ΦMS could also causethis, though they are less likely, since the former is only a small effect the a change in the latterwithout a new gate material. While CV measurements could answer the question about reducedgate capacitance, the low quality of our metalization process prevented reliable gate capacitancemeasurements. (See Section 6.3) SEM images, however, indicate a reduction in gate polysiliconthickness to 380 nm, as opposed to the expected 500 nm. As previously suggested, this reductionwas likely caused by the thermal oxidation of the polysilicon gate during LTO deposition. BecauseBoron preferentially segregates into oxide layers, it is possible that this high-temperature growthstep removed Boron from the gate electrode. The overall concentration of Boron in the gate wouldthen be reduced, increasing the severity of gate depletion effects. This would be evidenced by areduction in gate capacitance, leading to a negative shift in threshold voltage.

7.3 Comparison of Wafers B2 and B5: Gate Etch

During testing, it was found that although working pMOS devices were found on every wafer,working nMOS devices were only found on wafer B5. This was an interesting result, and lookingback at the process, the only difference between wafer B5 and wafers B1-B4 was the polysilicongate etch. For wafers B1-B4, the Drytek plasma etcher was used, while for B5, the Applied Mate-rials Precision 5000 (P5000) etcher was used. The P5000 is a magnetically-enhanced reactive ionetch (MERIE) system which has four dedicated chambers and is software controlled. There are twomain differences between the Drytek and P5000. The P5000 is equipped with endpoint detection soetch rates and ”breakthrough” points are easily determined. For the Drytek, completion of etchingis done by visual inspection, is a far more inaccurate technique, and there is wide variability inetch rates between each of the six electrodes in the Drytek. This can lead to the overetch of somewafers, and underetching (and hence short circuits) of other wafers. The second difference betweenthe two system is etch profile. The P5000 can produce better profiles while the Drytek tends toproduce more sloped profiles.

In investigating how the processing affected nMOS differently from pMOS, it is important



to compare nMOS vs. pMOS. In nMOS the shallow junction dopant was Boron, while for pMOS itwas Arsenic. Boron is well known to have a high diffusivity, thus resulting in larger junction depthsfor pMOS (1.26 µm) than for nMOS (0.59 µm) (see Section 2.3 for more details). The smallernMOS junction (both in terms of depth and in the lateral dimension) is then more susceptible togate alignment and definition problems.

SEM images of the cross-sections of wafers B2 (Figure 83) and B5 (Figure 85) show the etchprofiles of the polysilicon gate. In both cases, the etch profile is slightly sloped and no undercuttingis observed. There are no significant differences between the etch profiles of the Drytek and P5000wafers. This leaves us with the role of endpoint detection. It is very likely that in the Drytekcase, there was overetching during the gate etch. Underetching is less likely because this wouldhave caused a short circuit, which would have been detected during the electrical measurements.If overetching did occur, then the nMOS shallow junction regions would have been damaged, andthe source/drain regions could have become disconnected from the channel. This may have beenthe reason for lack of nMOS results.

Figure 83: Cross-Section of Wafer B2

Returning to the SEM images however, does not show significant evidence of overetching. Acontinuous layer of thermal oxide appears to extend from under the gate all the way to under thealuminum contact. If overetching did occur, it may be expected that this thermal oxide layer getsinterrupted near the edge of the gate. In the image, the substrate surface dips slightly to the right,but this is consistent with the consumption of silicon during oxidation (see Section 6.3). However,it could be that overetching does not produce enough contrast in the SEM or that the currentimages of the SEM test structures are not truly representative of the nMOS devices.



Figure 84: Cross-Section of Wafer B5

Figure 85: Cross-Section of Wafer B5, 20 µm Gate Length



7.4 Suggested Process Improvements

7.4.1 Wafer B1 Sheet Resistivity

Sheet resistance data obtained with the four-point technique was observed to be much worse ingeneral for Wafer B1 as compared to Wafer B2 or Wafer B3. This suggests a wafer-wide problemon Wafer B1 resulting in high resistance values. A graph comparing similar structures on the badwafer (Wafer B1) and the good wafer (Wafer B2) is shown in Figure 86.

Figure 86: B1/B2 Sheet Resistance Comparison

Since the resistivity data on Wafer B1 is orders of magnitude higher than Wafers B2, B3, orB5, it can be concluded that there is either a metal discontinuity or a native film of oxide on thecontact pads of these structures. The latter reason is unlikely because the probes were observed tomake good connection with the contact pads. It is therefore reasonable to blame the higher sheetresistance on Wafer B1 as the result of poor metallic continuity. This discontinuity maybe a resultof difficulty achieving uniform aluminum etches above a non-planar LTO layer.

Ideally, the LTO should planarize the surface but in practice the deposited LTO thickness issensitive to gas flow transport and therefore regions in the wafer center and wafer periphery havedifferent thicknesses of LTO. This leads to a non-planar surface and the non-planarity can propa-gate to subsequent higher layers. The consequence of a non-planar LTO for Al etch is that certainregions may experience Al over-etch and other regions may suffer from Al under-etch. This couldpotentially lead to an absence of Al (open circuit), and high sheet resistance data.

Indeed the LTO deposition was observed in the clean room to be non-uniform, even thoughcare was taken during deposition to rotate the wafers to achieve uniform deposition. Nonetheless,some degree of non-uniformity still persists.



To achieve better planarity, one could perform chemical mechanical polishing (CMP) after LTOdeposition. This would lead to a much more planar surface and also give the EE410 students a feelfor the precision of CMP techniques. Using CMP after LTO deposition would significantly improvethe EE410 CIS/CMOS-II process and lead to more working and more consistent wafers.

7.4.2 General Process Improvements

The large number of non-working devices calls for other process improvements in the EE410CIS/CMOS-II process flow. They are:

• Metallization: AluminumWhile most testing showed that the devices had been well fabricated, due to the poor qualityof the aluminum (large number of pits and voids) contacting to the devices became verydifficult. Replacement of the Gryphon deposition is proposed.

• Metallization: PhotoresistAs discussed in Section 6.3, a thicker layer of photoresist may be helpful in avoiding unwantedetching of the aluminum metal lines. Currently the same photoresist thickness is being usedon the bare silicon wafer and at the end of the process when topographical features havealready been patterned.

• Polysilicon Gate Etch: P5000The fact that the only working nMOS devices would be found on wafer 5 is attributed tothe fact that the gate was etched using the P5000 etcher. This is a far better system to use,as the profiles can be improved over the Drytek, and enables the use of essential endpointdetection. See Section 7.3 for more details.


CIS/CMOS-II Modeling/Fabrication/Characterization 8 CONCLUSIONS AND COMMENTS

8 Conclusions and Comments

Over the course of ten weeks, the EE410 CIS/CMOS-II chip was simulated, fabricated, testedand characterized. Analytical calculations of eight chip cross-sections were compared with simula-tions from TSUPREM-IV software. Output from TSUPREM-IV was then used to model transistorcharacteristics using MEDICI software. Upon completion of six weeks of fabrication, the fabrica-tion, process, device and SEM test structures of CIS/CMOS-II were evaluated. Those results, andcomparisons with the calculations and simulations have been discussed in this report.

Analytical calculations based on theoretical models were used to predict device parameters,such as dopant profiles, junction depths and threshold voltages. These predictions were then com-pared with output from simulations from TSUPREM-IV. In general, the analytical calculations andsimulations outputs were in agreement. While TSUPREM-IV failed in predicting junction depths,it gave a much more accurate picture of diffusion as it could include effects such as concentration-dependent diffusivity, oxidation-enhanced diffusivity, dopant segregation and surface reflection.Transient-enhanced diffusion was modeled in both the analytical calculations and the numericalsimulations.

MEDICI simulations of pMOS transistors were completed for 100 µm and 20 µm channel lengths.Output from the 1-D simulations were used, with estimations made for the second dimension. Thiswere compared with the electrical measurements, despite the omission of short channel effects anddrain-induced barrier lowering (DIBL).

Electrical characterization was hampered by the failure of several devices. For nMOS, workingdevices could only be found on wafer 5, and after some a unexplainable catastrophic failure, fur-ther testing on these same transistors could not be completed. Threshold voltages for the nMOSdevices were 0.67 V and 0.30 V for the 100 x 100 µm and 100 x 1.5 µm devices respectively. Shortchannel and narrow-width effects were observed. The minimum sized working transistor was thesmallest transistor fabricated on the chip, which was 1.5 x 1.0 µm. Failures for the nMOS devicesis attributed to shorting–between the gate and drain, the gate and source and both the source anddrain to the gate.

Working pMOS devices were found at all possible gate lengths and widths, even down to thesmallest transistors, though not all devices functioned properly. The major problem encounteredwith pMOS devices was the lack of control over threshold voltage and DIBL. These effects canbe explained when considering the high diffusivity of boron dopant atoms in silicon. Migrationof boron to the device channel or segregation to the growing LTO can cause the large shifts inthreshold voltage and other poor performance characteristics of our pMOS devices.

The process test structures gave some limited insights into the device. Sheet resistances mea-surements, conducted by both 4-Point Probe and Van der Pauw methods, more most consistenton wafers 2 and 3, using the 4-Point Probe method. The contact chains showed problems with thefabrication, most likely due to differences in poly deposition and etching. Metal step coverage wasalso an issue, as it was for continuity testing. Structures, however, were found to be well isolated


CIS/CMOS-II Modeling/Fabrication/Characterization 8 CONCLUSIONS AND COMMENTS

from one another. Contact resistance results showed a mixture of Schottky, ohmic and linear be-havior.

SEM imaging provided more information about the fabrication process. Metal deposition andsubsequent step coverage was the largest issue. Overetching of the polysilicon gate in the Drytek(vs. P5000 etcher) likely contributed to the failure of the nMOS devices in wafers 1-4.

Despite the fabrication issues, a variety of devices were successfully fabricated and characterized.Suggestions made for process improvements will hopefully be implemented for future generationsof EE410.


CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES

9 Appendices

9.1 Appendix A: CIS/CMOS-II Process Flow by Cross-Section



Tab

le50

:M

odel

edP

roce

ssFlo

ws

for

CIS

/CM

OS-

IIC

ross

-Sec

tion

s

Cross-

Sectio

nP

Bla

n-

ket

Impla

nt

Fie

ldSiO

2

FO

XEtch

Sacrifi

cia

lSiO

2

P-W

ell

Double

Im

-pla

nt

P-W

ell

Driv

e-

In

Sacrifi

cal

SiO

2Strip

Gate

SiO

2

Poly

-Si

Deposi-

tio

n

Poly

-Si

Etch

N-S

/D

Im-

pla

nt

BF

2B

lan-

ket

Im-

pla

nt

LT

OD

eposi-

tio

n

LT

OD

ensifi

-catio

n

SiO

2/Si

RIE

Ai/

Si

Deposi-

tio

n

Al/

Si

Etch

1X

XX

XX

XX

XX

XX

XX

X2

XX

XX

XX

XX

XX

XX

X3

XX

XX

XX

XX

XX

XX

4X

XX

XX

XX

XX

XX

X5

XX

XX

XX

XX

XX

XX

XX

XX

6X

XX

XX

XX

XX

XX

XX

XX

7X

XX

XX

XX

XX

XX

XX

X8

XX

XX

XX

XX

XX

XX

XX



9.2 Appendix B: Analytical Calculations (Handwritten Notes)



.



9.3 Appendix C: MATLAB Simulation Code

9.3.1 nMOS Channel

% Jinendra Raja Jain (jrjain)

% EE410 CIS/CMOS-II Process: NMOS Channel Region

% Filename: NMOS_Channel.m

% Parameters

x = [-0.888E-4:0.01E-4:2E-4];

% Blanket Phosphorus

P_Q = 1.75E12;

P_Rp = 0.127E-4;

P_DelRp = 0.0461E-4;

P_Dt = 5.9680E-10;

% Deep Boron

DB_Q = 5E12;

DB_Rp = 0.7005E-4;

DB_DelRp = 0.107E-4;

DB_Dt = 5.8879E-10;

% Shallow Boron

SB_Q = 1.4E12;

SB_Rp = 0.4025E-4;

SB_DelRp = 0.0628E-4;

SB_Dt = 5.8879E-10;

% N-Source/Drain Arsenic

As_Q = 5E15;

As_Rp = -0.1853E-4;

As_DelRp = 0.0261E-4;

As_Dt = 1.9271E-11;

% Blanket BF2

BF2_Q = 1E15;

BF2_Rp = -0.1799E-4;

BF2_DelRp = 0.0353E-4;

BF2_Dt = 5.3614E-10;

% Gaussian Profile Evolutions

Substrate_P_Concen = 8E14;

P_Concen = P_Q/sqrt(2*pi*(P_DelRp^2 + 2*P_Dt))*exp(-(x-P_Rp).^2/(2*(P_DelRp^2

+ 2*P_Dt)));



DB_Concen = DB_Q/sqrt(2*pi*(DB_DelRp^2 + 2*DB_Dt))*exp(-(x-DB_Rp).^2/(2*(DB_DelRp^2

+ 2*DB_Dt)));

SB_Concen = SB_Q/sqrt(2*pi*(SB_DelRp^2 + 2*SB_Dt))*exp(-(x-SB_Rp).^2/(2*(SB_DelRp^2

+ 2*SB_Dt)));

As_Concen = As_Q/sqrt(2*pi*(As_DelRp^2 + 2*As_Dt))*exp(-(x-As_Rp).^2/(2*(As_DelRp^2

+ 2*As_Dt)));

BF2_Concen = BF2_Q/sqrt(2*pi*(BF2_DelRp^2 + 2*BF2_Dt))*exp(-(x-BF2_Rp).^2/

(2*(BF2_DelRp^2 + 2*BF2_Dt)));

% N-Type and P-Type Consolidation

N_Doping = Substrate_P_Concen + P_Concen + As_Concen;

P_Doping = DB_Concen + SB_Concen; + BF2_Concen;

semilogy(x*1E4, N_Doping, x*1E4, P_Doping, ’--’);

vline(-0.8880, ’r:’, ’LTO’);

vline(-0.2266, ’r:’, ’Poly-Si’);

vline(0.2455, ’r:’, ’SiO_2’);

vline(0.2763, ’r:’, ’Si’);

vline(1.7420, ’r:’, ’1.7420\mum’)

title(’NMOS-Channel Impurity Concentration vs. Distance’);

xlabel(’Distance, \itx \rm (\mum)’);

ylabel(’Concentration (cm^-3)’);

h = legend(’N-Type Dopant’, ’P-Type Dopant’);

9.3.2 nMOS Source


% EE410 CIS/CMOS-II Process: NMOS Source/Drain Region

% Filename: NMOS_Source.m

% Parameters

x = [-0.6966E-4:0.01E-4:2E-4];


P_Q = 1.75E12;

P_Rp = 0.127E-4;

P_DelRp = 0.0461E-4;

P_Dt = 5.9680E-10;

% Deep Boron

DB_Q = 5E12;

DB_Rp = 0.7005E-4;


DB_Dt = 5.8879E-10;



% Shallow Boron

SB_Q = 1.4E12;

SB_Rp = 0.4025E-4;

SB_DelRp = 0.0628E-4;

SB_Dt = 5.8879E-10;


As_Q = 5E15;

As_Rp = 0.3147E-4;

As_DelRp = 0.0261E-4;

As_Dt = 1.9271E-11;

% Blanket BF2

BF2_Q = 1E15;

BF2_Rp = 0.3201E-4;

BF2_DelRp = 0.0353E-4;

BF2_Dt = 5.3614E-10;




+ 2*P_Dt)));


+ 2*DB_Dt)));


+ 2*SB_Dt)));


+ 2*As_Dt)));


(2*(BF2_DelRp^2 + 2*BF2_Dt)));





vline(-0.6966, ’r:’, ’Al’);

vline(0.3034, ’r:’, ’Si’);

vline(0.5934, ’r:’, ’0.5934\mum’)

vline(1.7434, ’r:’, ’1.7434\mum’)

title(’NMOS-Source/Drain Impurity Concentration vs. Distance’);






9.3.3 pMOS Channel


% EE410 CIS/CMOS-II Process: PMOS Channel Region

% Filename: PMOS_Channel.m

% Parameters

x = [-0.8880E-4:0.01E-4:2E-4];


P_Q = 1.75E12;

P_Rp = 0.127E-4;

P_DelRp = 0.0461E-4;

P_Dt = 3.2273E-10;

% Blanket BF2

BF2_Q = 1E15;

BF2_Rp = -0.1799E-4;

BF2_DelRp = 0.0353E-4;

BF2_Dt = 2.1596E-10;




+ 2*P_Dt)));


(2*(BF2_DelRp^2 + 2*BF2_Dt)));


N_Doping = Substrate_P_Concen + P_Concen;

P_Doping = BF2_Concen;


vline(-0.8880, ’r:’, ’LTO’);

vline(-0.2266, ’r:’, ’Poly-Si’);

vline(0.2455, ’r:’, ’SiO_2’);

vline(0.2763, ’r:’, ’Si’);

title(’PMOS-Channel Impurity Concentration vs. Distance’);




9.3.4 pMOS Source


% EE410 CIS/CMOS-II Process: PMOS Source/Drain Region



% Filename: PMOS_Source.m

% Parameters

x = [-0.6966E-4:0.01E-4:2E-4];


P_Q = 1.75E12;

P_Rp = 0.127E-4;

P_DelRp = 0.0461E-4;

P_Dt = 3.2273E-10;

% Blanket BF2

BF2_Q = 1E15;

BF2_Rp = 0.3201E-4;

BF2_DelRp = 0.0353E-4;

BF2_Dt = 2.1596E-10;




+ 2*P_Dt)));


(2*(BF2_DelRp^2 + 2*BF2_Dt)));





vline(-0.6966, ’r:’, ’Al’);

vline(0.3034, ’r:’, ’Si’);

vline(1.2634, ’r:’, ’1.2634\mum’);

title(’PMOS-Source/Drain Impurity Concentration vs. Distance’);




9.3.5 nMOS Metal


% EE410 CIS/CMOS-II Process: NMOS Metal Region

% Filename: NMOS_Metal.m

% Parameters

x = [-1.8775E-4:0.01E-4:2E-4];




P_Q = 1.75E12;

P_Rp = 0.127E-4;

P_DelRp = 0.0461E-4;

P_Dt = 5.9680E-10;

% Deep Boron

DB_Q = 5E12;

DB_Rp = 0.1624E-4;


DB_Dt = 5.8879E-10;

% Shallow Boron

SB_Q = 1.4E12;

SB_Rp = -0.1356E-4;

SB_DelRp = 0.0628E-4;

SB_Dt = 5.8879E-10;


As_Q = 5E15;

As_Rp = -0.1863E-4;

As_DelRp = 0.0261E-4;

As_Dt = 1.9271E-11;

% Blanket BF2

BF2_Q = 1E15;

BF2_Rp = -0.1809E-4;

BF2_DelRp = 0.0353E-4;

BF2_Dt = 5.3614E-10;




+ 2*P_Dt)));


+ 2*DB_Dt)));


+ 2*SB_Dt)));


+ 2*As_Dt)));


(2*(BF2_DelRp^2 + 2*BF2_Dt)));







vline(-1.8775, ’r:’, ’Al’);

vline(-0.8775, ’r:’, ’SiO_2’);

vline(0.2813, ’r:’, ’Si’);

vline(1.1725, ’r:’, ’1.1725\mum’)

title(’NMOS-Metal Impurity Concentration vs. Distance’);




9.3.6 nMOS Poly


% EE410 CIS/CMOS-II Process: NMOS Polysilicon Region

% Filename: NMOS_Poly.m

% Parameters

x = [-1.3889E-4:0.01E-4:2E-4];


P_Q = 1.75E12;

P_Rp = 0.127E-4;

P_DelRp = 0.0461E-4;

P_Dt = 5.9680E-10;

% Deep Boron

DB_Q = 5E12;

DB_Rp = 0.1624E-4;


DB_Dt = 5.8879E-10;

% Shallow Boron

SB_Q = 1.4E12;

SB_Rp = -0.1356E-4;

SB_DelRp = 0.0628E-4;

SB_Dt = 5.8879E-10;


As_Q = 5E15;

As_Rp = -0.6863E-4;

As_DelRp = 0.0261E-4;



As_Dt = 1.9271E-11;

% Blanket BF2

BF2_Q = 1E15;

BF2_Rp = -0.6809E-4;

BF2_DelRp = 0.0353E-4;

BF2_Dt = 5.3614E-10;




+ 2*P_Dt)));


+ 2*DB_Dt)));


+ 2*SB_Dt)));


+ 2*As_Dt)));


(2*(BF2_DelRp^2 + 2*BF2_Dt)));





vline(-1.3889, ’r:’, ’LTO’);

vline(-0.7276, ’r:’, ’Poly-Si’);

vline(-0.2555, ’r:’, ’SiO_2’);

vline(0.2630, ’r:’, ’Si’);

vline(1.1811, ’r:’, ’1.1811\mum’)

title(’NMOS-Poly Impurity Concentration vs. Distance’);




9.3.7 pMOS Metal


% EE410 CIS/CMOS-II Process: PMOS Metal Region

% Filename: PMOS_Metal.m

% Parameters

x = [-1.8775E-4:0.01E-4:2E-4];




P_Q = 1.75E12;

P_Rp = 0.127E-4;

P_DelRp = 0.0461E-4;

P_Dt = 3.2273E-10;

% Blanket BF2

BF2_Q = 1E15;

BF2_Rp = -0.1809E-4;

BF2_DelRp = 0.0353E-4;

BF2_Dt = 2.1596E-10;




+ 2*P_Dt)));


(2*(BF2_DelRp^2 + 2*BF2_Dt)));





vline(-1.8775, ’r:’, ’Al’);

vline(-0.8775, ’r:’, ’SiO_2’);

vline(0.2813, ’r:’, ’Si’);

title(’PMOS-Metal Impurity Concentration vs. Distance’);




9.3.8 pMOS Poly


% EE410 CIS/CMOS-II Process: PMOS Poly Region

% Filename: PMOS_Poly.m

% Parameters

x = [-1.3889E-4:0.01E-4:2E-4];


P_Q = 1.75E12;

P_Rp = 0.127E-4;

P_DelRp = 0.0461E-4;



P_Dt = 3.2273E-10;

% Blanket BF2

BF2_Q = 1E15;

BF2_Rp = -0.6809E-4;

BF2_DelRp = 0.0353E-4;

BF2_Dt = 2.1596E-10;




+ 2*P_Dt)));


(2*(BF2_DelRp^2 + 2*BF2_Dt)));





vline(-1.3889, ’r:’, ’LTO’);

vline(-0.7276, ’r:’, ’Poly-Si’);

vline(-0.2555, ’r:’, ’SiO_2’);

vline(0.2630, ’r:’, ’Si’);

title(’PMOS-Poly Impurity Concentration vs. Distance’);






9.4 Appendix D: TSUPREM-IV Simulation Code

9.4.1 Substrate

$ Jinendra Raja Jain (jrjain)

$ EE410 CIS/CMOS-II Process: Starting Substrate with Field Oxidation

$ Filename: Substrate.inp

$ Dopant Diffusion Model

METHOD PD.FULL

$ Wafer Initialization

INITIALIZE <100> Material=Silicon Phosphorus=8e14 Width=1.5 Dx=.005

$ Wafer Scribing

$ Standard Photoresist Strip

$ Standard Pre-Diffusion Clean

$ Phosphorus Blanket Substrate Implant

IMPLANT Phosphorus Dose=1.75e12 Energy=100 Tilt=7 Gaussian


$ Field Oxidation (Target Thickness = 500nm)

DIFFUSION Time=35 Temperature=800 T.Final=1000 Argon

DIFFUSION Time=10 Temperature=1000 DryO2

DIFFUSION Time=100 Temperature=1000 Steam



$ Ouput Results

OPTION Device=postscript Plot.Out="PS_Files/Substrate.ps"

PRINT Layers

SELECT Z=Log10(Active(Phosphorus))

PLOT.1D Bottom=14 Top=21 Right=2

SAVEFILE Out.File=Struct_Files/Substrate.str

9.4.2 Active


$ EE410 CIS/CMOS-II Process: Active Region

$ Filename: Active.inp


METHOD PD.FULL




INITIALIZE In.File=Struct_Files/Substrate.str

$ Photolithography #1 - Active Area

$ SiO2 Etch in 6:1 BOE (Buffered (HF) Oxide Etch)

ETCH Oxide All



$ Sacrificial Oxidation (Target Thickness = 40nm)






$ Output Results

PRINT Layers

SAVEFILE Out.File=Struct_Files/Active.str

9.4.3 Field


$ EE410 CIS/CMOS-II Process: Field Region

$ Filename: Field.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/Substrate.str

$ Photolithography #1 - Active Area



$ Sacrificial Oxidation (Target Thickness = 40nm)








$ Output Results

PRINT Layers

SAVEFILE Out.File=Struct_Files/Field.str

9.4.4 nMOS Active


$ EE410 CIS/CMOS-II Process: NMOS Active Region

$ Filename: NMOS_Active.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/Active.str

$ Photolithography #2 - P-Well

$ P-Well Double Implant

IMPLANT Boron Dose=5e12 Energy=180 Tilt=7 Gaussian

IMPLANT Boron Dose=1.4e12 Energy=50 Tilt=7 Gaussian


$ Standard Pre-Diffusion Clean with 50:1 HF Dip

$ P-Well Drive-In


DIFFUSION Time=60 Temperature=1000 Argon



$ Sacrificial Oxide Strip (Etch 60nm (60nm includes 50% overetch))

Etch Oxide Old.Dry Thickness=.06

$ Gate Oxidation (Target Thickness = 40nm)






$ Polysilicon Deposition (Target Thickness = 500nm)

DEPOSITION Polysilicon Thickness=.5



$ Photolithography #3 - Polysilicon

$ Output Results

PRINT Layers

SAVEFILE Out.File=Struct_Files/NMOS_Active.str

9.4.5 pMOS Active


$ EE410 CIS/CMOS-II Process: PMOS Active Region

$ Filename: P_Active.inp


METHOD PD.Full


INITIALIZE In.File=Struct_Files/Active.str




$ P-Well Drive-In
















$ Output Results



PRINT Layers

SAVEFILE Out.File=Struct_Files/PMOS_Active.str

9.4.6 nMOS Field


$ EE410 CIS/CMOS-II Process: NMOS Field Region

$ Filename: NMOS_Field.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/Field.str


$ P-Well Double Implant

IMPLANT Boron Dose=5e12 Energy=180 Tilt=7 Gaussian

IMPLANT Boron Dose=1.4e12 Energy=50 Tilt=7 Gaussian



$ P-Well Drive-In


















$ Output Results

PRINT Layers

SAVEFILE Out.File=Struct_Files/NMOS_Field.str

9.4.7 pMOS Field


$ EE410 CIS/CMOS-II Process: PMOS Field Region

$ Filename: P_Field.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/Field.str




$ P-Well Drive-In
















$ Output Results

PRINT Layers



SAVEFILE Out.File=Struct_Files/PMOS_Field.str

9.4.8 nMOS Channel


$ EE410 CIS/CMOS-II Process: NMOS Channel Region

$ Filename: NMOS_Channel.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/NMOS_Active.str


$ Photolithography #4 - N-Select

$ N-Source/Drain Implant

IMPLANT Arsenic Dose=5e15 Energy=100 Tilt=7 Gaussian

$ Matrix Photoresist Strip



$ Boron Blanket Implant

IMPLANT BF2 Dose=1e15 Energy=80 Tilt=7 Gaussian


$ LTO Deposition (Undoped Target Thickness = 50nm, Phosphorus-Doped (8%)

$ Target Thickness = 550nm)

DEPOSITION Oxide Thickness=.6


$ LTO Densification






$ Photolithography #5 - Contact Holes

$ Ash Photoresist





$ Aluminum/Silicon Alloy Deposition (Target Thickness = 10000A)

DEPOSITION Aluminum THICKNESS=1

$ Photolithography #6 - Metal

$ Dry Aluminum Etch

ETCH Aluminum All

$ Silicon Freckle Etch

$ PRX-127 Photoresist Strip

$ PRS-1000 Metal Cleanu

$ Anneal and Alloy (FGA Anneal with 10% H2 in N2)

$ Output Results

OPTION Device=postscript Plot.Out="PS_Files/NMOS_Channel.ps"

SELECT Z=Doping

PRINT Layers

SELECT Z=Log10(Boron) Title="NMOS Channel Impurity Concentration"

+ Label = "Log(Concentration) (cm-3)"

PLOT.1D Line.Type=1 Color=1 Symbol=1 Left=-2 Right=2 Top=21

SELECT Z=Log10(Phosphorus)

PLOT.1D !Axes !Clear Line.Type=2 Color=2 Symbol=2

SELECT Z=Log10(Arsenic)


LABEL X=1 Y=20 LABEL="Boron" Color=1 Symbol=1

LABEL X=1 Y=19.5 LABEL="Phosphorus" Color=2 Symbol=2

LABEL X=1 Y=19 LABEL="Arsenic" Color=3 Symbol=3

ELECTRICAL Resistance

ELECTRICAL Threshold NMOS V="-20 20 0.01" Qss=5e10

9.4.9 nMOS Source


$ EE410 CIS/CMOS-II Process: NMOS Source/Drain Region

$ Filename: NMOS_Source.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/NMOS_Active.str

$ Polysilicon Plasma Etch



Etch Polysilicon All















$ LTO Densification







$ SiO2 RIE in AMT 8100

ETCH Oxide All

$ Silicon Etch (Contact Holes)

$ Polymer Removal

$ Ash Photoresist









$ PRS-1000 Metal Clean


$ Output Results

OPTION Device=postscript Plot.Out="PS_Files/NMOS_Source.ps"

SELECT Z=Doping

PRINT Layers

SELECT Z=Log10(Boron) Title="NMOS Source/Drain Impurity Concentration"











9.4.10 pMOS Channel


$ EE410 CIS/CMOS-II Process: PMOS Channel Region

$ Filename: PMOS_Channel.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/PMOS_Active.str















$ LTO Densification







$ Ash Photoresist






$ Dry Aluminum Etch

ETCH Aluminum All





$ Output Results

OPTION Device=postscript Plot.Out="PS_Files/PMOS_Channel.ps"

SELECT Z=Doping

PRINT Layers

SELECT Z=Log10(Boron) Title="PMOS Channel Impurity Concentration"













ELECTRICAL Threshold PMOS V="-20 20 0.01" Qss=5e10

9.4.11 pMOS Source


$ EE410 CIS/CMOS-II Process: PMOS Source/Drain Region

$ Filename: PMOS_Source.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/PMOS_Active.str















$ LTO Densification







$ SiO2 RIE in AMT 8100



ETCH Oxide All

$ Silicon Etch (Contact Holes)

$ Polymer Removal

$ Ash Photoresist









$ Output Results

OPTION Device=postscript Plot.Out="PS_Files/PMOS_Source.ps"

SELECT Z=Doping

PRINT Layers

SELECT Z=Log10(Boron) Title="PMOS Source/Drain Impurity Concentration"











9.4.12 nMOS Metal


$ EE410 CIS/CMOS-II Process: NMOS Metal Region

$ Filename: NMOS_Metal.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/NMOS_Field.str



















$ LTO Densification







$ Ash Photoresist









$ Output Results



OPTION Device=postscript Plot.Out="PS_Files/NMOS_Metal.ps"

SELECT Z=Doping

PRINT Layers

SELECT Z=Log10(Boron) Title="NMOS Metal Impurity Concentration"












9.4.13 nMOS Poly


$ EE410 CIS/CMOS-II Process: NMOS Poly Region

$ Filename: NMOS_Poly.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/NMOS_Field.str

















$ LTO Densification







$ Ash Photoresist






$ Dry Aluminum Etch

ETCH Aluminum All





$ Output Results

OPTION Device=postscript Plot.Out="PS_Files/NMOS_Poly.ps"

SELECT Z=Doping

PRINT Layers

SELECT Z=Log10(Boron) Title="NMOS Poly Impurity Concentration"














9.4.14 pMOS Metal


$ EE410 CIS/CMOS-II Process: PMOS Metal Region

$ Filename: PMOS_Metal.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/PMOS_Field.str















$ LTO Densification







$ Ash Photoresist











$ Output Results

OPTION Device=postscript Plot.Out="PS_Files/PMOS_Metal.ps"

SELECT Z=Doping

PRINT Layers

SELECT Z=Log10(Boron) Title="PMOS Metal Impurity Concentration"












9.4.15 pMOS Poly


$ EE410 CIS/CMOS-II Process: PMOS Poly Region

$ Filename: PMOS_Poly.inp


METHOD PD.FULL


INITIALIZE In.File=Struct_Files/PMOS_Field.str















$ LTO Densification







$ Ash Photoresist






$ Dry Aluminum Etch

ETCH Aluminum All





$ Output Results

OPTION Device=postscript Plot.Out="PS_Files/PMOS_Poly.ps"

SELECT Z=Doping

PRINT Layers

SELECT Z=Log10(Boron) Title="PMOS Poly Impurity Concentration"







9.5 Appendix E: MEDICI Simulation Code

Presented below are the three MEDICI input files used to extract pMOSFET parameters forthe 20 µm length transistor. In order to model the 100 µm transistor, identical files were used,except certain parameters were modified, as specified in the first input file.

TITLE EE410 PMOS Transistor Simulations, 20 um Transistor

COMMENT Specify a rectangular mesh

MESH SMOOTH=1

X.MESH WIDTH=28 H1=1

$ Gate Length +8um

Y.MESH N=1 L=0

Y.MESH N=2 L=0.500

Y.MESH N=4 L=0.540

Y.MESH DEPTH=1.54 H1=0.05

Y.MESH DEPTH=5.54 H1=0.5

COMMENT Eliminate some unnecessary substrate nodes

ELIMIN COLUMNS Y.MIN=2.5

ELIMIN ROWS Y.MIN=3.5

COMMENT Specify oxide and silicon regions

REGION SILICON IY.MIN=4 NAME=BODY

REGION OXIDE IY.MAX=4

REGION POLYSILI X.MIN=4 X.MAX=24 IY.MAX=2 NAME=GATE

$x.max=gate+4

COMMENT Electrode definition

ELECTR NAME=Gate TOP X.MIN=4 X.MAX=24

$ X.MAX=gate+4

ELECTR NAME=Substrate BOTTOM

ELECTR NAME=Source X.MIN=1 X.MAX=3 IY.MAX=4

ELECTR NAME=Drain X.MIN=25 X.MAX=27 IY.MAX=4

$ X.MIN=GATE+5

$ X.MAX=GATE+7

COMMENT Specify impurity profiles and fixed charge\\

+ background substrate doping \\

PROFILE N-TYPE N.PEAK=1E15 UNIFORM Y.MIN=0.540\\

+ OUT.FILE=DPdopproDS.out REGION=BODY\\

PROFILE N-TYPE N.PEAK=4.43E16 Y.CHAR=0.13 Y.MIN=0.54 REGION=BODY\\

COMMENT Source Implant\\



PROFILE IN.FILE=psourcets.out 1d.ascii n.column=3 y.column=2

+ p.column=4 x.min=0.0 width=4 xy.rat=.75 y.offset=0.54

+ REGION=BODY

$PROFILE P-TYPE N.PEAK=3E19 Y.JUNCTION=0.4 X.MIN=0.0 WIDTH=4 Y.MIN=0.065

$ + XY.RAT=.75

COMMENT Drain Implant

PROFILE IN.FILE=psourcets.out 1d.ascii n.column=3 y.column=2

+ p.column=4 x.min=24 width=4 xy.rat=.75 y.offset=0.54

+ REGION=BODY

$ x.min=gate+4

$ PROFILE P-TYPE N.PEAK=3E19 Y.JUNCTION=0.4 X.MIN=104 WIDTH=4

$ + XY.RAT=.75 Y.MIN=0.065

COMMENT Gate profile

PROFILE IN.FILE=pchants.out 1d.ascii n.column=3 y.column=2 p.column=4

+ X.MIN=4 REGION=GATE X.MAX=24 xy.rat=0.01 y.offset=0.54

$ X.MAX=GATE+4

$ PROFILE P-TYPE N.PEAK=5E18 Y.CHAR=0.01

PLOT.2D GRID TITLE="Initial Grid-PMOS 100 um" FILL SCALE $ +

DEVICE=postscript PLOT.OUT=NoHaloInGri.eps

COMMENT Regrid on doping REGRID DOPING LOG IGNORE=OXIDE

RATIO=2 SMOOTH=1 + IN.FILE=DPdopproDS.out PLOT.2D GRID

TITLE="Doping Regrid-PMOS 100 um" FILL SCALE $ +

DEVICE=postscript PLOT.OUT=NoHaloDopRe.eps

COMMENT Specify contact parameters

CONTACT NAME=Gate

CONTACT NAME=Source

CONTACT NAME=Drain

CONTACT NAME=Substrate

COMMENT Specify physical models to use

MODELS CONMOB FLDMOB SRFMOB2

COMMENT Symbolic factorization, solve, regrid on potential

SYMB CARRIERS=2

METHOD ICCG DAMPED

SOLVE



REGRID POTEN IGNORE=OXIDE RATIO=.2 MAX=1 SMOOTH=1 +

IN.FILE=DPdopproDS.out + OUT.FILE=DPmeshsolnMS.out PLOT.2D

GRID TITLE="Potential Regrid-PMOS" FILL SCALE $ +

DEVICE=postscript PLOT.OUT=NoHaloPotRe.eps

COMMENT Solve using the refined grid, save solution for later use

SYMB CARRIERS=2

SOLVE OUT.FILE=DPinitS

COMMENT Extract init channel length to aid in refining structure

EXTRACT MOS.PARA

COMMENT Impurity profile plots PLOT.1D DOPING X.START=.0

X.END=28 Y.START=0.541 Y.END=0.541 + Y.LOG POINTS

BOT=1E15 TOP=1E21 COLOR=2 + TITLE="Channel Impurity

Profile-PMOS 100" $x.end=gate+8 $ + DEVICE=postscript

PLOT.OUT=NoHaloChDop.eps LABEL LABEL="Y = 0.0001 um" PLOT.1D

DOPING X.START=2 X.END=2 Y.START=0 Y.END=2.5 + Y.LOG

POINTS BOT=1E15 TOP=1E22 COLOR=2 + TITLE="SOURCE Impurity

Profile" $ + DEVICE=postscript PLOT.OUT=NoHaloLDDDop.eps

LABEL LABEL="X = 2 um" PLOT.1D DONORS X.START=14 X.END=14

Y.START=0 Y.END=2.5 + Y.LOG POINTS BOT=1E14 TOP=1E22

COLOR=2 + TITLE="Gate Impurity Profile" $ +

DEVICE=postscript PLOT.OUT=NoHaloGatDop.eps LABEL LABEL="X = 14

um-middle Channel Vertical Profile" PLOT.1D ACCEPTOR X.START=54

X.END=14 Y.START=0 Y.END=2.5 + POINTS COLOR=4 UNCHANGE

PLOT.2D BOUND TITLE="Impurity Contours-100 um PMOS" FILL SCALE

$ + DEVICE=postscript PLOT.OUT=NoHaloImpCon.eps CONTOUR

DOPING LOG MIN=16 MAX=20 DEL=.5 COLOR=2 CONTOUR DOPING LOG

MIN=-16 MAX=-15 DEL=.5 COLOR=1 LINE=2



TITLE EE410 PMOS Transistor Simulations, 20 um Transistor

COMMENT Calculate Gate Characteristics

COMMENT Read in simulation mesh

MESH IN.FILE=DPmeshsolnMS.out

COMMENT Read in saved solution

LOAD IN.FILE=DPinitS

COMMENT Use Newton’s method for the solution

SYMB NEWTON CARRIERS=1 HOLES

COMMENT Setup log file for IV data for a low Vd

LOG OUT.FILE=DPgaLowVd.out

COMMENT Solve for Vds=-0.01 and then ramp gate

SOLVE V(Drain)=-.2

SOLVE V(Gate)=0 ELEC=Gate VSTEP=-.1 NSTEP=51

COMMENT Extract parameter Vth for device refinement

EXTRACT MOS.PARA

COMMENT Plot Ids vs. Vgs

PLOT.1D Y.AXIS=I(Drain) X.AXIS=V(Gate) POINTS COLOR=2

+ TITLE="Gate Characteristics--Low Vds"

LABEL LABEL="Vds = -0.2v" X=-1.6 Y=-0.7E-6

COMMENT Setup log file for IV data for a high Vds

LOG OUT.FILE=DPgaHighVd.out

COMMENT Solve for Vds=-4 and then ramp gate

SOLVE V(Drain)=-4

SOLVE V(Gate)=0 ELEC=Gate VSTEP=-.1 NSTEP=51

COMMENT Extract parameter Vth just for fun

EXTRACT MOS.PARA

COMMENT Plot Ids vs. Vgs for high Vds

PLOT.1D Y.AXIS=I(Drain) X.AXIS=V(Gate) POINTS COLOR=2

+ TITLE="Gate Characteristics--High Vds"

LABEL LABEL="Vds = -1.2v" X=-1.6 Y=-0.7E-4

COMMENT Plot Results simultaneously

PLOT.1D IN.FILE=DPgaHighVd.out Y.AXIS=I(Drain) X.AXIS=V(Gate)



+ POINTS COLOR=4 LINE.TYP=2 SYMBOL=1

+ TITLE="Subthreshold Behavior" Y.LOGARI

LABEL LABEL="Vds = -4.0v" COLOR=4 SYMBOL=1

PLOT.1D IN.FILE=DPgaLowVd.out Y.AXIS=I(Drain) X.AXIS=V(Gate)

+ POINTS COLOR=2 LINE.TYP=1 SYMBOL=2 Y.LOGARI UNCHANGE

LABEL LABEL="Vds = -0.2v" X=-3 COLOR=2 SYMBOL=2



TITLE EE410 PMOS Transistor Simulatrions, 20 um Transistor

COMMENT Calculate Drain Characteristics

COMMENT Read in simulation mesh

MESH IN.FILE=DPmeshsolnMS.out

COMMENT Read in initial solution

LOAD IN.FILE=DPinitS

COMMENT Do a Poisson solve only to bias the gate

SYMB CARRIERS=1 HOLES

METHOD ICCG DAMPED

SOLVE V(Gate)=0.0

COMMENT Now solve for new gate voltage


LOG OUT.FILE=DPdrainIV00.out

SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52


METHOD ICCG DAMPED

SOLVE V(Gate)=-0.5

COMMENT Use Newton’s method and solve for holes


COMMENT Setup log file for IV data


COMMENT Ramp the drain



METHOD ICCG DAMPED

SOLVE V(Gate)=-1.0






METHOD ICCG DAMPED

SOLVE V(Gate)=-1.5







COMMENT Reset gate bias for next run


METHOD ICCG DAMPED

SOLVE V(Gate)=-2






METHOD ICCG DAMPED

SOLVE V(Gate)=-2.5





COMMENT Repeat for each gate voltage value


METHOD ICCG DAMPED

SOLVE V(Gate)=-3





METHOD ICCG DAMPED

SOLVE V(Gate)=-3.5








METHOD ICCG DAMPED

SOLVE V(Gate)=-4





METHOD ICCG DAMPED

SOLVE V(Gate)=-4.5




COMMENT Plot Ids vs. Vds Curves

PLOT.1D Y.AXIS=I(Drain) X.AXIS=V(Drain) LINE.TYP=1

+ SYMBOL=1 POINTS COLOR=1

+ TITLE="Drain Output Characteristics"

LABEL LABEL="Vg=-4.5" X=-1 Y=-3.3E-6 COLOR=1 SYMBOL=1

PLOT.1D IN.FILE=DPdrainIV40.out Y.AXIS=I(Drain) X.AXIS=V(Drain)

+ LINE.TYP=2 SYMBOL=2 POINTS COLOR=2 UNCHANGE



LABEL LABEL="Vg=-3.5" X=-1 Y=-3.1E-6 COLOR=3 SYMBOL=3





LABEL LABEL="Vg=-2.5" X=-1 Y=-2.9e-6 COLOR=5 SYMBOL=5










9.6 Appendix F: Individual Group Member Contributions

Table 51 presents the contributions made by each group member during the testing/characterizationphase of the project.

Table 51: Individual Group Member Contributions - Testing/Characterization

Member ContributionsDeji Akinwande nMOSFETs, Sheet ResistivityAaron Gibby pMOSFETs, Parasitics, Continuity, Isolation

Jinendra Raja Jain MOSCAPs, Diodes, Contact Chains, Contact ResistanceSaeroonter Oh MOSCAPs, Diodes, Contact Chains, Contact Resistance

Shiyu Sun nMOSFETs, Sheet ResistivityGloria Wong pMOSFETs, Parasitics, Continuity, Isolation

Table 52 presents the contributions made by each group member during the report-writingphase of the project.

Table 52: Individual Group Member Contributions - Report

Member ContributionsDeji Akinwande Secs. 6.1.1, 6.2.1Aaron Gibby Secs. 5, 6.1.2, 7.2, 8, 9

Jinendra Raja Jain Management/compilation/editing, Secs. 1, 2, 3, 4, 6.1.3, 6.1.4, 7.1, 9Saeroonter Oh Secs. 6.2.2, 6.2.3, 6.1.4

Shiyu Sun Secs. 6.2.1Gloria Wong Secs. 1, 6.1.2, 6.2.4, 6.3, 7.3, 7.4, 8


CIS/CMOS-II Modeling/Fabrication/Characterization REFERENCES

References

[1] K. Saraswat, EE410 CMOS Process Schedule, Stanford University, Stanford, CA, Winter 2004-05.

[2] K. Saraswat, EE410 TSUPREM-IV simulation handout, Stanford University, Stanford, CA, Winter2004-05.

[3] Plummer, Deal, and Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling, UpperSaddle River, NJ, USA: Prentice Hall, 2000.

[4] Synopsys, TSUPREM-4: Two-Dimensional Process Simulation Program - User Manual (ver. 2002.4),Feb. 2003.

[5] Pierret, Robert F., Semiconductor Device Fundamentals, Reading, MA, USA: Addison-Wesley, 1996.

[6] Sun and Plummer, IEEE TED, 27, 1980: p. 1497.

[7] S. Simon Wong, EE316 Course notes, Stanford University, Stanford, CA, Winter 2003-04.

[8] K. Saraswat, EE410 CIS/CMOS-II Instruction Manual, Stanford University, Stanford, CA, Winter2004-05.

[9] Walton, A.J., Microelectronic Test Structures

[10] J. Harris, EE216 Course Notes, Stanford University, Stanford, CA, Fall 2004-05.

* This report was prepared using LATEX.


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