1

POP IP

Overview - Fast

deployment of ARM

Technology

2

Agenda

POP™ IP Introduction

ARM® 28nm Physical IP

Logic Products for Advanced Platforms

Memory Products for Advanced Platforms

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POP IP

Introduction

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Many Factors in SoC Design Tradeoffs

Power Factors

IP architecture; 9 track Vs 12 track

Power management and DVFS

Vt and channel length options

Performance Factors

IP architecture; 9 track Vs 12 track

Vt and channel length options

Over drive

Area Factors

Cache sizes; L1 and L2

Single, Dual or Quad core

IP architecture; 9 track Vs 12 track

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ARM POP Solution Delivers

Performance

Time To Market

Proven Results

Cortex™-A15, Cortex-A7 & Cortex-A9 POPs deliver market leading

performance and power numbers

Knowledge transfer from ARM through product deployments

and expert support options

Partners have achieved 1GHz+ implementations of Cortex-A9

within 4-6 weeks of deployment

Production silicon on TSMC 40nm G, 40nm LP & SEC 32nm LP

Numerous production designs underway at 28nm

Early enablement

First to support new cores with industry standard Physical IP

Early enablement of new processor licensees

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POP: Implementation Exploration and Tuning

Our POP IP will provide you

with some expertise to seek out

the most optimal solutions

Eliminate a few variables at a

time by using detailed result

analysis

Early experience with the

design and process node

Early exploration with libraries

and new methodologies

Co-working across

development teams,

implementation and Physical IP

development; we don’t

develop in isolation

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Implementation trade offs at 28nm

Need to pull the right levers to get

the desired result

Highest performance

Lowest power (efficiency)

Balanced implementation

Standard cell architectures

SC9 & SC12

Devices

uLVT, LVT, SVT, HVT & uHVT

Channel lengths

C31, C35 & C38

Voltage domains

0.8v, 0.9v or 1.0v operation

Power management

DVFS, Power gating

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POP IP: Core Optimized Physical IP

Core-optimized Memories

Core-optimized Logic

40LP 40LE 40G

28HP 28HPM

28 SLP

New Processes

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POP: ARM Certified Benchmarking

New Cores

Mali support and next generation CPU

support in development

Core-Optimized

Physical IP

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POP IP: Unique ARM Core Expertise

New Optimizations

Unique ARM low power

implementation expertise

Proprietary ARM POP

leakage reduction technology

Enhanced hierarchical

multi-core reference flow

Continuous improvement

of PPA results

ARM ActiveAssist™

Core-Optimized

Physical IP

ARM

Certified

Benchmarking

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ARM POP Technology

New Processes

New Cores

New Optimizations

Core-Hardening Acceleration by ARM

Over 28 licenses, including…

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Widest Coverage

of Today’s Cores

POP IP: Unique Solution For ARM Cores

Unique ARM Core

Expertise

Earliest Foundry

Collaboration

Earliest Availability

for New Cores

Core-Hardening Acceleration by ARM

Continuous

Improvement

ARM ActiveAssist

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ARM POP Leakage Reduction Technology

New technology for 2012

Available only from ARM

Standard in new POP IP products

Leakage Savings:

20% for Power Optimized

35% for Performance Optimized

>50%versus non-POP design

2011 P

OP

Desig

n

35%

lower

2011

Technology

2012 Leakage

Technology

Cortex-A9 Dual Core

TSMC 28HPM

1

0.5

0.25

0.75

Non

-PO

P D

esig

n

SC

12

Perf

. O

ptim

ize

d

Relative Leakage

20%

lower

SC

9 P

ow

er

Op

tim

ize

d

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ARM 28nm Physical IP

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Increased Demands on Physical IP

DFM-optimized pattern-based

layout

ARM invests to become the leader

in layout automation

New logic & memory architecture;

Color awareness

Second generation write assist

standard in all memories

New logic and memory

products and features

Design rule complexity &

manufacturability

PDK churn &

time-to-market risk

Double patterning,

Variability

Voltage scaling challenge

Power and Density

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Physical IP Advanced Technology Timeline

2009 2010 2011 2012 2013 2014 2015 2016

Production

Tape Outs

R&D

Test Chips 14nm

Production

Tape Outs

R&D

Test Chips 20nm

Production

Tape Outs

R&D

Test Chips 28nm

Development Under Way,

Evaluation IP Now

Early Development

Under Way

IP

Available Lead Partner

Engagement

Lead Partner

Engagement

Lead Partner

Engagement

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Physical IP Advanced Technology Timeline

Production

Tape Outs

R&D

Test Chips 28nm IP

Available Lead Partner

Engagement

Comprehensive 28nm solutions rolled out

Production IP on multiple 28nm processes

IP designed-in on multiple high-volume products

2009 2010 2011 2012 2013 2014 2015 2016

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IP Status

28nm Production-Ready IP Platforms

65/55nm 40nm 32/28nm 20nm 14nm

28HPM

28HP

Production-ready

Production-ready

28LPP Production-ready

28SLP

28HPP Beta PDK IP Ready

Production-ready

L28HPM Upcoming

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Advanced Logic

Products

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SC12MC High Performance and SC9 High Density

Channel/Vt Combinations

Standard Cell Library • Up to 5 Vt’s • Up to 3 channel lengths Typical number of products 8 to 10

Power Management Kit • Up to 4 Vt’s • Up to 3 channel lengths Typical number of products 4 to 6

Retention Kit • Up to 3 Vt’s • Up to 2 channel lengths Typical number of products 2 to 3

High-Performance Kit (Part of POP)

• Up to 5 Vt’s • Up to 3 channel lengths Typical number of products 8 to 10

ECO Kit • 1 Vt/1 channel length

High number of cells for single Vt/C combinations

Higher number of cells across all Vt/C combinations

PVTs to suit commercial requirements and specific

applications

Typical 28/20nm Logic Product Platform

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Advanced Memory

Products

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ARM Advanced Memory Leadership

Best-in-class Performance, Power, Area

Solving Power Issues

Multi-Vt periphery in 28nm, standard at 20nm

Progressive power gating modes

Improving DVFS

Assist schemes for low Vdd_min

Extensive features set

Supporting wide rage of application

Simplifying SoC design

Unmatched quality, detailed validation reporting

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Memory Compilers Foundry Bit Cell

Periphery Option

High Density SP SRAM Compiler HD SP Standard Standard Vt

Low Leakage High Vt

High Speed SP SRAM Compiler HP SP Standard Standard Vt

High Performance Lower Vt and Standard Vt

Ultra-High Capacity SP SRAM HD SP Standard Standard Vt

Low Leakage High Vt

High Speed SP Register File Compiler HP SP Standard Standard Vt

High Performance Lower Vt and Standard Vt

High Speed 2P Register File Compiler 2P Standard Standard Vt

High Performance Lower Vt and Standard Vt

Ultra High Density 2P Register File Compiler

HP SP Standard Standard Vt

Low Leakage High Vt

High Speed DP SRAM Compiler DP Standard Standard Vt

High Performance Lower Vt and Standard Vt

High Density Via ROM Compiler n/a Standard Lower Vt and Standard Vt

Low Leakage Standard Vt + Long Channel

All compilers are implemented with multiple

periphery options for performance – power

optimization

Typical 28/20nm Memory Product Platform

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Implementation

Assist

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Implementation Assist

Rapidly achieve PPA targets on Cortex-A profile processors

In conjunction with the appropriate POP Technology from ARM

Based on internal implementation experience

Series of up to 8 technical conference calls to review:

Process & library options

EDA toolchain

Configuration

Constraints

Floorplan & Placement

Implementation

Overview report of Implementation Assist delivered 2 weeks

after the engagement

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Summary

The POP products allows Partners to take advantage of application

specific optimized IP

Delivers tuned Physical IP for Cortex-A class processors

Multichannel standard cell architecture to allow leakage recovery and single Vt implementation

Power Management Kit to enable ARM partners to partition the Processor and the rest of the SoC

design for leakage management

POPs can reduce a Partner’s time to silicon and provide confidence in

meeting specific power and performance targets

ARM 28nm Physical IP Platforms in production quality

Development of multiple 20nm SoC platforms already underway

Continues improvement of products and features ensure leading PPA and ease of SoC integration

Successful Silicon Validation

Extensive testchip program in 28 and 20nm