Power Distribution Network Design and Optimization based on Frequency Dependent Target Impedance

Youngwoo Kim, Kiyeong Kim, Jonghyun Cho and Joungho Kim

Department of Electrical Engineering Korea Advanced Institute of Science and Technology

Daejeon, South Korea youngwoo@kaist.ac.kr

Kibum Kang, Taisik Yang ,Yun Ra and Woohyun Paik

System IC Center LG Electronics

Seoul, South Korea yun.ra@lge.com

Abstract — In this paper, frequency dependent target impedance is proposed for optimal Power Distribution Network (PDN) design. Target impedance indicates how much and where decoupling capacitors should be located in the PDNs therefore it directly affects performance of the electrical systems or manufacturing cost. In this paper, frequency dependent target impedance considering IC’s power current spectrum is proposed. Based on the proposed target impedance, GPU’s VDD PDN is designed so that the hierarchical PDN impedance is maintained bellow the proposed target impedance in frequency domain. We simulated designed PDN with GPU chip’s signal model in the time domain to verify the proposed target impedance. Simultaneous Switching Noise (SSN) in the GPU chip PDN was suppressed bellow the target which is 5% of the supply voltage based on proposed design. Compared to the conventional target impedance, proposed target impedance allowed more flexible design and at the same time satisfied the design criterion.

Keywords—Power Distribution Network (PDN); Target Impedance; Design and Optimization; GPU

I. INTRODUCTION Optimal Power Distribution Network (PDN) design is

crucial since PDN is a path where power current flows from a voltage regulator to the ICs. A poor PDN with high PDN impedance can induce large supply voltage fluctuations which cause signal/power integrity and EMI radiation issues [1]. Also when many circuits operate at the same time, they derive power currents from PDN. When the frequencies of power current spectrum coincide with the frequencies where high PDN impedance peaks appear, Simultaneous Switching Noise (SSN) is generated and propagates through PDN which will deteriorate the system performance. In figure 1-(a), concept of SSN is depicted. To avoid these problems, many decoupling capacitors are hierarchically located which is conceptually described in figure 1-(b) based on the target impedance.

Proper target impedance is important since too loosely defined target impedance will lead to system malfunction and too tightly set target impedance which will lead to overuse of decoupling capacitors or splitting PDNs will increase the system cost and chances of fabrication failure. Therefore it is important to define proper target impedance.

(a)

(b)

Fig 1-(a) Simultaneous Switching Noise (SSN) which makes PDN noisy is shown. (b) Decoupling capacitors are hierarchically located in PDN to suppress SSN

Conventionally maximum value of power current is used to define the target impedance which is very flat-low in entire frequencies [2]. Therefore if this conventional target impedance is adopted during designing and optimizing PDN, excessive amount of decoupling capacitors are needed in on-chip, interposer, package and even if in system board level to

maintain PDN impedance under the target impedance. This lead to cost increase and sometimes it is even impossible to maintain PDN impedance under the target impedance. Therefore target impedance depending on the frequency considering power current spectrum is needed.

In this paper, frequency dependent target impedance is proposed. It is based on power current consumed at the chip PDN and power noise (SSN) transferred from adjacent switching ICs. Effectiveness of proposed target impedance is verified in frequency and time domain by designing and analyzed the interposer-based GPU module’s VDD PDN.

II. PROPOSAL OF PDN DESIGN PROCEDURES AND FREQUENCY DEPENDENTTARGET IMPEDANCE

A. PDN Design and Optimization Process PDN design and optimization process is shown with a flow

chart in figure 2. In previous works, there are many accurate ways to estimate the impedance properties of hierarchical PDN impedance [3-4] since simulating whole hierarchical PDN using 3D-EM solvers takes too much time and computational resources. When physical dimensions of the PDN to be designed are given, estimation of the impedance properties is possible. It is also possible to use extracted models such as Chip Power Model (CPM) or combination of CPM can also be used. By combining these models using circuit simulators or even using a segmentation method [3-4], impedance properties of the hierarchical PDN can be accurately estimated in short time.

After estimating the impedance properties, modeled PDN and voltage regulator module should be included in the circuit simulation to obtain power current spectrum to define the target impedance. Defined target impedance and the impedance estimated should be compared and if the PDN impedance violates the target impedance, proper decoupling capacitors should be located at the chips, interposer and package. Modified PDN must go through same procedures until the impedance of designed PDN does not violate the defined target impedance.

Fig 2. PDN design and optimization procedures are shown in flow chart format

B. Defining Target Impedance Based on the Power Current Spectrum Proper target impedance should consider the power current

spectrum of ICs. There are many ways to obtain the power current spectrum of ICs such as direct circuit simulation if the circuit is simple or design file is available. Circuit’s behavior model can also be used or sometimes, it could be measured. In this paper, we derive target impedance based on mobile GPU core’s chip signal model. Power current profiles of GPU core with different VDD pins are shown in figure 3-(a) which was simulated in ADS 2012. It can be seen in figure 3-(a) that since each VDD has different phase and value of power current profile, it is difficult to define total power current. It is possible to consider all these phase and magnitude difference if we have all VDD pin’s signal model, CPM and other PDN components such as interposer, package system board and VRM. However it takes too much time and computational resources. Therefore some assumptions are used to define the target impedance. This assumption is verified in section 3 by proving that PDN designed using the proposed target impedance successfully reduced the level of simultaneous switching noise (SSN) under the target of 5% of the power supply voltage.

To define the target impedance, allowable voltage ripple in chip PDN should be defined. For the GPU core, 0.9V is required to operate the core circuits. Usually 5% of voltage ripple is allowed [5].Total noise is summation of self-power noise (generated by the multiplication of the self-impedance and current spectrum) and transfer-noise (generated by the multiplication of the transfer-impedance and current spectrum). This is described in Eq. (1) Usually PDN transfer impedance is different among ports therefore in this case it is assumed that all the transfer impedances are identical and 10% of the self-impedance. By using this assumption, Eq. (2) becomes Eq. (3). Using these procedures, the target impedance of GPU core can be summarized and it is expressed in Eq. (4)

noise noise-self noise-transferV =V V+å (1)

noise noise-self noise-transfer noise-self noise-self1V =V V V V (total # of VDD pins)

10+ = + ×å

(2)

noise-selfV 2.81mV» (3)

target2.81Z = mΩI(ω)

(4)

In figure 3-(b), current spectrum of VDD 60 pin is shown. Based on this current spectrum and procedures shown above, equation (4) which is the proposed target impedance is plotted in figure 3-(c) in comparison with a conventional target impedance based on the maximum power current value. In the frequency range between 500MHz ~ 1GHz, proposed target impedance and the conventional target impedance is almost the

same since at this range, GPU’s clock frequency and its harmonic exist where maximum current peak is formed which can also be seen in figure 3-(b). However frequency ranges below and above this range, proposed target impedance is higher in value compare to conventional target impedance which enables more flexible PDN design.

(a)

(b)

(c)

Fig 3. GPU core’s current profile of different VDD pins are shown in (a). In (b), VDD-60 pin’s current spectrum is shown. Based on proposed assumption, target impedance is defined and compared with conventional target impedance in (c).

III. 2.5D GPU CORE PDN DESIGN BASED ON PROPOSED TARGET IMPEDANCE

In this section, we apply the proposed target impedance for designing an optimal 2.5D GPU VDD core PDN. GPU core PDN’s metal stack-up is based on the previous work [4] and the x-y dimensions of PDN is based on the real size of GPU core PDN. Interposer and package dimensions are based on the previous work [6]. Based on these previous dimensions and using a segmentation method, hierarchical PDN was modeled. In figure 4-(a), hierarchical PDN impedance is shown with parameters that dominate the impedance property. In figure 4-(b), hierarchical PDN impedance is compared with proposed target impedance. It can be seen that in many frequency ranges, hierarchical PDN impedance violate the target impedance. As a solution, 48.9nF of on-chip decoupling capacitors and 1000nF of on-interposer decoupling capacitors are placed to maintain the hierarchical PDN impedance below the target impedance.

By applying the decoupling capacitors, hierarchical PDN impedance was lowered below the proposed target impedance expect in some frequency ranges due to the resistance of on-chip PDN and ESR of the decoupling capacitors.

In figure 5, SSN in in GPU chip PDN is simulated based on PDN model and current model. . Period of SSN is about 2.2nsec, 454MHz in frequency which is similar to the clock frequency of the GPU core. Peak to peak voltage of SSN in the VDD PDN without decoupling capacitors is about 206mV which is 23 percent of the power supply voltage. SSN should be below 5% for the system to operate properly thus PDN should be optimized with decoupling capacitors. Therefore by designing PDN based on proposed target impedance successfully suppressed SSN and at the same time using less decoupling capacitors compared to the design based on the conventional target impedance.

I.V CONCLUSION Optimal PDN design in the electrical systems is important

since a poorly designed PDN cause many problems such as SSN, SI/PI and EMI issues. When these problems occur, performance of the electrical system is heavily deteriorated or even system failure can happen. Therefore PDN should be hierarchically designed with proper decoupling capacitor schemes and the target impedance plays important rule for determining the decoupling capacitor schemes. In this paper, frequency dependent target impedance based on GPU core’s current model was proposed. Hierarchical PDN impedance was compared with proposed target impedance and decoupling capacitors were placed to maintain hierarchical PDN impedance bellow the target impedance. To verify the effectiveness of the proposed target impedance, SSN was simulated at the chip PDN in the time domain. PDN design based on proposed frequency dependent target impedance suppressed SSN below the 5% of the supply voltage and at the same time enabled more flexible PDN design compared to the design based on the conventional target impedance.

(a)

(b)

(c)

Fig 4. PDN simulation set up is shown in (a) with GPU chip signal model. Hierarchical PDN impedance of 2.5D GPU core PDN is estimated and analyzed in figure (b) and it is compare with proposed target impedance in figure (c). Also in figure (c), optimized PDN impedance (with decoupling capacitors) is also shown

Fig 5. SSN in VDD PDN with and without decoupling capacitors is compared.

ACKNOWLEDGMENT This work was supported by International Collaborative R&D Program (funded by the Ministry of Trade, Industry and Energy (MKE, Korea) [N0000899, Glass interposer based RF FEM for Next Generation Mobile Smart Phone] also we would like to acknowledge the financial support from the R&D Convergence Program of MSIP (Ministry of Science, ICT and Future Planning) and ISTK (Korea Research Council for Industrial Science and Technology) of Republic of Korea (Grant B551179-12-04-00). We also like to acknowledge the technical support from ANSYS for providing 3D-EM simulator HFSS. Lastly we appreciate technical and financial support from LG electronics R&D project.

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