practical differential pair design€¦ · vl-155 practical differential pair design slide -20...

Slide -1VL-155 Practical Differential Pair Design

Bogatin Enterprises 2010 www.beTheSignal.com

Dr. Eric Bogatin,

Signal Integrity Evangelist,

Bogatin Enterprises

www.beTheSignal.com

April 2010Presented at the Huntsville EMC Symposium, April 2010

Practical Differential Pair Design



Copyright © 2010 by

Bogatin Enterprises, LLC

All rights reserved. No material contained in

this presentation may be distributed or

reproduced in whole or in part without the

written permission of Bogatin Enterprises.

Please respect the great deal of effort that

has gone into the preparation of these

lectures and use these materials for your

personal use only.

Bogatin Enterprises, LLC26235 W. 110th Terr.Olathe, KS 66061v: 913-393-1305f: 913-393-0929e: [email protected]



For More Information

www.BeTheSignal.com

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� Monthly Pop Quiz

� My Blog: What I learned this monthPublished by Prentice Hall, 2009



Outline

• Download a copy of the presentation from beTheSignal.com: under SI content, select “slides presentation”, PPT-VL-155

• Design Methodology

• Problems to avoid

• Decision factors for coupling

• Exploring Design Space



Pop Quiz

• Which is better:

� Tightly coupled diff pairs?

� Loosely coupled diff pairs?



What is the most common answer to

all SI questions?

“>it depends”

We answer it depends questions by

“putting in the numbers” with analysis:

� Rules of thumb

� Approximations

� Numerical simulation tools



Differential mode

Common mode

A Secret to Minimize Confusion

About Differential Impedance

Think:

Differential signals

Common signals

Odd mode

Even mode



Differential and Common Signals

V1

V2

• Definitions:

� Vdiff = V1 – V2

� Vcomm = ½ (V1 + V2)

2 4 6 8 10 12 14 16 180 20

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.0

2.0

time, nsec

V1, V

V2, V

Typical LVDS levels

2 4 6 8 10 12 14 16 180 20

0.0

0.5

1.0

-0.5

1.5

time, nsec

Vcom

mV

diff

common

differential



Every Pair of Signals Has a

Differential and Common Component

2 4 6 8 10 12 14 16 180 20

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.0

2.0

time, nsec

V1

, V

V2

, V

2 4 6 8 10 12 14 16 180 20

0.0

0.5

1.0

-0.5

1.5

time, nsec

Vco

mm

Vdiff

Added Skew = RT to one line

common

differential

• Differential and common signals

propagate independently and DO

NOT Interact on the board

• They each see a different

electrical environment:� Diff and comm impedance

� Diff and comm prop velocity

� Diff and comm attenuation

� Diff and comm cross talk

• But>.� Any line to line asymmetry will convert

diff into comm signal and vis versa

Definitions:

Vdiff = V1 – V2

Vcomm = ½ (V1 + V2)



A New Design Methodology to Eliminate SI Problems

Before the Design is Released

}Understand the essential

principles

-15 -10 -5 0 5 10 15-20 20

0.05

0.10

0.15

0.00

0.20

Center to Center Pitch, mils

NE

XT

, fr

actio

n

pitch

•An efficient methodology:

� Identify the SI problems

� Find the root cause

� Establish design guidelines to minimize them- balancing tradeoffs

� “correct by design”: use analysis tools to develop pre-layout design rules specific to your design

� Use post layout analysis tools to verify the final design



Practical Design Considerations

• Always do what is free

• Explore design space with simple estimates, then more accurate analysis

• Explore cost- performance trade offs with “virtual prototypes”

• The most difficult tradeoffs: higher component cost for lower system cost

• Consider product lifetime performance

• Manage risk: buy “insurance” by adding design margin

Cost factors:

Performance(meet specs)



Establish a Design Guideline by

Applying the “Youngman Principle”

Read www.bethesignal.com/blog, Nov 9, 2008

“If your arm hurts when you raise it, don't raise your arm.”

Identify the root cause of a problem and fix the root cause

“If problem A happens when your design has feature B, then eliminate feature B from your design”



Four Chief Problems to Manage in

High Speed Serial Links

• Losses

� Conductor loss

� Dielectric loss

• Ripple

� Impedance mismatches from: TX, channel, vias, connectors, RX

• Noise: cross talk

� Diff to diff and comm to diff coupling

• Mode conversion

� Line to line asymmetry

50 100 150 200 250 300 3500 400

0.0

0.2

0.4

0.6

-0.2

0.8

time, psec

Eye_uniform

.Density

0.8

What you think you have

Mantra: “losses, ripple, noise, mode conversion”

What you actually have



Design Solution Options to Achieve

Performance Goals

• Lowest attenuation

� Low dissipation factor laminate

� Lowest Dk laminate

� Wide lines

� Smooth copper

� Lower impedance

• Lowest ripple noise

� Controlled impedance to a target impedance

� Lower target impedance to match lower via impedance

• Lowest cross talk

� Avoid microstrip

� Large spacing between channels

� Tight coupling when return path is screwed up

• Lowest mode conversion

� Matched length, or length compensation

� Matched cross section lines

� Mitigate glass weave skew

• Lowest cost features

� FR4

� Highest interconnect density

1

2



A “Hidden Variable” to Real World

Performance

• Identical boards from different suppliers

• Very different insertion loss: 2x difference- why?

example courtesy of Cisco



Solutions are Available for

Smoother Copper

Courtesy of John Andresakis

(dual flat foil)

Push your fab vendors for:

1. rms roughness characterization data

2. Smoother copper foil

Cost will be driven by the market

If you do not ask for it, there will be no market need

The higher the volume the lower the cost



Tight or Loose Coupling?

• Performance drivers:

� Target impedance

� Widest line width

� Channel to channel cross talk

� Glass weave pitch

• Cost drivers:

� Fewest layers

� Lowest cost laminate

� Highest interconnect density

� Narrowest line that is free

� Tightest pitch that is high yield

Cost factors:

Performance(meet specs)



What is NOT influenced by Coupling

• The degree of coupling has NO impact on reflections or mismatch

• The differential signal only sees the differential impedance-

Symmetric,

uncoupled lines

make a perfectly

good differential

pair

uncoupled tightly coupled

HyperLynx 8.0



Microstrip:

Differential Impedance and Coupling

Increasing coupling decreases

differential impedance



Compensate Line Width for Separation to

Keep Differential Impedance Constant

This line defines design space for 100 Ohm differential impedance

h = 3.5 mils

h = 2.7 mils, Dk = 4



Attenuation and Line Width

• Consequence of wider line width, w:

� Lower Resistance

� If impedance is constant, lower attenuation

� Need thicker b to keep impedance constant

• What if dielectric thickness, b is fixed? What is impact of wider w?

wb

−=

0

LenLen

Z

Rx34.421SFor ALL transmission lines:

dB/inchRL in Ohms/inZ0 in Ohms



Attenuation and Line Width

Stripline, ½ oz copper

Fixed total thickness b = 12.2 mils

- Increasing line width, decreases R,

decreasing S21

- Increasing line width decreases Z0,

increasing S21.

Which has lower S21, narrow or wide w?

Lower Z0 than 50 Ohms is lower loss

wb

5 10 15 20 25 30 35 40 450 50

10

20

30

40

50

60

70

0

80

Line Width, w, mils

Ch

ara

cte

ristic Im

ped

an

ce

, O

hm

s

5 10 15 20 25 30 35 40 450 50

-0.15

-0.10

-0.05

-0.20

0.00

Line Width, w, mils

Insert

ion L

oss, d

B/inch

Optimum impedance for lowest

conductor loss ~ 35 Ohms

−=

0

LenLen

Z

Rx34.421S

@ 1 GHz

Conductor loss, rms = 0



How Else to Enable Wide Lines,

And Tight Pitch?

• Compromise: Loose coupling

� s = 2 x w, w = 5 mils

� Dk = 4

• Lower target impedance

� 85 Ohms is target in PCIeII

• Thicker H1 = H2 = 13 mils

� s = w = 5 mils

� Dk = 4

• Lower Dk = 3.1

� s = w = 5 mils

� H1 = H2 = 6.5 mils



Worse Case: Far End Cross Talk in

Microstrip: Single-ended to Diff

+ -aggressorvictim

spacingCoupling

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.0 2.0

-0.20

-0.15

-0.10

-0.05

0.00

-0.25

0.05

time, nsec

Diffe

rential N

ois

e, fr

action

100 Ohm diff

5 mil line, spacing

RT = 100 psec

Len = 10 inchesRT

Len~FEXT

Coupling cases:

Uncoupled: s = 3 x w

Loose: s = 2 x w

Tight s = w

~ 5 dB reduction in cross talk from tightest coupling

Differential cross talk from common sources can be -20 dB!

FEXT often limits max trace length in PCIe to < ~16 inches

(non-interleaved)

10 15 20 25 30 35 40 455 50

-40

-30

-20

-10

-50

0

Spacing, mils

FarE

nd N

ois

e,

fraction

Far

End N

ois

e in d

B



Worst Case Near End Cross Talk in

Stripline

+ -aggressorvictim

spacingCoupling

1 2 3 40 5

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

0

Spacing/line width

Near

End C

ross T

alk

, in

dB

For less than -50 dB xtk,

keep spacing > 3 x w

Three coupling cases:

Tight s = w

Loose: s = 2 x w

Uncoupled: s = 3 x w

Which is more important

influencing NEXT: coupling or

spacing?

~ 1 dB reduction in cross

talk from tightest

coupling

Reduce cross talk by

increasing spacing to

aggressor!



Coupling and Differential Cross Talk

• When the return path is a wide, uniform plane, tighter coupling has little impact on differential cross talk ( ie, in controlled impedance board traces)

• When the return path is not a uniform plane, tighter coupling can dramatically decrease differential cross talk

• Always use tight coupling between lines in a differential pair when the return path is not a wide uniform plane:

� Gaps

� Vias

� Connectors

� Leaded, 2 layer packages

� Sockets/interposers

� Flex/ribbon cable



Local Dk Variation Causes

“Weave Induced Skew”

Worst case if pitch = (1/2 + n) x glass pitch

Typical glass weave pitch ~ 15-25 mils

1080, 2116 are 17 mils pitch

Best case is if routing pitch matches glass weave

pitch: ~16-20 mils

Brist et al. PCD&F Nov 2004

8 mil wide line, 17 mil pitch



Time Delay Measurements of

Different Traces

straight

zig-zag

Courtesy of Altera

8 inch long Stripline in

2116 glass

8 psec in 8

inches ~ 1

psec/inch



Measured Skew in 4 inch Test Lines

Typical glass weave skew ~ 2.5

psec/inch

Worst case glass weave skew maybe

~15 psec/inch Courtesy of Jeff Loyer, Intel Corp.

+ -

Higher local Dk

Slower speed

Longer delay

Lower local Dk

higher speed

shorter delay

Glass Dk ~ 6

Resin Dk ~ 3

Photo courtesy of Jeff Loyer, Intel

40,000 TDR measurements

Typical case: 20 inches x 2.5 psec/inch = 50 psec skew. Possible problem for > 2 Gbps



Which is Better:


tight loose

Higher Interconnect Density

Lower Conductor Loss

Sweet spot s ~ 2w

If interconnect density is

most important, always

use tight coupling

If loss is important,

consider using

loose coupling



Which is Better,


It depends:

• Why loose coupling:

� Lower loss

� Risk reduction for glass weave skew mitigation

• Why tight coupling

� Higher interconnect density

� Lower cost

• What is not critical

� Differential impedance control

� Channel to channel cross talk

• What else:

� Lower Df

� Lower Dk

� Smoother copper



Practical Guidelines

• If bit rate is < ~ 1 Gbps

� Loss not an important driver

� Always consider tight coupling

• If bit rate is > ~ 5 Gbps

� Loss very important

� Consider looser coupling

� Route on a pitch equal to the glass weave pitch

• Regardless of bit rate, always do your own analysis



The End!

www.BeTheSignal.com

� Signal Integrity Certification Programs

� Continuing Education Curriculums

� Signal integrity public classes

� No Myths Allowed webinar series

� Streaming recorded lectures

� Hands on labs

� Feature articles and columns

� SI-Insights quarterly publication

� Monthly Pop Quiz

� My Blog: What I learned this monthPublished by Prentice Hall, 2009

practical differential pair design€¦ · vl-155 practical differential pair design slide -20...

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