project guide group members dr.b.gopi,b.e.m.e.ph.d p.menaka g.nivedha m.pavithra m.poornima g.priya...

25
SIMULATION STUDY ON REDUCTION OF DRAIN CURRENT IN MOSFET PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

Upload: eunice-nelson

Post on 04-Jan-2016

212 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

1

SIMULATION STUDY ON REDUCTION OF DRAIN CURRENT IN

MOSFET

PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA

Page 2: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

2

A numerical study on performance of MOSFET is analyzed. The drain current value of MOSFET can be reduced by varying substrate, gate and gate oxide materials. By reducing the drain current (Id), the power dissipation can be reduced. Thus the performance of the device can be increased by reducing the drain current (Id).

ABSTRACT

Page 3: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

3

Single gate MOSFETOutput characteristicsTransfer characteristicsOn state ResistancePower dissipation

WORK DONE

Page 4: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

4

SINGLE GATE STRUCTURE

Page 5: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

5

SUBSTRATE MATERIALS Silicon GermaniumGATE MATERIAL AluminiumGATE OXIDE MATERIALS Silicon di oxide Hafnium oxide Air

MATERIALS

Page 6: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

6

Id=knW/L((Vgs-VT)Vds-(Vds2/2))

kn=Coxµn

WhereId – drain current

kn - process parameter

W-width of gateL-length of gateVgs – gate source voltage

VT - threshold voltage

Vds - drain source voltage

Cox - gate oxide capacitance

µn - charge carrier effective mobility

DRAIN CURRENT EQUATION

Page 7: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

7

Output characteristics is a plot between drain voltage(VDS ) and drain current(ID) by keeping gate voltage(VGS) constant.

CUTOFF REGION: ID =0 LINEAR REGION: ID= µnC0xW/L ((VGS-VT)VDS-(VDS

2/2))

OUTPUT CHARACTERISTICS

Page 8: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

8

SATURATION REGION:ID=0.5 µnC0xW/L(VGS-VT)2

µn – mobility

C0X – capacitance of oxide layer

C0X – (ε0 εr)/t0x

ε0 –permittivity of free space

ε0 –8.854*10^-12

εr –relative permittivity

Page 9: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

9

OUTPUT CHARACTERISTICS OF MOSFET WITH Al AS GATE MATERIAL , SiO2 AS OXIDE LAYER AND Si AS SUBSTRATE

Vds(2V) ID(A) Vds (3V) ID(A) Vds (4V) ID(A) Vds (5V) ID(A) Vds (6V) ID(A)

0 5.01E-17 0 5.61E-17 0 6.21E-17 0 1.09E-16 0 8.17E-17

0.2 0.000273 0.2 0.000425 0.2 0.000544 0.2 0.000642 0.2 0.000725

0.4 0.000462 0.4 0.000778 0.4 0.001026 0.4 0.00123 0.4 0.001403

0.6 0.000554 0.6 0.001029 0.6 0.001414 0.6 0.001733 0.6 0.002004

0.8 0.000583 0.8 0.001172 0.8 0.001689 0.8 0.002129 0.8 0.002506

1.0 0.000595 1 0.001232 1 0.001853 1 0.002407 1 0.002893

1.2 0.000604 1.2 0.001255 1.2 0.00193 1.2 0.002575 1.2 0.003161

1.4 0.000612 1.4 0.001268 1.4 0.001963 1.4 0.00266 1.4 0.003324

1.6 0.000618 1.6 0.001279 1.6 0.00198 1.6 0.002698 1.6 0.00341

1.8 0.000624 1.8 0.001288 1.8 0.001993 1.8 0.002719 1.8 0.003451

2 0.00063 2 0.001296 2 0.002004 2 0.002733 2 0.003474

Page 10: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

10

Output Characteristics of MOSFET with Silicon as substrate and SiO2 ,HfO2, Air as oxide materials

Page 11: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

11

RON = 1/(μn COX W/L)(Vgs-Vds-VT)

μn-charge carrier effective mobility

COX -gate oxide capacitance

W –width of the gateL-length of the gateVgs – gate source voltage

VT - threshold voltage

Vds - drain source voltage

ON STATE RESISTANCE

Page 12: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

12

ON RESISTANCE OF MOSFET WITH Al AS GATE MATERIAL , SiO2

AS OXIDE LAYER AND Si AS SUBSTRATE

Id(A) RON2(Ω) Id(A) RON3(Ω) Id(A) RON4(Ω) Id(A) RON5(Ω) Id(A) RON6(Ω)

5.01E-17 0 5.61E-17 0 6.21E-17 0 1.09E-16 0 8.17E-17 00.000273 733.8

0.000425 470.63 0.000544 367.715 0.000642 311.554 0.000725 275.6860.000462 865.636

0.000778 514.099 0.001026 389.966 0.00123 325.317 0.001403 285.1680.000554 1082.27

0.001029 582.824 0.001414 424.28 0.001733 346.182 0.002004 299.3530.000583 1371.47

0.001172 682.501 0.001689 473.524 0.002129 375.728 0.002506 319.1840.000595 1679.4

0.001232 811.741 0.001853 539.671 0.002407 415.446 0.002893 345.6740.000604 1986.01

0.001255 956.32 0.00193 621.607 0.002575 466.016 0.003161 379.6120.000612 2288.94

0.001268 1103.77 0.001963 713.289 0.00266 526.361 0.003324 421.1170.000618 2587.96

0.001279 1250.96 0.00198 807.93 0.002698 593.056 0.00341 469.2050.000624 2883.39

0.001288 1397.34 0.001993 902.962 0.002719 662.115 0.003451 521.612.00063 3175.55

0.001296 1542.81 0.002004 997.82 0.002733 731.676 0.003474 575.788

Page 13: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

13

On state resistance of MOSFET with Silicon as substrate and SiO2,HfO2,Air

Page 14: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

14

PD= ID2RON

ID = drain current

RON = ON state resistance

POWER DISSIPATION

Page 15: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

15

POWER DISSIPATION OF MOSFET WITH Al AS GATE MATERIAL , SiO2 AS OXIDE LAYER AND Si AS SUBSTRATE

Id(A) Pd2(W) Id(A) Pd3(W) Id(A) Pd4(W) Id(A) Pd5(W) Id(A) Pd6(W)

5.01E-17 0 5.61E-17 0 6.21E-17 0 1.09E-16 0 8.17E-17 0

0.000273 5.45E-05 0.000425 8.50E-05 0.000544 0.000109 0.000642 0.000128 0.000725 0.000145

0.000462 0.000185 0.000778 0.000311 0.001026 0.00041 0.00123 0.000492 0.001403 0.000561

0.000554 0.000333 0.001029 0.000618 0.001414 0.000848 0.001733 0.00104 0.002004 0.001203

0.000583 0.000467 0.001172 0.000938 0.001689 0.001352 0.002129 0.001703 0.002506 0.002005

0.000595 0.000595 0.001232 0.001232 0.001853 0.001853 0.002407 0.002407 0.002893 0.002893

0.000604 0.000725 0.001255 0.001506 0.00193 0.002317 0.002575 0.00309 0.003161 0.003793

0.000612 0.000856 0.001268 0.001776 0.001963 0.002748 0.00266 0.003724 0.003324 0.004654

0.000618 0.000989 0.001279 0.002046 0.00198 0.003169 0.002698 0.004317 0.00341 0.005456

0.000624 0.001124 0.001288 0.002319 0.001993 0.003588 0.002719 0.004893 0.003451 0.006212

0.00063 0.00126 0.001296 0.002593 0.002004 0.004009 0.002733 0.005467 0.003474 0.006947

Page 16: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

16

Power Dissipation of MOSFET with Silicon as substrate and SiO2,HfO2,Air

Page 17: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

17

Output characteristics is a plot between gate voltage (VGS ) and drain current(ID) by keeping drain voltage(VDS) constant

TRANSFER CHARACTERISTICS

Page 18: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

18

TRANSFER CHARACTERISTICSOF MOSFET WITH Al AS GATE MATERIAL , SiO2 AS OXIDE LAYER AND Si AS SUBSTRATE

Gate voltage(V) Drain current (A)

0 1.44E-11

0.2 6.74E-11

0.4 5.83E-09

0.6 7.36E-07

0.8 2.09E-05

1 8.30E-05

1.2 0.000171

1.4 0.000274

1.6 0.000386

1.8 0.000506

2 0.00063

Page 19: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

19

Transfer Characteristics of MOSFET with Silicon as substrate and SiO2,HfO2 ,Air

Page 20: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

20

“HYBRID Ge-Si BASED MOSFET DEVICES” in the “International Journal of Electrical, Electronics and Computer System (IJEECS)”

“VARIATION OF GATE MATERIALS FOR HYBRID GE-SI MOSFET” in the “International Journal of Nanotechnology and Application journal”

PAPER PUBLISHED

Page 21: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

21

“HYBRID AlGaAs-SI BASED MOSFET DEVICES” in the “IOSR Journal of vlsi and signal processing”

“TRI-GATE STRUCTURE TO REDUCE DRAIN CURRENT” in “International Journal Of Electrical, Electronics and Telecommunication Engineering Recent Science Publications”

ACCEPTED FOR PUBLICATION

Page 22: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

22

“ANALYSING THE PERFORMANCE OF MOSFET BY VARYING THE SUBSTRATE MATERIALS” in “Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE)”

“COMPARATIVE STUDY ON THE PERFORMANCE OF MOSFET WITH GOLD AND SILVER AS GATE MATERIALS” in “IMPACT :International Journal of Research in Engineering & Technology”

ACCEPTED FOR PUBLICATION

Page 23: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

23

We have obtained output characteristics, transfer characteristics, ON resistance, power dissipation for MOSFET by changing the substrate and gate materials.

Thus the power dissipation of MOSFET is reduced with the help of reducing the drain current and the performance of the device is increased through this.

CONCLUSION

Page 24: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

24

H. Iwai, Extended Abstracts 2008 8th International Workshop on Junction Technology (IWJT '08) (Shanghai, China 2008 May 15-16, IEEE Press) p. 1. [DOI:10.1109/IWJT.2008.4540004].

International Technology Roadmap for Semiconductors (ITRS) 2007

Edition. Available from: http://www.itrs.net/links/2007ITRS/Home2007.html. B. Razavi, Design of Analog CMOSIntegrated Circuits (McGraw-

Hill, Boston,MA, 2001).

R. F. Pierret, Semiconductor Device Fundamentals (Addison-Wesley, Reading,MA, 1996) p. 691.

REFERENCE

Page 25: PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

25

J. Appenzeller et al., “Scheme for the fabrication of ultrashort channel MOSFETs,” Appl. Phys. Lett., vol. 77, pp. 298–300, July 2000

B. Yu et al., “15 nm gate length planar CMOS transistor,” in IEDM Tech.Dig., 2001, pp. 937–939.