Project Status

• Risks

• BOM

• Analysis

• Feasibility

• Designs

• Test Plans

Electronic System

FPGA Board Diagram

FPGA Board to Scale

Electronic System

OEM Board

1. Integrate supplied componentsA. 10MP Visual Band CameraB. 1.3MP IR CameraC. Spatial Sensors

i. NovAtel OEM Board OEMV3ii. NovAtel OEM Board OEMV2

D. Camera Processing Board2. Capture data from two cameras3. Capture 10MP @ 1fps4. Capture 1.3MP @ 30fps5. Capture INS data @ 30/sec

(simultaneously)

Processing elements

Customer Needs Met

6. External INS units7. Data processing (overlay)8. Real time viewing9. Store full-res. Data during flight10. Support NovAtel GNSS board

1. Integrate supplied componentsA. 10MP Visual Band CameraB. 1.3MP IR CameraC. Spatial Sensors

i. NovAtel OEM Board OEMV3ii. NovAtel OEM Board OEMV2

D. Camera Processing Board2. Capture data from two cameras3. Capture 10MP @ 1fps4. Capture 1.3MP @ 30fps5. Capture INS data @ 30/sec

(simultaneously)

Processing elements

Customer Needs Met

6. External INS units7. Data processing (overlay)8. Real time viewing9. Store full-res. Data during flight10. Support NovAtel GNSS board

1. Integrate supplied componentsA. 10MP Visual Band CameraB. 1.3MP IR CameraC. Spatial Sensors

i. NovAtel OEM Board OEMV3ii. NovAtel OEM Board OEMV2

D. Camera Processing Board2. Capture data from two cameras3. Capture 10MP @ 1fps4. Capture 1.3MP @ 30fps5. Capture INS data @ 30/sec

(simultaneously)

Processing elements

Customer Needs Met

6. External INS units7. Data processing (overlay)8. Real time viewing9. Store full-res. Data during flight10. Support NovAtel GNSS board

1. Integrate supplied componentsA. 10MP Visual Band CameraB. 1.3MP IR CameraC. Spatial SensorsD. Camera Processing Board

2. Capture data from two cameras3. Capture 10MP @ 1fps4. Capture 1.3MP @ 30fps5. Capture INS data @ 30/sec

(simultaneously)

Processing elements

Customer Needs Met

6. External INS units7. Data processing (overlay)8. Real time viewing9. Store full-res. Data during flight10. Support NovAtel GNSS board

FPGA• Inputs/Outputs• Flexible Architecture• Faster Speed• Parallel Processing

DSP• Energy Efficient• Single Pipeline• Easy Implementation• Math based ISA

Processing Elements

DSP

• Customer programmable– Encoding/Decoding media– Peripherals

• Role in this design– Image compression– Real time streaming of data– INS interface

• Required skills– Implementable Knowledge of C– DSP/BIOS

FPGA

• FPGA Selection– Quicker time to fabrication– Supreme configurability/Field reprogrammable– Has the I/O needed– Parallel processing

FPGA

• Xilinx Selection– Resources available to the team– Larger range of choices than other companies– Customer preference

• Model XC6SLX75T Selection– Package size (23mm x 23mm)– High speed transceiver count– I/O pin count– Cost effectiveness

Data Flow – Initial Design• Pictures

Camera FPGA OEM

• INS Data

INS OEM

Data Flow – Final Design• Pictures

Camera FPGA OEMCamera FPGA HD

• INS Data

INS OEM FPGA HD

Data Speeds

**Note: baud = bits per second (RS-232)

• Image– IR: 30 images / second

• VGA=640x480• 9.2 MHz

– Visible :1 image / second• 10.7MP=3664x2748 • 10.07 MHz

• INS– 30 captures / second

• 1kB=8kb• 8000 baud

FPGA Pin Speeds

• Minimum values

– 13ns -> 76 MHz

– 5ns -> 200 MHz

System Software Design

FPGA Image Controller

System Software Design

FPGA Central Dispatch

FPGA Process

Flowchart

Backup

FPGA Configurability

• Basis of configurability– Nature of transistor based FPGA

• Physical limitations– Through header on PCB using Xilinx provided

development tools

Backup

FPGA Configurability

• Customer configurable– Configuration languages• Knowledge of VHDL/Verilog

– Development packages• Xilinx provided development tools

– Physical configuration requirements• Connect programmer and download data file, restart

board

Backup

Processing Elements

DSP• CPU based• C Language

FPGA• Transistor based• VHDL/Verilog

Backup