rad-tolerant class v, wideband operational amplifier (rev. a
TRANSCRIPT
1FEATURES DESCRIPTION/ORDERING INFORMATION
APPLICATIONS
DIFFERENTIAL ADC DRIVE
From
50
Source
W
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007www.ti.com
RAD-TOLERANT CLASS V, WIDEBAND OPERATIONAL AMPLIFIER
• Wide Bandwidth: 1 GHz The THS4304 is a wideband, voltage-feedbackoperational amplifier designed for use in high-speed• Minimum Gain of 2 V/V (6 dB)analog signal processing chains operating with a• High Slew Rate: 800 V/μssingle 5 V power supply. Developed in the BiCom3
• Low Voltage Noise: 2.4 nV/√Hz silicon germanium process technology, the THS4304• Single Supply: 5 V, 3 V offers best-in-class performance using a single 5 V
supply as opposed to previous generations of• Quiescent Current: 18 mAoperational amplifiers requiring ±5 V supplies.
• Rad-Tolerant: 150 kRad (Si) TIDThe THS4304 is a traditional voltage-feedback• QML-V Qualified, SMD 5962-07219topology that provides the following benefits:balanced inputs, low offset voltage and offset current,low offset drift, high common mode and power supply
• Active Filter rejection ratio.• ADC Driver The THS4304 is offered in 10-pin ceramic flatpack• Ultrasound (U) and is specified over the full military temperature• Gamma Camera range, –55°C to 125°C.• RF/Telecom
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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5 6
7
8
9
10
VS–
DISSIPATION RATINGS
ABSOLUTE MAXIMUM RATINGS (1)
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
These devices have limited built in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
U PACKAGETOP VIEW
NC – No internal connection
ORDERING INFORMATION (1)
TRANSPORT MEDIA,PACKAGED DEVICES PACKAGE TYPE (2) PACKAGE MARKINGS QUANTITY5962-0721901VHA Ceramic Flatpack 0721901VHA Tubes, 25
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
POWER RATING (1)θJC θJAPACKAGE (°C/W) (°C/W) TA ≤ 25°C TA = 85°C TA = 125°CU (10) 14.7 189 661 mW 344 mW 132 mW
(1) Power rating determined for a maximum junction temperature of 150°C. However, distortion starts to substantially increase above125°C. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performanceand long-term reliability.
over operating free-air temperature range (unless otherwise noted)
UNITVS Supply voltage +6.0 VVI Input voltage ±VS
IO Output current 150 mAVID Differential input voltage ±2 V
Continuous power dissipation See Dissipation Rating TableTJ Maximum junction temperature, any condition (2) 150°CTstg Storage temperature range –65°C to 150°C
HBM 1600 VESD Ratings CDM 1000 V
MM 100 V
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings maycause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature mayresult in reduced reliability and/or lifetime of the device.
2 Copyright © 2007, Texas Instruments Incorporated
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad)
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNITDual supply ±1.35 ±2.5
Supply voltage, (VS+ and VS–) VSingle supply 2.7 5
Input common-mode voltage range VS– – 0.2 VS+ + 0.2 V
Specifications: VS = 5 V: RF = 249 Ω, RL = 100 Ω, and G = +3 unless otherwise noted
TYP OVER TEMPERATUREPARAMETER CONDITIONS –55°C to MIN/25°C 25°C UNITS125°C MAX
AC PERFORMANCEG = +2, VO = 100 mVpp 1 GHz Typ
Small-Signal Bandwidth G = +3, VO = 100 mVpp 800 MHz TypG = +5, VO = 100 mVpp 220 MHz Typ
Gain Bandwidth Product G > +5 1 GHz TypG= +3, VO = 100 mVpp,0.1 dB Flat Bandwidth 100 MHz TypCF = 0 pF
Large-Signal Bandwidth G = +3, VO = 2 VPP 290 MHz TypSlew Rate G = +3, VO = 2-V Step 800 V/μs TypSettling Time to 1% G = +3, VO = 2-V Step 11 ns TypRise/Fall Times G = +3, VO = 2-V Step 2.5 ns TypHarmonic Distortion
RL= 100 Ω –67 dBc TypSecond HarmonicG = +3,Distortion RL = 1 kΩ –85 dBc TypVO = 2 VPP,
RL = 100 Ω –100 dBc Typf = 10 MHzThird Harmonic DistortionRL = 1 kΩ –85 dBc Typ
Third-Order Intermodulation –80 dBc TypG = +3, VO= 2-VPP envelope,Distortion (IMD3)200 kHz tone spacing,
Third-Order Output Intercept f = 20 MHz 41 dBm Typ(OIP3)Noise Figure G = +2, f = 1 GHz 15 dB TypInput Voltage Noise f = 1 MHz 2.4 nV/√Hz TypInput Current Noise f = 1 MHz 2.1 pA/√Hz Typ
Copyright © 2007, Texas Instruments Incorporated 3
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ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad)
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
Specifications: VS = ±2.5 V, VCM = 0 V, RL = 500 Ω unless otherwise noted
TYP OVER TEMPERATUREPARAMETER CONDITIONS –55°C to MIN/25°C 25°C UNITS125°C MAX
DC PERFORMANCEOpen-Loop Voltage Gain VO = ±0.8 V 58 54 49 dB Min(AOL)Input Offset Voltage 0.5 4 6 mV Max
Input Offset Voltage Drift 5 μV/°C TypInput Bias Current 7 12 20 μA Max
VO = 0 VInput Bias Current Drift 50 nA/°C Typ
Input Offset Current 0.5 1 1.5 μA MaxInput Offset Current Drift 10 nA/°C Typ
INPUT CHARACTERISTICSCommon-Mode Input Range ±2.7 ±2.3 ±2 V MinCommon-Mode Rejection VO = 0 V, VCM = ±1 V 86 78 52 dB MinRatioInput Resistance 100 kΩ Typ
Each input, referenced to GNDInput Capacitance 1.5 pF TypOUTPUT CHARACTERISTICS
RL = 100 Ω ±1.4 ±1.3 ±1.15Output Voltage Swing V Min
RL = 1 kΩ ±1.5 ±1.4 ±1.25Output Current (Sourcing) RL = 10 Ω 98 80 70 mA MinOutput Current (Sinking) RL = 10 Ω 95 70 55 mA MinOutput Impedance f = 100 kHz 0.016 Ω TypPOWER SUPPLYMaximum Operating Voltage ±2.5 ±2.75 ±2.75 Max
VMinimum Operating Voltage ±2.5 ±1.35 ±1.35 MinMaximum Quiescent Current IO = 0 mA 18 18.9 19.7 mA MaxMinimum Quiescent Current IO = 0 mA 18 17.5 16.0 mA MinPower Supply Rejection VS+ = 3 V to 2 V, VS– = –2.5 V 78 72 64 dB Min(+PSRR)Power Supply Rejection VS+ = 2.5 V, VS– = –2 V to –3 V 60 57 53 dB Min(–PSRR)
4 Copyright © 2007, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad)
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
Specifications: VS = 3 V: RF = 249 Ω, RL = 500 Ω, and G = +3 unless otherwise noted
TYP OVER TEMPERATUREPARAMETER CONDITIONS MIN/25°C 25°C –55°C to 125°C UNITS MAX
AC PERFORMANCEG = +2, VO = 100 mVpp 1 GHz Typ
Small-Signal BandwidthG = +5, VO = 100 mVpp 230 MHz Typ
Gain Bandwidth Product G > +5 1 GHz TypSlew Rate G = +3, VO = 1-V Step 675 V/μs TypRise/Fall Times G = +3, VO = 0.5-V Step 1.5 ns TypHARMONIC DISTORTION
Second Harmonic Distortion G = +3, –82 dBc TypVO = 0.5 VPP, RL = 499 Ω –82 dBcThird Harmonic Distortion Typf = 10 MHz
Noise Figure G = +2, f = 1 GHz 15 dB TypInput Voltage Noise f = 1 MHz 2.4 nV/√Hz TypInput Current Noise f = 1 MHz 2.1 pA/√Hz Typ
Copyright © 2007, Texas Instruments Incorporated 5
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ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad)
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
Specifications: VS = ±1.5 V, VCM = 0 V, RL = 500 Ω unless otherwise noted
TYP OVER TEMPERATUREPARAMETER CONDITIONS MIN/25°C 25°C –55°C to 125°C UNITS MAX
DC PERFORMANCEOpen-Loop Voltage Gain (AOL) VO = ±0.3 V 57 52 50 dB MinInput Offset Voltage 1 4 6 mV Max
Input Offset Voltage Drift 5 μV/°C TypInput Bias Current 6 12 20 μA Max
VO = 0 VInput Bias Current Drift 50 nA/°C Typ
Input Offset Current 0.4 1 1.5 μA MaxInput Offset Current Drift 10 nA/°C Typ
INPUT CHARACTERISTICSCommon-Mode Input Range ±1.7 ±1.3 ±1 V MinCommon-Mode Rejection VO = 0 V, VCM = ±0.3 V 68 62 50 dB MinRatioInput Resistance 100 kΩ Typ
Each input, referenced to GNDInput Capacitance 1.5 pF TypOUTPUT CHARACTERISTIC
RL = 100 Ω ±0.4 ±0.3 ±0.2Output Voltage Swing V Min
RL = 1 kΩ ±0.5 ±0.4 ±0.3Output Current (Sourcing) RL = 10 Ω 30 25 20 mA MinOutput Current (Sinking) RL = 10 Ω 32 27 21 mA MinOutput Impedance f = 100 kHz 0.016 Ω TypPOWER SUPPLYMaximum Operating Voltage ±1.5 ±2.75 ±2.75 Max
VMinimum Operating Voltage ±1.5 ±1.35 ±1.35 MinMaximum Quiescent Current IO = 0 mA 17.2 17.9 18.6 mA MaxMinimum Quiescent Current IO = 0 mA 17.2 16.5 15.0 mA MinPower Supply Rejection VS+ = 1.8 V to 1.2 V, VS– = –1.5 V 80 60 53 dB Min(+PSRR)Power Supply Rejection VS+ = 1.5 V, VS– = –1.2 V to –1.8 V 60 55 52 dB Min(–PSRR)
6 Copyright © 2007, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
Table of GraphsFIGURE
5 VFrequency Response 1 through 3, 5, 60.1 dB Flatness 4S-Parameters vs Frequency 72nd Harmonic Distortion vs Frequency 8, 103rd Harmonic Distortion vs Frequency 9, 11Harmonic Distortion vs Output voltage 12
IMD3 3rd Order Intermodulation Distortion vs Frequency 13OIP3 3rd Order Output Intercept Point vs Frequency 14SR Slew Rate vs Output voltage 15Vn/In Noise vs Frequency 16
Noise Figure vs Frequency 17Iq Quiescent Current vs Supply voltage 18
Rejection Ratio vs Frequency 19VO Output Voltage vs Load resistance 20VOS Input Offset Voltage vs Input common-mode voltage 21IIB/IIO Input Bias and Offset Current vs Case temperature 22VOS Input Offset Voltage vs Case temperature 23VO Small-signal Transient Response 24VO Large-signal Transient Response 25VO Settling Time 26VO Overdrive Recovery Time 273 V
Frequency Response 28 through 30Harmonic Distortion vs Frequency 31Harmonic Distortion vs Output voltage 32
SR Slew Rate vs Output voltage 33VO Output Voltage vs Load resistance 34IIB/IIO Input Bias and Offset Current vs Case temperature 35VOS Input Offset Voltage vs Case temperature 36
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TYPICAL CHARACTERISTICS (5 V)
1 M 10 M 100 M 1 G 10 G
Sig
na
l G
ain
dB
–
f Frequency Hz– –
G = 3
G = 5
G = 2
V = 100 mV ,
R = 249 ,
R = 100 ,
V = 5 V
O pp
F
L
S
W
W
1 M 10 M 100 M 1 G 10 G
Sig
nal G
ain
dB
–
f Frequency Hz– –
C = 0.5 pFF
C = 0 pFF
C = 1 pFF
Gain = 2,V = 100 mV ,
R = 249 ,
R = 100 ,
V = 5 V
O pp
F
L
S
W
W
1 M 10 M 100 M 1 G 10 G
Sig
na
l G
ain
dB
–
V = 100 mVO P-P
f Frequency Hz– –
V = 1 VO P-P
V = 2 VO P-P
Gain = 2,
R = 249 ,
R = 100 ,
V = 5 V
F
L
S
W
W
1 M 10 M 100 M 1 G 10 G
Sig
na
l G
ain
dB
–
f Frequency Hz– –
G = 5
G = 3
G = 2
V = 1 V ,
R = 249 ,
R = 100 ,
V = 5 V
O pp
F
L
S
W
W
1 M 10 M 100 M 1 G
Sig
na
l G
ain
dB
–
f Frequency Hz– –
Gain = 3,V = 100 mV ,
R = 249 ,
R = 100 ,
V = 5 V
O pp
F
L
S
W
W
1 M 10 M 100 M 1 G 10 G
Sig
na
l G
ain
dB
–
f Frequency Hz– –
G = 5
G = 3
G = 2V = 2 V ,
R = 249 ,
R = 100 ,
V = 5 V
O pp
F
L
S
W
W
2n
d-H
arm
on
ic D
isto
rtio
nd
Bc
–
f Frequency MHz– –
R = 100L
R = 1 KL
Gain = 3,V = 2 V ,
R = 249 ,
V = 5 V
O pp
F
S
W
3rd
-Ha
rmo
nic
Dis
tort
ion
dB
c–
f Frequency MHz– –
R = 100L
R = 1 KL
Gain = 3,V = 2 V ,
R = 249 ,
V = 5 V
O pp
F
S
W
1 M 10 M 100 M 1 G 10 G
Sig
na
l G
ain
dB
–
f Frequency Hz– –
S21S22
S11S12
Gain = 3,V = 100 mV ,
R = 249 ,
R = 100 ,
V = 5 V
O pp
F
L
S
W
W
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 1. Figure 2. Figure 3.
0.1 dB FLATNESS FREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 4. Figure 5. Figure 6.
S-PARAMETERS 2nd-HARMONIC DISTORTION 3rd-HARMONIC DISTORTIONvs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 7. Figure 8. Figure 9.
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f Frequency MHz– –
R = 100L
R = 1 KL
2n
d-H
arm
on
ic D
isto
rtio
nd
Bc
–
Gain = 3,V = 1 V ,
R = 249 ,
V = 5 V
O pp
F
S
W
3rd
-Ha
rmo
nic
Dis
tort
ion
dB
c–
f Frequency MHz– –
Gain = 3,V = 1 V ,
R = 249 ,
V = 5 V
O pp
F
S
W
R = 100L
R = 1 KL
Ha
rmo
nic
Dis
tort
ion
dB
c–
HD2
Output Voltage V– pp
HD3
Gain = 3,
R = 249 ,
R = 100 ,
V = 5 V
f = 10 MHz
F
L
S
W
W
V = 1 V
envelopeO PP
IMD
dB
c3
–
f Frequency M z– – H
V = 2 V
envelopeO PP
Gain = 3,
R = 249 ,
R = 100 ,
200 kHz spacing,V = 5 V
F
L
S
Ω
Ω
400
450
500
550
600
650
700
750
800
850
900
0 0.5 1 1.5 2 2.5 3
Gain = 2,RF = 249 Ω,RL = 100 Ω,VS = 5 V
SR
− S
lew
Rat
e −
V/
VO − Output V oltage −V PP
sµ
Rise
Fall
OIP
dB
c3
–
f Frequency MHz– –
V = 1 V
envelopeO PP
V = 2 V
envelopeO PP
V = 5 VS
Gain = 3,
R = 249 ,
R = 100 ,
200 kHz spacing
F
L
W
W
1
10
100
1000
10 100 1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
nV/
Hz
− Vo
ltage
Noi
se −
Vn
I n−
Cur
rent
Noi
se −
pA/
Hz
Vn
In
0
2
4
6
8
10
12
14
16
18
20
10 M 500 M 1 G
Noi
se F
igur
e −
dB
f − Frequency − Hz
Gain = 2,RF = 249 Ω,RG = 249 Ω,RL = 100 Ω,VS = 5 V
0
2
4
6
8
10
12
14
16
18
20
22
2 2.5 3 3.5 4 4.5 5
I−
Qui
esce
nt C
urre
nt −
mA
VS − Supply V oltage − V
TA = 85°C
TA = -40°C
TA = 25°C
q
TA = -55°C
TA = 125°C
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (5 V) (continued)
2nd-HARMONIC DISTORTION 3rd-HARMONIC DISTORTION HARMONIC DISTORTIONvs vs vs
FREQUENCY FREQUENCY OUTPUT VOLTAGE
Figure 10. Figure 11. Figure 12.
3rd-ORDER INTERMODULATION 3rd-ORDER OUTPUT INTERCEPTDISTORTION POINT SLEW RATE
vs vs vsFREQUENCY FREQUENCY OUTPUT VOLTAGE
Figure 13. Figure 14. Figure 15.
NOISE NOISE FIGURE QUIESCENT CURRENTvs vs vs
FREQUENCY FREQUENCY SUPPLY VOLTAGE
Figure 16. Figure 17. Figure 18.
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1
1.5
2
2.5
3
3.5
4
10 100 1000
VS = 5 V
RL − Load Resistance − Ω
− O
utpu
t Vol
tage
− V
V O
0
10
20
30
40
50
60
70
80
90
100
110
10 k 100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Rej
ectio
n R
atio
− d
B
CMRR
PSRR+
PSRR−
VS = 5 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
−1 0 1 2 3 4 5 6
− In
put O
ffset
Vol
tage
− m
VV
OS
VICR − Input Common-Mode Range − V
VS = 5 V
Input B
ias C
urr
ent
µA
–
Case Temperature °C–
Input O
ffset C
urr
ent
nA
–
IIO
IIB–
IIB
V = 5 VS
Ou
tpu
t V
olta
ge
V–
Time ns–
Inp
ut
Vo
lta
ge
V–
Input
Output
Gain = 3,
R = 249 ,
R = 100 ,
V = 5 V
F
L
S
W
W
Inp
ut O
ffset V
olta
ge
µV
–
Case Temperature °C–
V = 5 VS
Outp
ut V
oltage
V–
Time ns–
Input
Output
Input V
oltage
V–
Gain = 3,
R = 249 ,
R = 100 ,
V = 5 V
F
L
S
W
W
Ou
tpu
t V
olta
ge
%o
f F
ina
l V
alu
e–
Time ns–
Gain = 3,
R = 249 ,
R = 100 ,
V = 2 V
V = 5 V
F
L
S
W
W
O PP
Ou
tpu
t V
olta
ge
V–
Time µs–
Input
Output
Inp
ut
Vo
lta
ge
V–
Gain = 3,
R = 249 ,
R = 100 ,
V = 5 V
F
L
S
W
W
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (5 V) (continued)
REJECTION RATIO OUTPUT VOLTAGE INPUT OFFSET VOLTAGEvs vs vs
FREQUENCY LOAD RESISTANCE INPUT COMMON-MODE VOLTAGE
Figure 19. Figure 20. Figure 21.
INPUT BIAS AND OFFSETCURRENT INPUT OFFSET VOLTAGE
vs vs SMALL-SIGNALCASE TEMPERATURE CASE TEMPERATURE TRANSIENT RESPONSE
Figure 22. Figure 23. Figure 24.
LARGE-SIGNAL OVERDRIVETRANSIENT RESPONSE SETTLING TIME RECOVERY TIME
Figure 25. Figure 26. Figure 27.
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TYPICAL CHARACTERISTICS (3 V)
Sig
na
l G
ain
dB
–
f Frequency Hz– –
1 M 10 M 100 M 1 G 10 G0
5
10
15
C = 0 pFF
C = 0.5 pFF
C = 1 pFF
Gain = 2,V = 100 mV ,
R = 249 ,
R = 499 ,
V = 3 V
O pp
F
L
S
W
W
1 M 10 M 100 M 1 G 10 G
Sig
na
l G
ain
dB
–
f Frequency Hz– –
V = 100 mV ,
R = 249 ,
R = 499 ,
V = 3 V
O pp
F
L
S
W
W
0
5
10
15
G = 5
G = 2
1 M 10 M 100 M 1 G 10 G
Sig
na
l G
ain
dB
–
f Frequency Hz– –
V = 100 mVO
V = 200 mVO
V = 500 mVO
Gain = 2,
R = 249 ,
R = 499 ,
V = 3 V
F
L
S
W
W
Ha
rmo
nic
Dis
tort
ion
dB
c–
f Frequency MHz– –
1 10 100
-110
-100
-90
-80
-70
-60
-50
-40
Gain = 3,
R = 249 ,
R = 499 ,
V = 3 V
F
L
S
W
W
V = 500 mV ,O pp
HD2
HD3
400
450
500
550
600
650
700
750
800
850
900
0 0.1 0.2 0.3 0.4 0.5 0.6
Rise
Fall
Gain = 2,RF = 249 Ω,RL = 499 Ω,VS = 3 V
SR
− S
lew
Rat
e −
V/µ
s
VO − Output V oltage − V PP
Ha
rmo
nic
Dis
tort
ion
dB
c–
Output Voltage Vpp–
Gain = 3,
R = 249 ,
R = 499 ,
V = 3 V
F
L
S
W
W
f = 10 MHz,
HD3
HD2
T Case Temperature °C –– C
Inp
ut B
ias C
urr
en
tµ
A–
Inp
ut O
ffset C
urr
en
tn
A–
IIB+
IIB-
IIO
Vs = 3 V
0.5
0.75
1
1.25
1.5
1.75
2
2.25
10 100 1000
− O
utpu
t Vol
tage
− V
VO
RL − Load Resistance −
VS = 3 V
Inp
ut
Offse
t V
olta
ge
mV
–
T Case Temperature °C – – C
Vs = 3 V
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 28. Figure 29. Figure 30.
HARMONIC DISTORTION HARMONIC DISTORTION SLEW RATEvs vs vs
FREQUENCY OUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 31. Figure 32. Figure 33.
INPUT BIAS ANDOUTPUT VOLTAGE OFFSET CURRENT INPUT OFFSET VOLTAGE
vs vs vsLOAD RESISTANCE CASE TEMPERATURE CASE TEMPERATURE
Figure 34. Figure 35. Figure 36.
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APPLICATION INFORMATION
For many years, high-performance analog design has required the generation of split power supply voltages, like
SNR SignalNoise
SFDR SignalSpur
GENERAL APPLICATION
HARMONIC DISTORTION
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
±15 V, ±8 V, and more recently ±5 V, to realize the full performance of the amplifiers available. Modern trends inhigh-performance analog are moving toward single-supply operation at 5 V, 3 V, and lower. This reducespower-supply cost due to less voltage being generated and conserves energy in low-power applications. It alsocan take a toll on available dynamic range, a valuable commodity in analog design, if the available voltage swingof the signal also must be reduced.
Two key figures of merit for dynamic range are signal-to-noise ratio (SNR) and spurious free dynamic range(SFDR).
SNR is simply the signal level divided by the noise:
and SFDR is the signal level divided by the highest spur:
In an operational amplifier, reduced supply voltage typically results in reduced signal levels due to lower voltageavailable to operate the transistors within the amplifier. When noise and distortion remain constant, the result is acommensurate reduction in SNR and SFDR. To regain dynamic range, the process and the architecture used tomake the operational amplifier must have superior noise and distortion performance with lower power supplyoverhead required for proper transistor operation.
The THS4304 BiCom3 operational amplifier is just such a device. It is able to provide 2 Vpp signal swing at itsoutput on a single 5 V supply with noise and distortion performance similar to the best 10 V operational amplifierson the market today
The THS4304 is a traditional voltage-feedback topology with wideband performance up to 1 GHz at a gain of2 V/V. Care must be taken to ensure that parasitic elements do not erode the phase margin.
Capacitance at the output and inverting input, and resistance and inductance in the feedback path, can causeproblems.
To reduce parasitic capacitance, the ground plane should be removed from under the part. To reduce inductancein the feedback, the circuit traces should be kept as short and direct as possible.
For a gain of +2V/V, it is recommended to use a 249 Ω feedback resistor. With good layout, this should keep thefrequency response peaking to around 6 dB. This resistance is high enough to not load the output excessively,and the part is capable of driving 100 Ω load with good performance. Higher-value resistors can be used, withmore peaking. Lower-value feedback resistors also can be used to reduce peaking, but degrade the distortionperformance with heavy loads.
Power supply bypass capacitors are required for proper operation. The most critical are 0.1 μF ceramiccapacitors; these should be placed as close to the part as possible. Larger bulk capacitors can be shared withother components in the same area as the operational amplifier.
For best second harmonic (HD2), it is important to use a single-point ground between the power supply bypasscapacitors when using a split supply. It also is recommended to use a single ground or reference point for inputtermination and gain-setting resistors (R8 and R11 in the non-inverting circuit). It is recommended to follow theEVM layout closely in your application.
12 Copyright © 2007, Texas Instruments Incorporated
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EVALUATION MODULES
1
2
43
5
VREF
R3 R6+VS
C8 R8 C3
R7
+VS
U1
R9
C7J1 R10
R11 R1
VREF
−VS
THS4304 R2 C9 J2
C5 C1
−VSFB1 FB2
J3 J4 J6 J5
−VS +VSGND GND
+VS
TP1GND
C2 C4
R12*
C6*−VS +VS
*C6 − DGK EVM Only
*R12 − DBV EVM Only
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
The THS4304 has two evaluation modules (EVMs) available. One is for the MSOP (DGK) package and the otherfor the SOT-23 (DBV) package. These provide a convenient platform for evaluating the performance of the partand building various different circuits. The full schematics, board layout, and bill of materials (as supplied) for theboards are shown in the following illustrations.
Figure 37. EVM Full Schematic
Copyright © 2007, Texas Instruments Incorporated 13
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THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
EVM BILL OF MATERIALSTHS4304 EVM (1)
SMD Reference PCB Manufacturer's Distributor'sItem Description Size Designator Quantity Part Number Part Number1 FB1, FB2 2 (STEWARD) (DIGI-KEY)Bead, ferrite, 3 A, 80 Ω 1206 HI1206N800R-00 240-1010-1-ND2 Capacitor, 3.3 μF, Ceramic 1206 C1, C2 2 (AVX) 1206YG335ZAT2A (GARRETT)
1206YG335ZAT2A3 Capacitor, 0.1 μF, Ceramic 0603 C4, C5 2 (AVX) 0603YC104KAT2A (GARRETT)
0603YC104KAT2A4 Open 0603 C3, C6 (2) 25 Open 0603 R1, R3, R6, 5
R9, R12 (3)
6 Resistor, 0 Ω, 1/10 W, 1% 0603 C7. C8, C9, 4 (KOA) RK73Z1JTTD (GARRETT)C10 RK73Z1JTTD
7 Resistor, 49.9 Ω, 1/10 W, 1% 0603 R2, R11 2 (KOA) RK73H1JLTD49R9F (GARRETT)RK73H1JLTD49R9F
8 Resistor, 249 Ω, 1/10 W, 1% 0603 R7, R8 2 (KOA) RK73H1JLTD2490F (GARRETT)RK73H1JLTD2490F
9 Jack, banana recepticle, 0.25 in. J3, J4, J5, J6 4 (HH SMITH) 101 (NEWARK) 35F865diameter hole
10 Test point, black TP1 1 (KEYSTONE) 5001 (DIGI-KEY) 5001K-ND11 Connector, edge, SMA PCB jack J1, J2 2 (JOHNSON) 142-0701-801 (NEWARK) 90F262412 Integrated Circuit, THS4304 U1 1 (TI) THS4304DGK, or
(TI) THS4304DBV13 Standoff, 4-40 HEX, 0.625 in. 4 (KEYSTONE) 1808 NEWARK) 89F1934
Length14 Screw, Phillips, 4-40, 0.250 in. 4 SHR-0440-016-SN15 Board, printed-circuit 1 (TI) THS4304DGK ENG A, or
(TI) THS4304DBV ENG A
(1) NOTE: All items are designated for both the DBV and DGK EVMs unless otherwise noted.(2) C6 used on DGK EVM only.(3) R12 used on DBV EVM only.
14 Copyright © 2007, Texas Instruments Incorporated
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THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
Figure 38. THS4304DGK EVM Layout Top and L2 Figure 39. THS4304DGK EVM Layout Bottom and L3
Figure 40. THS4304DBV EVM Layout Top and L2 Figure 41. THS4304DBV EVM Layout Bottom and L3
Copyright © 2007, Texas Instruments Incorporated 15
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NON-INVERTING GAIN WITH SPLIT SUPPLY
1
2
4
3
5
C8
0
R8
249 249
R7
+VS
U1
−VS +VSFB1 FB2
−VS +VSGND GND
J3 J4 J6 J5
C50.1 F
C13.3 F
GND
TP1
C23.3 F
C40.1 F
J1 C7 R10
0 0R1149.9 −VS
THS4304DBV
R2
49.9
C9
0
J2
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
The following schematic shows how to configure the operational amplifier for non-inverting gain with split powersupply (±2.5V). This is how the EVM is supplied from TI. This configuration is convenient for test purposesbecause most signal generators and analyzer are designed to use ground-referenced signals by default. Notethe input and output provides 50 Ω termination.
Figure 42. Non-Inverting Gain With Split Power Supply
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INVERTING GAIN WITH SPLIT POWER SUPPLY
1
2
43
5
−VS +VSFB1 FB2
−VS +VSGND GND
J3 J4 J6 J5
C50.1 F
C13.3 F
GND
TP1
C23.3 F
C40.1 F
+VS
J1 C7 R9
0R1161.9
−VS
THS4304DBV
C9
0
J2
221
R1124
C80
U1R2
49.9
R7
249
51
2
43 +
−
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
The following schematic shows how to configure the operational amplifier for inverting gain of 1 (–1 V/V) withsplit power supply (±2.5 V). Note the input and output provides 50 Ω termination for convenient interface tocommon test equipment.
Figure 43. Inverting Gain With Split Power Supply
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NON-INVERTING SINGLE-SUPPLY OPERATION
1
2
43
5
+VSFB2
−VS +VSGND GND
J3 J4 J6 J5
GND
TP1
C23.3 F
C40.1 F
NC
C8 R8
249 249
R7
+VS
U1
J1 C7 R10
0 0R149.9
THS4304DBV
R2
49.9
C9
0
J2
VREF
R3
10 k 10 k
R6+VS
0.1 F
C5
VREF
3
41
5
2+
−
DIFFERENTIAL ADC DRIVE AMPLIFIER
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
The THS4304 EVM can easily be configured for single 5 V supply operation, as shown in the followingschematic, with no change in performance. This circuit passes dc signals at the input, so care must be taken toreference (or bias) the input signal to mid-supply.
If dc operation is not required, the amplifier can be ac coupled by inserting a capacitor in series with the input(C7) and output (C9).
Figure 44. Non-Inverting 5-V Single-Supply Amplifier
The circuit shown in Figure 44 is adapted as shown in Figure 45 to provide a high-performance differentialamplifier drive circuit for use with high-performance ADCs, like the ADS5500 (14 bit 125 MSP ADC). For testingpurposes, the circuit uses a transformer to convert the signal from a single-ended source to differential. If theinput signal source in your application is differential and biased to mid-rail, no transformer is required.
The circuit employs two amplifiers to provide a differential signal path to the ADS5500. A resistor divider (two10 kΩ resistors) is used to obtain a mid-supply reference voltage of 2.5 V (VREF) (the same as shown in thesingle-supply circuit of Figure 44). Applying this voltage to the one side of RG and to the positive input of theoperational amplifier (via the center-tap of the transformer) sets the input and output common-mode voltage ofthe operational amplifiers to mid-rail to optimize their performance. The ADS5500 requires an inputcommon-mode voltage of 1.5 V. Due to the mismatch in required common-mode voltage, the signal is ac coupledfrom the amplifier output, via the two 1 nF capacitors, to the input of the ADC. The CM voltage of the ADS5500 isused to bias the ADC input to the required voltage, via the 1 kΩ resistors. Note: 100 μA common-mode current isdrawn by the ADS5500 input stage (at 125 MSPS). This causes a 100 mV shift in the input common-modevoltage, which does not impact the performance when driving the input to –1 dB of full scale. To offset this effect,a voltage divider from the power supply can be used to derive the input common-mode voltage reference.
Because the operational amplifiers are configured as non-inverting, the inputs are high impedance. This isparticularly useful when interfacing to a high-impedance source. In this situation, the amplifiers provideimpedance matching and amplification of the signal.
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+5V
A IN+
A IN−
ADS 5500
RFRG
49 .9
VIN
From50
Source
1001:1
RFRG
CM
CM
0.1
THS4304
THS4304
1k
+3.3 VA +3.3 VD
D
A
0.1
+5V
10 k
VREF (= 2.5V)
VREF
VREF
VREF
1nF
1nF
+5VCM
10 k
100
1k
F
F
THS4304-SP
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
Figure 45. Differential ADC Drive Amplifier Circuit
Copyright © 2007, Texas Instruments Incorporated 19
Product Folder Link(s): THS4304-SP
PACKAGING INFORMATION
Orderable Device Status (1) PackageType
PackageDrawing
Pins PackageQty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-0721901VHA ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4304-SP :
• Catalog: THS4304
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
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