reliability and performance scaling of very high speed sige hbts

Microelectronics Reliability 44 (2004) 397–410

www.elsevier.com/locate/microrel

Introductory Invited Paper

Reliability and performance scaling ofvery high speed SiGe HBTs

Greg Freeman *, Jae-Sung Rieh, Zhijian Yang, Fernando Guarin

IBM Microelectronics Semiconductor Research and Development Center, 2070 Rt. 52,

Hopewell Junction, New York, NY 12533, USA

Received 5 November 2003

Abstract

We discuss the SiGe HBT structural changes required for very high performance. The increase in collector con-

centration, affecting current density and avalanche current, appears to be the most fundamental concern for reliability.

In device design, a narrow emitter and reduced poly–single-crystal interfacial oxide are important elements in mini-

mizing device parameter shifts. From the application point of view, avalanche hot-carriers appear to present new

constraints, which may be managed through limiting voltage (to 1.5·–2· BVCEO), or through circuit designs robust to

base current parameter shifts.

� 2003 Elsevier Ltd. All rights reserved.

1. Introduction

SiGe HBT speed and noise performance continue to

improve, with demonstrated results among the highest

speed and lowest noise of any device in any material

system. Recent performance results exceed 350 GHz fT[1] and NFMIN results demonstrated below 0.4 dB at 10

GHz [2]. Compared to III–V devices, only the smallest

dimension HEMT devices [3] or laboratory InP HBT

devices [4] have demonstrated such high fT or low

NFMIN, and silicon NFETs are expected to achieve

comparable fT performance at the 25 nm node. Largely

responsible for the silicon-based HBT advancement are

material innovations, the first of which is 10–25% Ge

incorporation into the silicon lattice, which provides

bandgap modifications and drift-fields to enhance per-

formance above non-Ge containing devices. Another

more recent material innovation is the additional

incorporation of <1% C into the SiGe epitaxy, which

dramatically reduces the base layer boron diffusion

through subsequent thermal processing and thus reduces

transit time by retaining narrow base layers.

* Corresponding author. Tel.: +1-845-892-4690.

E-mail address: [email protected] (G. Freeman).

0026-2714/$ - see front matter � 2003 Elsevier Ltd. All rights reserv

doi:10.1016/j.microrel.2003.11.003

Structural innovations have also contributed to the

improved performance. Because performance is a func-

tion of parasitic capacitance and resistance as well as

transit times, the reduction in parasitic elements is

also needed. Small feature sizes, shallow junctions, self-

aligned silicides, trench isolation, and other silicon

process features have been employed to maximize device

performance. A survey of the various SiGe HBT devices

reported will find a wide range of structures, reflecting

the baseline silicon process capability at different facili-

ties, as well as differences in innovation (e.g., see [5]).

Thus these material and structural capabilities well make

up for the lower electron mobility in silicon to boost

SiGe HBT performance above most InP and GaAs

based devices.

Device construction to achieve such high perfor-

mance typically results in higher electric fields, higher

temperature operation, or higher current densities, each

of which may result in increased device degradation if

not appropriately accounted for in device design. The

material system and the associated fabrication capability

determine the tools and the innovations available to

adjust for the negative effects of scaling in order to

construct a highly reliable device.

The scaling experience and reliability expectations

from III to V devices are commonly applied to the

ed.

mail to: [email protected]

398 G. Freeman et al. / Microelectronics Reliability 44 (2004) 397–410

silicon system. This may be because the same engineers

who have historically designed and assessed telecom-

munication, space, and military applications with III–V

devices are using SiGe HBTs and more recently silicon

FET devices. Experience defines the expectation of

failure signatures and the methods for assuring reliable

devices. III–V device reliability has historically exhibited

failure modes within the crystal structure that exhibit

abrupt and catastrophic end-of-life characteristics.

There are also failure modes driven by the integrity of

ohmic contacts and by the mesa ledge and its passiv-

ation. Silicon device reliability has historically exhibited

failure modes within device non-crystal elements, such

as dielectrics and thin metal lines. Gradual degradation

is observed in the dielectric interfaces, and catastrophic

degradation may be found in such structures as the

metal lines when overstressed due to improper metal

layout (detailed design guidelines are provided to avoid

these situations).

Regarding the Si or SiGe crystal structure, experience

indicates that, in contrast to III–V systems, the Si/SiGe

crystal structure is extremely robust. From the material

science to the practical fabrication of the devices, there

are many important differences that indicate the

robustness of the SiGe HBT device. First, we note that

the fabrication temperatures used are substantially

higher with silicon and SiGe systems. During the wafer

fabrication, thermal oxidation and anneal process con-

ditions many times exceed 900 �C and at times exceed

1000 �C with well-behaved effects. III–V fabrication

processes generally restrict temperatures to below 500

�C, utilizing low-temperature epitaxial growth and

ohmic metal contact formations as well as mesa struc-

tures for isolations. One reason for the low-temperature

processing in III–V is the difference in diffusion prop-

erties of dopants. Comparing the diffusion constants of

typical p-type dopants Be in GaAs to B in Si (chosen

since they affect base stability in HBTs) one finds that Be

in GaAs exhibits higher diffusion constant of approxi-

mately six orders of magnitude at a moderately high

processing temperature of 800 �C (e.g., see [6]; we note

that due to the complexity of diffusion in III–V hosts,

reported diffusion constants vary widely). As one should

expect, this temperature tolerance difference results in

significant guard banding in normal 125 �C device

operation, where the diffusion constant difference is ex-

pected to be even larger, extrapolating to over 20 orders

of magnitude in favor of the Si system. Because the

implication of the diffusion constant difference is difficult

to understand in the device operation and reliability,

consider the use of these diffusion characteristics for

approximating the temperature required for the dopant

to move a distance of 10 nm in a period of 10 years

(driven only by a concentration gradient). In this extrap-

olation, we estimate that the Be dopant would require a

temperature of 390 �C, compared to B in Si which would

require a temperature of 871 �C for that amount of

movement.

This difference in thermal response manifests itself in

the well-known device failure mechanisms of III–V

systems [7–9], and the observation that such failure

mechanisms have not been reported in silicon or SiGe

systems. Common failure mechanisms in III–V devices

are movement of dopants or host atoms. As a result,

location of the dopant relative to the band offset is

found to change through the life of the device, eventu-

ally resulting in significant rapid degradation once the

dopant moves beyond the band discontinuity. The dif-

ference in gradient-driven diffusion of base dopants

discussed above, while not the same mechanism as takes

place during device operation, still provides insight into

the different electrical mechanisms observed. Addition-

ally, defect clusters may grow within the device, resulting

in increasing charge storage and carrier recombination,

and thus device performance degradation. Or crystal

material movement may cause threading defect migra-

tion in the device, causing sudden shorts or leakage

between device terminals. Heat and current density are

often responsible for accelerating these mechanisms, and

without changes in the fundamental device structure,

increasing these effects with device performance scaling

can impose serious limitations in achieving reliable

performance in III–V devices.

Additional well-known advantages of the silicon

system are the higher thermal conductivity of the silicon

substrate and the narrow line patterning capability,

which together ensures lower device temperature and the

reliable operation of device components that are sensi-

tive to temperature (such as metal migration). At 1.48

W/cmK, the thermal conductivity of Si is approximately

2–3 times higher than InP or GaAs at 0.74 and 0.45

W/cmK respectively. The narrow device dimensions

achievable in the silicon anisotropic dry etches enable

overall lower power (through smaller devices) as well as

better spreading of heat at the device (from a more

narrow emitter stripe), further improving the thermal

properties and reliability of the integrated circuit. Thus,

as compared to III–V systems, the silicon material and

processing capabilities have proven to be robust to his-

toric failure modes in high performance III–V device

reliability. We conclude that, based on fundamental

material properties as well as consistent lack of evidence

that similar mechanisms exist, that the reliability expe-

rience in III–V devices should not be directly applied to

Si devices.

To better understand the reliability of the SiGe HBT

to ever increasing performance, we explore the topic

through a systematic approach focusing on historic sili-

con bipolar device reliability issues. In this paper, we

relate the trends in SiGe HBT device structure and

electrical properties to the known degradation mecha-

nisms in silicon and SiGe bipolar devices. To accomplish

CollectorBase

Ge ramp

Con

cent

ratio

n (l

og s

cale

)

G. Freeman et al. / Microelectronics Reliability 44 (2004) 397–410 399

this, we discuss device scaling in the next section as

background to enumerate the required structure and

electrical modifications to enhance performance. This is

followed by a review of the device degradation mecha-

nisms reported for Si and SiGe devices, relating these

mechanisms to the previously discussed device scaling

trends. In this section, we report the status of high-speed

SiGe HBT device reliability assessment for 200 GHz

HBTs and comment on trends observed. The results and

trends may be extrapolated to the 350 GHz devices and

beyond.

Depth

Emitter Base Collector

Structure Replace Arsenic with Phos.

Reduce interface layer

Narrow baseReduce base doseIncrease Ge rampAdd CarbonImprove extrinsic

structure

Increase concentration

Improve extrinsic structure

Electrical Lower RE

Higher IB

Lower VBE

Reduce total RB

Higher avalancheHigher peak fT JC

Higher CCB

Fig. 1. SiGe HBT device scaling.

2. Device scaling

Device performance is improved through reduction

in transit time and parasitic resistances and capaci-

tances. fT improvement is achieved through improve-

ment in each of the delay components, related to fT in

the well-established approximation:

1

2pfT¼ sEC ¼ sE þ sC þ sB þ sCSCL

� kTqIC

CEB þ kTqIC

�þ RC þ RE

�CCB þ W 2

B

cDnþ WCSCL

2vSAT

;

where CEB and CCB are emitter–base and base–collector

capacitance, RC and RE are collector and emitter resis-

tance, WB and WCSCL are neutral base and base–collector

space charge layer width, respectively, k is Boltzmann

constant, T is temperature, q is unit electron charge, Dn

is the electron diffusivity, c is field factor, and vSAT is the

electron saturation velocity.

Due to its unambiguous definition and straightfor-

ward extraction, fT is probably the most common figure

of merit for an RF transistor. However, in many cases

the fMAX figure of merit is more predictive of circuit

performance [10]. This figure of merit emphasizes RB and

CCB due to their importance in driving power to a load,

as in the following approximation:

fMAX �

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffifT

8pRBCCB

s:

The device design generally focuses separately on the

emitter, the base, and the collector. Fig. 1 illustrates and

itemizes the scaling aspects, and these are discussed be-

low.

2.1. Emitter design

The goal of emitter design in high-speed SiGe HBTs

is to provide an optimal junction depth for maximum fTperformance, to provide low emitter resistance with tight

parametric control, to minimize the adverse effects on

base dopant diffusion during processing, and to provide

for a reliable device as will be discussed later in this

article. Reduced drive-in temperature requirements have

established phosphorous over arsenic as the preferred

emitter dopant in the highest performance SiGe HBTs

[1,11,12]. This lower temperature reduces the base dop-

ant diffusion and thus the electron transit time. On the

other hand, arsenic emitter junction drive-in requires a

higher temperature, which is more compatible with

NFET and PFET device activation anneals. This has

influenced a majority of production BiCMOS processes

to adopt such an emitter dopant. Carbon doping in the

base layer is enabling the use of arsenic in high perfor-

mance BiCMOS processes by minimizing the base

dopant diffusion during these higher thermal cycles

[13,14]. Further, the higher current densities in high

performance SiGe HBTs (due to the collector design to

be discussed) have required the compensation of higher

currents with lower emitter resistance to maintain a low

RE � IC product. This has caused some manufacturers to

adopt an in situ-doped re-aligned emitter with minimal

interfacial oxide [15,16].

2.2. Base design

The goal in base design is the reduction in base tran-

sit time sB without severe degradation in base resistance

and fMAX. Base transit time is typically reduced by some

combination of the following methods: (1) thinning the

base film as deposited; (2) reducing thermal cycles to

minimize the base dopant diffusion; (3) adding carbon to

the SiGe epitaxy to reduce boron diffusion and (4)

increasing the Ge ramp to accelerate electrons more


quickly across the neutral base. In some cases, the total

boron dose (i.e. the base Gummel number) is reduced as

a method to define a thinner base, and in other cases, the

reduced diffusion from temperature and/or the carbon

effect on diffusion leads to a thinner base with the same

total dose. In the former case, the lower boron dose

leads to higher base resistance, which negatively impacts

device fMAX figure of merit, as well as NFMIN, and makes

the device more susceptible to punch-through at higher

collector–base voltages. In addition, the higher base

resistance may have an impact on operating voltage

limits as will be discussed later. The incorporation of

carbon has little effect on the electrical characteristics,

and thus it appears to have little negative effect on device

degradation. Instead, it may produce a positive effect,

from constraining boron diffusion and thus improving

the field at the silicon surface, as will be discussed in the

next section. Further, because the increase in Ge ramp

rate is accompanied by a reduction in base width, the

higher Ge concentration is over a lesser depth in the

device, and thus the effective strain is reduced going to

higher performance devices.

Total base resistance must also be reduced, as the

figure of merit fMAX is highly dependent on the base

resistance, and fMAX need also be increased with fT for

improved circuit performance. The extrinsic base resis-

tance must be reduced. This may be accomplished by a

variety of methods, including raised extrinsic base [11]

and self-aligned silicides to the emitter [17].

2.3. Collector design

Finally, the collector design for high performance

HBTs addresses multiple performance bottlenecks.

First, the collector–base space-charge layer contributes a

significant portion of the total transit time, and must be

reduced by an increase in collector concentration. Sec-

ond, because the charging rate of the collector–base and

emitter–base capacitance is influenced in part by the

small-signal transconductance of the device, an increase

M-1

at V

CB=1

.5V

0

5

10

15

20

25

0 100 200 300 400

Peak fT (GHz)

J C a

t pea

k f T

[mA

/m2 ]

(a) (b

Fig. 2. Effect of collector design on: (a) peak fT current density an

collector–base space-charge region.

in the collector current, and thus the transconductance

is needed. This higher transconductance is achieved

through delaying the onset of the Kirk effect, again with

a higher collector concentration.

Increasing collector concentration negatively impacts

the capacitance of the device and thus partially reduces

the performance gains obtained. Because the increase in

concentration is constrained to the region under and

slightly surrounding the emitter of the device through a

mask and implant step (or self-aligned implant), the

impact is minimized. Further, because the mask overlay

control is improved between technology generations, the

surrounding extrinsic parasitic capacitance may be re-

duced. Also, at the option of the circuit designer, the

mask may produce a complete block to the implant,

resulting in an alternate device with lower collector

concentration that may be optimal for purposes where

the bias current is not required to be as high.

The straightforward increase in collector concentra-

tion has probably the greatest impact on the concerns

for device degradation as will be discussed in Section 3.

The electrical effects are shown in Fig. 2. Fig. 2a shows

the increased peak fT current density JCP resulting

from the delayed Kirk effect as a function of peak fT for

various device designs. This has implications to device

self-heating and other degradation if device sizes are not

adjusted to take such effects into account. Fig. 2b shows

the increased collector current avalanche multipli-

cation M-1, also as a function of peak fT value. Since

this avalanche process is a result of high kinetic energy

carriers and high electric fields, it results in significant

hot-carrier generation at some bias conditions, as will

also be discussed.

Extrinsic collector resistance reduction is also a key

element to performance enhancement. The higher col-

lector dose just described, as well as modifications to the

subcollector layer and the elimination of shallow-trench

to reduce the resistive path length [18] may have an

impact. Because only majority carriers are involved, and

no significant degradation has been identified relating to

0

0.005

0.01

0.015

0.02

0 100 200 300 400

Peak fT (GHz))

d (b) excess collector and base current from avalanche in the


the collector–base diode, these modifications are not

expected to result in significant reliability implications.

3. Silicon bipolar transistor reliability

The various bipolar degradation signatures and

mechanisms are described next. We relate the mecha-

nisms to the device scaling just described. The degra-

dation mechanisms are organized into the regions of

device operation as shown in Table 1.

3.1. Reverse emitter–base

Reverse emitter–base stress, with the emitter–base

diode in reverse bias and the collector terminal either

open or shorted to the base, not only measures the

degradation of the device in reverse operation, but also

characterizes the emitter–base passivation for suscepti-

bility to interface trap generation [19,20]. Poor degra-

dation is typically a result of a combination of the

electric field at the emitter–base perimeter as well as the

quality of the passivation to silicon interface. Worsened

degradation from this stress is not expected to accom-

pany performance improvements in the device since

vertical scaling fundamentally does not involve changes

in these structural elements. Further, little or no degra-

dation is expected from the reverse bias condition in

actual operation on most circuits. This is due to the fact

that the energy required to form the interface traps is not

likely to occur in typical ECL circuits, or in other con-

figurations where this is more likely, the excursions may

be limited by certain circuit topologies [21].

To illustrate that little change in degradation is ex-

pected from reverse operation for high performance

Table 1

Bipolar reliability overview and performance trend related issues

Operation

region

Stress condition Typical

signature

Mechanism

VBE VBC

Reverse ) Low bias IBnon-ideality

E–B oxide

interface

states

Saturation + + Low bias IBnon-ideality

E–B oxide

interface

states

Forward

mode

+ ) Low bias IBnon-ideality,

parallel IBshift, RE shift,

self-heating

E–B oxide

interface

states, poly–

sc interface

oxide, metal

migration

Avalanche + ) Low bias IBnon-ideality,

self-heating

E–B oxide

interface

states

devices in comparison to lesser performance devices,

we show in Fig. 3 the degradation in base and collec-

tor current for very different emitter structures, with the

arsenic emitter of an fT ¼ 120 GHz device and the

phosphorous emitter of the fT ¼ 200 GHz device. No

degradation is observed at a reverse bias of 2 V in both

cases, confirming the earlier point that degradation in

this operating regime does not present a concern for

continued scaling to higher performance.

3.2. Saturation

Operation of the device in saturation, where both the

emitter–base and collector–base junctions are forward

biased, is similarly of limited concern in device scaling.

Again, the degradation occurs in the emitter–base pas-

sivation and occurs principally with significant minority

carrier injection from the collector–base diode into the

neutral base [22]. Like the reverse bias condition, the

properties of the device structure relevant to this deg-

radation change little with increased performance de-

vices. Also, circuits designed to take advantage of high

performance devices are not driven into saturation as

this affects the propagation delay of the output signal.

Furthermore, the need to approach saturation during

operation is alleviated by the smaller voltage swings seen

in these circuits. Thus this presents little concern for

scaling.

3.3. Forward mode

Forward bias operation is a concern for device scal-

ing, since the operation current density increases be-

tween generations, of the order shown in Fig. 2. Several

Stress condition

in typical

circuit?

Trend with

scaling

Remedy Refs.

Limited Neutral Limit reverse

voltage in design

[19–21]

Limited Neutral Limit saturation

voltage in design

[22]

Yes Worse Min. interface

oxide, min. e-

fields at surface,

narrow WE

[22–30]

Yes Worse Design robust to

IB variations,

limit voltage in

design

[33–35]

1.E-15

1.E-13

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

0.2 0.4 0.6 0.8

VBE (V)

IC initialIC finalIB initialIB final

1.E-15

1.E-13

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

0.2 0.4 0.6 0.8

VBE (V)

Ib, I

c (A

)

IC initialIC finalIB initialIB final

fT = 120 GHz fT = 200 GHz

Fig. 3. Reverse emitter–base junction degradation for 120 and 200 GHz devices with As and P emitters, respectively. Stress condition is

VBE ¼ �2 V, collector open, for 104 s and TAMB ¼ 30 �C.


degradation signatures are relevant and will be discussed

here.

Low-bias base current non-ideality caused by for-

ward mode stress has been observed for some devices

[22–25] and not observed for other devices [26]. Again, it

has been proposed that the forward operation may cause

the creation of surface states at the emitter–base

perimeter passivation silicon-oxide interface. Because a

carrier traversing the emitter–base space charge region

does not have sufficient energy to create such a state, it

has been proposed that such energy may be created

through Auger recombination [27]. Because such deg-

radation has not been observed in some devices, it ap-

pears that the degradation is sensitive to the specific

device structure. In particular the low-bias base current

non-ideality appears to be less common in SiGe devices.

The epitaxy process may have a significant advantage in

containing the boron to a deeper region of the device

compared to an implanted base process, thus reducing

the electric fields at the emitter–base interface and

reducing many of the degradation mechanisms associ-

ated with the emitter–base passivation [28]. The trend

toward reducing the boron diffusion in high-perfor-

mance devices maintains the low electric fields at the

passivation interface, and thus is expected to maintain

low degradation in the device.

A second signature is a parallel shift in the base

current when plotted on the logðIBÞ versus VBE plot.

Once again, device structure appears to affect how a

device behaves with regard to this signature. Both an

increase in IB [25,26] and a decrease in IB [23–26,29] have

been observed. In both cases, the change has been

attributed to the modification of the very thin oxide

layer between the single-crystal to polycrystalline emitter

regions of the device with high current stress. In the case

of increasing IB, it has been hypothesized that the gen-

eration or de-passivation of traps with high current

density enhances the trap-assisted tunneling through the

oxide material, causing the increase in IB [25,26]. This

has been reported to accompany a reduction in emitter

resistance RE due to the same mechanism [26]. In the

case of a parallel reduction in IB, again the interfacial

oxide is implicated, with a hypothesis that the hydrogen

passivation of the interface states cause reduced hole

recombination velocity at this interface [23,24,26,29].

Although the mechanism has been reported to pro-

ject a relatively small shift in base current over the life-

time for a device with fT ¼ 120 GHz, a strong current

sensitivity was also reported [25,26], suggesting this

interfacial film may pose significant degradation issues

with higher performance devices. We show here a similar

current density sensitivity in the degradation of the

fT ¼ 200 GHz device. Fig. 4 shows the time evolution of

beta degradation for an fT ¼ 200 GHz device, illustrat-

ing the difference in degradation between two samples.

The stress of these samples differ in both stress current

density JSTRESS and junction temperature TJ. In Fig. 5,

we show the degradation of a variety of devices with

different junction temperatures, but with constant

JSTRESS. Evident from these two plots is that JSTRESS has

a greater impact accelerating the device degradation

than TJ. As described in both [25] and [26], the 2· cur-

rent stress has the effect of accelerating the device deg-

radation time by a factor of more than 100·. In the

referenced work, the temperature played a small role in

acceleration, as is also demonstrated in Fig. 5 in this

work. With this assumption, the 2X stress degradation

in Fig. 4 may be considered compressed on the time

1.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-031.E-02

0.4 0.5 0.6 0.7 0.8 0.9 1VBE

IB, I

C (A

)

-50%-25%

0%25%50%

0.6 0.7 0.8 0.9 1VBE

∆IB

∆IC∆β

Fig. 6. Gummel plot of 1· stress after 1140 h at 160 �Cambient. Solid lines are the pre-stress currents and dotted lines

after stress. Inset is the change in post-stress current compared

to the pre-stress current. Measurement is at 25 �C ambient.

-10-8-6

-4-2024

68

10

1 10 100 1000 10000Stress time (Hrs)

% B

eta

shift

AE=0.12x2.5µm2

Jstress=11mA/µm2 (1x IC at peak fT)Tamb=160C, Tj =192C

VCE=1.5VAE=0.12x2.0µm2

Jstress=22mA/µm2 (2x IC at peak fT)Tamb=180C, Tj=239C

Fig. 4. Current gain shift under forward-mode stress, com-

paring stress current of 1· and 2· of IC at peak fT. Measure-

ment and stress condition are the same.

-10

0

10

1 10 100 1000Stress time (Hrs)

% B

eta

shift

AE=0.12x2.0µm2, TJ=239C, TAMB=180CAE=0.12x0.64µm2, TJ=214C, TAMB=180CAE=0.12x2.0µm2, TJ=159C, TAMB=100C

Fig. 5. Current gain shift under forward current stress com-

paring two different size devices and two ambient temperatures,

all with the same stress current density of 2· peak fT JC ¼ 22

mA/lm2. Measurement is at 1· peak fT JC and at the stress

temperature.


scale compared to the actual expected degradation at 1·operation. By shifting the 2· degradation characteristics

on the log time scale to approximately 100· later in time,

one may approximate the expected degradation to

approximately 3 · 104 h. It is worth noting that base

current degradation is gradual, indicating a lack of any

catastrophic failure.

Fig. 6 shows the parameter shift bias dependence at

the end of the stress, for the 1· stress device of Fig. 5

now measured at 25 �C. Note that the fractional shift in

base current for the 200 GHz device is similar across the

entire low-VBE bias range, diminishing above VBE ¼ 0:85V where it is increasingly dominated by emitter resis-

tance. The small collector current shift (and similar

amount of base current shift) is likely a result of a slight

(i.e. 1–2 �C) ambient temperature condition difference

present during the module test outside of the stress

chamber.

For the forward current degradation just described,

we compare the direction of parameter shift and the time

dependence to the referenced work. In contrast to Figs.

4 and 5 of this work, where the current gain monoton-

ically increases with time, Refs. [25,26] report an initial

decrease in current gain followed by an increase occur-

ring (either measured or projected) between 103–105 h of

operation. The stress on the 200 GHz device here shows

a result more similar to the effect reported in [23], where

a decrease in current gain is not observed, and current

gain only increases. Each report ascribes the shift in

current gain principally to a base current shift, as we

have shown in Fig. 6. Each report also indicates an

acceleration resulting principally from high current

density (rather than temperature) as we also have ob-

served here.

As described above, the commonly understood

mechanism responsible for this shift in base current is

the generation or passivation of the traps at the emitter

single-crystal to polysilicon interface. The increase of

base current is a result of the generation of traps, and

the decrease of base current is a result of the passivation

of traps. In the reports of [25,26] with an increase fol-

lowed by a decrease in IB, competing mechanisms are

suggested with trap generation followed by passivation.

The passivation process is described in [23] and is sup-

ported with further evidence in [25]. In this model,

hydrogen bound to metal and polysilicon grains is re-

leased by the high electron flux. These hydrogen atoms

migrate to the region of the device where minority car-

rier (hole) diffusion length affects the base current in the

device. With the hydrogenation of silicon dangling

bonds within the polysilicon–single-crystal interface re-

gion, the recombination velocity and thus the base

current is reduced. The absence of the initial increase

of base current observed in this work implies that no


significant trap generation occurred in the early phase of

the stress on the 200 GHz devices. Instead, it indicates

that the parameter shift was dominated by the passiv-

ation of the existing traps.

The time progression shown in Figs. 4 and 5 are

measured at high current densities, where device resis-

tances cause the parameter shifts to be less obvious

compared to the low-bias region of operation. This bias

region is more representative of device operation con-

ditions, but the lower bias region provides more insight

into the origin of the parameter shift and a better

comparison to published work. In Fig. 7, we compare

the time progression of degradation measured at low

bias for the device described here and three published

devices, each stressed at similar current densities in the

vicinity of 10 mA/lm2. Note that even though the

comparison is at similar current densities, the current

density for each device to attain its peak fT performance

may be much different between these devices. Thus the

degradation shown here is not a comparison of degra-

dation at operating conditions for all devices.

Note again the difference in sign of degradation be-

tween the different devices. This suggests that the trap

generation mechanism, indicated by the reduction of

beta (i.e. an increase in IB) is minimized in the device

design and fabrication of the 200 GHz device. Also by

minimizing the presence of hydrogen and optimizing the

interface properties, it has been possible to minimize the

magnitude of increasing beta in the 200 GHz device

compared to other devices shown. The comparison

indicates that optimized process conditions and device

design may achieve reduced parameter degradation

required for the higher current density operation.

-15

0

15

0.01 0.1 1 10 100 1000Sress time (Hrs)

% B

eta

or -%

IB s

hift

[23] 150C 10mA/µm2 0.5V[25] 125C 11mA/µm2 0.8V[26] 140C 8.5mA/µm2 0.7VThis work 160C 11mA/µm2 0.7V

Fig. 7. Comparison of beta shifts across published work mea-

sured at low bias, each stressed in the vicinity of the current

density used in this work. In cases [23,26], �IB shifts are shown

and IC shift is indicated to be small. The legend lists the stress

and measurement ambient temperature and stress current

density, with measurement bias point.

The degradation so far described, and which the de-

signer to some degree should expect, is regarding base

current and emitter resistance. For ECL and CML cir-

cuits, which are the most common high-speed circuit

configuration, the variation in base current in itself is

not much of a concern since it does not alter the oper-

ating points. In other configurations that are more

sensitive to base current degradation, an understanding

and modeling of the degradation will enable the designer

to avoid the degradation through the device bias, or to

design the circuit for tolerance to the degradation. The

reduction in RE, while it affects operating point, gain,

and noise margin, must be once again included in the

device model and thus worst case scenarios can be

evaluated during the design process.

What remains to be discussed are the electromigra-

tion concerns in delivering the current to the device and

managing the device self-heating. These topics are clo-

sely tied, since the self-heating negatively impacts the

metal migration, and the metal migration in turn limits

the useable current through the device. An approach to

view this is through the simultaneous solution of the

current–temperature relations for both maximum cur-

rent allowed through a metal configuration and device

self-heating, conservatively assuming the metal temper-

ature is the same as the junction temperature. This ap-

proach is applied to a 200 GHz device as shown in Fig.

8, and provides a boundary for the steady-state bias of

the device to maintain reliable operation. The goal is to

enlarge the useable operation range as much as possible

through device design and reliability analysis. Modifi-

cations to device thermal resistance or metal current

carrying capability from layout or material system

0

5

10

15

20

0 0.5 1 1.5 2 2.5 3

VCE [V]

JC [m

A/µ m

2 ]

1 um2.5 um5 um10 um

Region of safe operation for electromigration

Region of concern for electromigration

Boundaries

Fig. 8. Boundary conditions by emitter stripe length, obtained

for each bias point through simultaneous consideration of both

maximum current through a metal line and device self-heating.

Curves represent 200 GHz device with a certain layout.


improvements (such as the improvements from copper

interconnect) strongly affect this boundary.

Approaching the layout from the view of improving

electromigration, the target is to obtain constant or re-

duced collector and emitter current per length of emitter

with increasing peak fT current density JCP. Employing

the technique known as constant current scaling requires

reducing the emitter stripe width WE in proportion to

1/JCP, such that the current through the metal system is

constant and the electromigration issues are the same

between generations.

Thermal resistance may also be maintained with this

technique. Because designers typically choose the device

size to achieve a certain peak fT current, it is illustrative

to compare the self-heating effect of different scaling

methods from a fixed current perspective. To maintain

fixed current, the emitter area between device genera-

tions is proportional to 1/JCP. With a peak fT current of

2 mA and utilizing a structure-based analytic thermal

model as described in [30], we compare in Fig. 9 the

approximate self-heating of devices from fT ¼ 47 to 350

GHz. The emitter scaling methods compared are to (1)

fix WE and vary the length with 1=JCP, or (2) fix the

emitter length and vary WE with 1/JCP. The case with

fixed WE results in more concentrated power dissipation

as well as substantial deep-trench enclosure area reduc-

tion, and consequently a large increase in thermal

resistance and self-heating for the higher current density

devices. In contrast, the emitter width scaled as 1=JCP

maintains a near constant device perimeter and main-

tains only a slight decrease in the deep trench enclosed

area. Thus the self-heating is managed with an appro-

priate reduction in stripe width. With the 0.20 lm device

as a baseline, we find that WE of 0.12 and 0.075 lm for

200 and 350 GHz devices, respectively, are required for

the device self-heating properties shown in Fig. 9.

Thus we find that the two most fundamental con-

cerns regarding increasing current density, e.g., provid-

ing current to the device through the metal system and

0

5

10

15

20

25

30

0 100 200 300 400Peak fT [GHz]

Dev

ice

self-

heat

ing

∆TJ

[K] We=0.2um fixed

We scaled with 1/Jc

Fig. 9. Self-heating versus fT for length compared to width

scaling.

the self-heating of the device, critically depend upon the

ability to spread the current over the length of the device

and maintain a near constant current per unit length of

the device. With emitter width reduction in proportion

to inverse peak fT current density, we expect that the

device may be scaled for reliable operation beyond peak

fT values of 350 GHz and JCP of 20 mA/lm2.

3.4. Avalanche

It is well known that lower breakdowns accom-

pany higher fT performance [31]. With the collector–

base breakdown BVCBO and off-state collector–emitter

breakdown BVCER in the range of 5–6 V for devices with

fT of 350 GHz, designers may find considerable latitude

in voltages that they may apply to the device. However,

the on-state breakdown is considerably more complex

since the carriers that traverse the collector–base space-

charge layer generate significant additional carriers

through a process of avalanche multiplication. To

illustrate the magnitude and the scaling, we show in Fig.

10 the avalanche current multiplication factor M-1 ver-

sus VCB for various device designs. Note that the M-1

value for fixed VCB is plotted in Fig. 2b and shows an

approximate linear relation to device peak fT. Looked at

with an eye to maintaining a constant avalanche multi-

plication M-1, it is interesting to note that the voltage

reaches a near minimum (e.g. at approximately VCB ¼1:4 V for M-1¼ 0.01). This has implications on the

voltage limits with continued device scaling as will be

apparent with the discussion that follows.

The bias voltage at which the avalanche current in

the device becomes significant (i.e. the same as the base

current) is approximately BVCEO, which is reported to be

1.4 V for the 350 GHz device. Many designers have

viewed the value of BVCEO as a limit to avoid due to the

additional complications it represents. With ever-higher

Fig. 10. Avalanche multiplication for SiGe HBTs with increas-

ing fT performance.

0

50

100

150

200

250

0.0001 0.001 0.01Ic (A)

fT (G

Hz)

1.5

2.0

2.5

VCB

Fig. 11. fT performance variation with increasing avalanche, at

VCB values listed in legend. VCE values range from approxi-

mately 2.4–3.4 V at peak fT, compared to BVCEO ¼ 1:8 V.

Emitter size is 0.12· 1.0 lm2.


fT and ever-lower BVCEO devices, the design boundary is

now required to go beyond BVCEO, and the operation

and degradation mechanisms of the device need to be

better understood in this operation regime.

First, we demonstrate that performance does not

significantly degrade due to avalanche. Shown in Fig. 11

are fT vs. IC characteristics with various VCB bias points

for the fT ¼ 200 GHz SiGe HBT. It is apparent that the

avalanche conditions have little effect on the AC per-

formance of the device. The small fT reduction might be

ascribed to the increasing junction temperature with

increasing VCB. Circuit results also demonstrate the

performance capability of the SiGe HBT operating over

BVCEO. For instance, an electro-absorption modulator

driver operating to 48 Gb/s with an fT ¼ 120 GHz SiGe

HBT has been reported, where a device with BVCEO of

1.9 V drives an output of 3.5 V peak–peak, resulting in a

device which sustains VCE of approximately 4.5V [32].

This again demonstrates the lack of performance loss

operating well over BVCEO.

With the understanding that BVCEO is not a hard bias

limit and high-speed operation can take place well above

BVCEO, we wish to explore what limits the maximum

voltage, and how this varies with device scaling. The

answer is complex, and in part depends on the applica-

tion. First, voltage driven self-heating needs to be con-

sidered. This is mostly independent of avalanche, but

imposes a practical limit to the current–voltage product.

Also, increased avalanche impacts noise, and device bias

voltage must be kept low to minimize avalanche and

maintain low noise. Fortunately, the circuit designer

typically has flexibility in choosing a collector through

the previously described mask-selectable collector op-

tion in the device layout. Since low collector current is

typically chosen as a bias point for the lowest noise

conditions, the higher collector concentrations are not a

requirement for the operation of the low noise device

since the peak fT is generally not utilized. An alternate

lower concentration collector, typically available on the

same chip, provides an alternative to the designer with

little loss of performance at lower bias conditions but at

an incrementally higher fabrication cost.

More fundamental are the effects of avalanche on

device instability and on device degradation. These ef-

fects are discussed in [33] and [34,35], respectively, and

are described here in the context of device scaling.

Instability results from the avalanche current flowing

out of the base, causing a reversal in base current and a

potential drop across the intrinsic base. A significant

potential drop across the intrinsic base results from a

large amount of avalanche current, and can cause a

device operation discontinuity, or ‘‘pinch-in’’ of the

device operation into the center of the device. While

degradation has not been associated with this phenom-

enon, it appears to represent a device operation dis-

continuity that should be avoided. Shown in Fig. 12 is a

diagram of three regions of device operation: low,

moderate, and high avalanche, with varying VCB. The

third region of operation illustrates the just described

‘‘pinch-in’’ condition, where the avalanche causes the

current to focus into the center of the device. The pinch-

in voltage is both a function of avalanche and of base

resistance. In order to compare different device designs,

one may compare the pinch-in voltage according to the

technique described in [33]. This pinch-in is observed as

the voltage at which VBE drops abruptly on a common

base, forced IE measurement, as shown in Fig. 13 for

various device designs. This set of characteristics show

that the lower performance devices do not demonstrate

pinch-in below 5 V. The remaining devices, at fT ¼ 120,

195, and 210 GHz, show little trend in the pinch-in

voltage with increasing avalanche and fT. This is because

of a dramatic decrease in base resistance from the 120

GHz device to the 195 and 210 GHz devices. Thus the

increased avalanche does not fundamentally reduce the

instability voltage, since base resistance scaling, which is

required for fMAX optimization in device design, com-

pensates the negative effect and maintains an acceptable

pinch-in voltage.

Increased avalanche in high-speed devices under

forward current operation also affects device degrada-

tion as described in [34,35]. Hot carriers generated in the

collector–base space-charge region are said to traverse

to and damage the perimeter emitter–base dielectric and

the base–collector dielectric. The location of the hot

carrier generation and the damage are shown in Fig. 14.

The degradation signature of most concern appears to

relate to the damage created in the emitter–base peri-

meter dielectric, and is observed in the base current

degradation at low bias, in a similar fashion described

earlier for degradation from different operating regimes.

An example of this degradation is shown in Fig. 15.

h+ h+

EB(a) EB

h+h+

(b)

EB

h+h+

(c)

Fig. 12. Avalanche effect on device operation: (a) low VCB; (b) moderate avalanche and (c) ‘‘pinch-in’’ resulting from high voltage drop

across base resistance.

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0 1 2 3 4 5Vcb (V)

Vbe

(V) a

t Ie=

1e-5

210

195

120

90

50

Fig. 13. Measured VBE vs. VCB for fixed IE ¼ �10�5 A. Pinch-in

is apparent in the voltage drop across the base resistance,

exhibited as a sudden drop in VBE. The legend lists the peak fTvalue for the device in GHz.

Fig. 14. Hot carrier generation from avalanche and trapping in

dielectric layers.

1.E-13

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

0.1 0.3 0.5 0.7 0.9

I C, I

B [A

]

T0

T1

VBE [V]

Fig. 15. Avalanche generated base current degradation for 200

GHz SiGe HBT. Emitter area is 0.12· 2.0 lm2. Stress is

VCB ¼ 2:5 V, IE ¼ 1:92 mA. T0 is the initial device characteristic

and T1 is after 8.3 h under the specified stress.


Device degradation on the 200 GHz SiGe HBT in

avalanche (i.e. operation above BVCEO) has been re-

ported and a model presented in [35]. The key data upon

which the model is built is shown in Fig. 16. As observed

in this plot, degradation exhibits a power-law function

of avalanche charge (which is principally a function of

collector–base voltage VCB and collector current) and an

exponential function of VCB. The unit perimeter base

current degradation DIB=PE is a function of the accu-

mulated avalanche charge normalized to device perim-

eter QB=PE, as exhibited in the following empirical

relation:

DIB=PE ¼ A expð�V0=VCBÞðQB=PEÞn

where A, V0 and n are fitting parameters for a given VBE

bias. The model does not account for possible saturation

1E-3 0.01 0.1 1

1E-3

0.01

0.1

∆I B/

PE,

(nA/

µm)

QB/PE, (C/µm)

VCBstr=3.0 V VCBstr=2.5 V VCBstr=1.5 V

Fig. 16. Avalanche base current degradation normalized to

device perimeter versus avalanche charge normalized to device

perimeter, for different collector–base voltage VCB.


effects as observed in Fig. 16 above 0.1 C/lm, and so it is

conservative. Further investigation is required to

understand the saturation of the degradation with

increasing avalanche charge, and the degradation recov-

ery during forward non-avalanche bias.

Conservatively neglecting the saturation and recov-

ery effects, the model predicts degradation that is

acceptable for most applications with typical voltage

operation above BVCEO. For instance, in a digital

application with a load line on the 200 GHz device

traversing VCE from 2.0 to 2.5 V, assuming the operation

in the avalanche regime is approximately 1% of the total

operation time, degradation after 100 K power-on hours

is expected to be approximately 5% in IB at a 10% peak

fT bias point [35]. Again, the allowable degradation is

highly application dependent, and many applications are

likely to tolerate much higher degradation (e.g. see [36]

which reports X–Ku band 1W HBT power MMIC,

where 40% DC gain loss at the operating point causes a

relatively small <0.5 dB power loss), and thus be able to

operate with higher VCB, with little loss of performance.

Again, we address how scaling is expected to influ-

ence the degradation just described. At a given collec-

tor–base voltage, the degradation is expected to become

worse between generations according to the M-1 in-

creases as shown in Fig. 2b. However, because degra-

dation is a sensitive function of voltage due to the

exponential collector voltage dependence of both ava-

lanche carrier generation and of interface state creation,

the negative effects of avalanche can easily be reduced by

a small decrease in operating voltage.

In summary this avalanche-induced hot carrier deg-

radation appears to introduce a degradation mechanism

not clearly observed in lower performance devices, due

to the higher collector concentration and higher ava-

lanche current. Compared to the pinch-in voltage, this

degradation mechanism appears to take place at a lower

voltage, at approximately VCE ¼ 3 V. Because the deg-

radation only takes place when the device experiences

higher values of VCE, and because it is seen in base

current and not in the more critical collector current, it is

expected that a limited number of circuit configurations

will be affected. Those that are affected may employ

robust circuit techniques, such as common base config-

urations, to substantially reduce the performance impact

to such device parameter shifts.

4. Conclusions

We find that with the appropriate attention to device

design as well as some attention in the circuit design in

less common high and low voltage regimes, the trends in

SiGe HBT design to increase performance to over 350

GHz impose no fundamental limitations to fabricating

reliable circuits. Device design needs to focus on

reducing stripe widths for electromigration and self-

heating, and the emitter polysilicon to single-crystal

interface layer needs to be minimized to reduce base

current and emitter resistance shifts. Further, the

reduction in base resistance, which is already a key de-

sign goal in advanced HBTs, is needed to maintain a

high pinch-in voltage. Avalanche introduces a degrada-

tion mechanism, to be taken into account when

designing at the highest voltages. In general, it should be

possible to continue scaling beyond today’s 200 GHz

devices and the demonstrated 350 GHz devices, with

straightforward extension of the mechanisms and con-

cerns outlined in this paper.

Acknowledgements

The authors would like to acknowledge partial sup-

port of this work by DARPA under SPAWAR contract

number N66001-02-C-8014. The authors also would like

to thank Seshadri Subbanna, Peter Cottrell and David

Greenberg for their helpful discussions, and Dale Jadus

and Michael Longstreet for their help in the device test.

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