rembrandt™-102 (rm102) data sheet -...

Rembrandt™-102

(RM102) Data Sheet

OPD-01-009-0403B August 2003

Confidential

Terms and Conditions Rembrandt-102 Data Sheet

Company Headquarters Oplus Technologies Ltd. Shaar Yokneam Tavor Building 2 P.O. Box 563 Yokneam 20692 Israel Tel: +972-4-959-2288 Fax: +972-4-959-2289 Email: [email protected], [email protected] Website: www.oplus.com

Proprietary and Confidential Copyright (c) 2003 Oplus Technologies Ltd. All rights reserved. Oplus, the Oplus logo, Rembrandt, Matisse, Monet, The Art of Display, Display to Perfection, PMR, Pixel Entropy, ICC, FlexScale, AutoDAP, KeystoneC, FlexPIP and SID are trademarks of Oplus Technologies Ltd. (hereinafter: “OPLUS”), and may be registered in certain jurisdictions. Any use of these trademarks without the explicit prior written consent of OPLUS is strictly prohibited. All other trademarks are the property of their respective owners. The information contained herein is proprietary and confidential. Any reproduction, in whole or in part or the divulgence of any of its contents, without the prior written consent of OPLUS, is prohibited. The contents of this document are given for general information purposes only. All rights in OPLUS products are the sole property of OPLUS. NO LICENSE is granted in any intellectual property rights by this document and/or by the purchase and/or use of an OPLUS product - whether express or implied, in whole or in part, by estoppel or otherwise. OPLUS assumes no liability whatsoever - and OPLUS disclaims any express or implied warranty - relating to the use of OPLUS products, including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any third party patent, copyright or any other intellectual property right. OPLUS further disclaims any liability of indemnification for whatever event, cause or claim. In no event shall OPLUS be liable for any indirect, incidental, or consequential damages as a result of the product’s performance. Caution! - OPLUS products are not intended for any use in life saving and/or life sustaining applications and/or in any applications where such use might reasonably result in bodily harm/injury. OPLUS may make changes to specifications and product descriptions at any time, without notice. It is recommended that users keep abreast of such changes and attain current versions of such specifications and product descriptions.

2 Confidential Oplus Technologies Ltd.

mailto:[email protected]

mailto:[email protected]

Rembrandt-102 Data Sheet Revision History

Revision History OPD-01-009-0403B Version Date Description OPD-01-009-0403B August 2003 Original version

Abbreviations CSC – Color Space Conversion/Converter CTI – Color Transition Improvement DI – De-Interlacer FRC – Frame Rate Conversion ICC – Independent Color Control IF – Interface LTI – Luma Transition Improvement LUT – Look Up Table NRF – Noise Reduction Filter OSD – On Screen Display PIP – Picture In Picture PLL – Phase Locked Loop PMR – Pixel Mode Recognition RM102 – Rembrandt-102 multimedia display processor chip SMF – Static Motion Filter VIF – Video Interface

Related Documents Rembrandt-102 (RM102) Preliminary Register Details, OPD-01-012-0803A, August 2003

Oplus Technologies Ltd. Confidential 3

Revision History Rembrandt-102 Data Sheet

Blank Page


Rembrandt-102 Data Sheet Contents

Contents 1 RM102 Overview ..............................................................................................................9

1.1 Description .................................................................................................................9 1.2 Features.......................................................................................................................9 1.3 Applications..............................................................................................................10 1.4 Ordering Information................................................................................................10

2 Functional Overview ......................................................................................................11 2.1 Functional Description .............................................................................................12 2.2 Video Path ................................................................................................................12 2.3 Graphics Path............................................................................................................13 2.4 Output Path...............................................................................................................13 2.5 Services.....................................................................................................................14

3 Functional Signal Definition..........................................................................................17 3.1 Pin Out Schematic ....................................................................................................17 3.2 Pin Descriptions........................................................................................................18

3.2.1 Graphics Input Port...........................................................................................18 3.2.2 Video Input Port ...............................................................................................19 3.2.3 Display Port ......................................................................................................20 3.2.4 SDRAM Port ....................................................................................................21 3.2.5 CPU Port...........................................................................................................22 3.2.6 MISC ................................................................................................................22 3.2.7 PLL Inputs ........................................................................................................22 3.2.8 JTAG Port Interface .........................................................................................22 3.2.9 Pin Out Location...............................................................................................23 3.2.10 Functional Ball Table .......................................................................................24 3.2.11 Power and Ground Ball Table ..........................................................................25

4 Electrical Specification...................................................................................................27 4.1 Absolute Maximum Ratings.....................................................................................27 4.2 DC Electrical Specifications.....................................................................................27

4.2.1 Power Supplies .................................................................................................27 4.2.2 Digital Inputs ....................................................................................................27 4.2.3 Digital Outputs .................................................................................................27

4.3 AC Electrical Specifications.....................................................................................28 4.3.1 Graphics Input Port...........................................................................................28 4.3.2 Video Input Port ...............................................................................................28 4.3.3 Display Port ......................................................................................................29 4.3.4 SDRAM Port ....................................................................................................30 4.3.5 CPU Port...........................................................................................................31 4.3.6 Miscellaneous ...................................................................................................32

5 RM102 Interfaces ...........................................................................................................35 5.1 Video Port Interface .................................................................................................35 5.2 Graphics (Data) Port Interface..................................................................................38

5.2.1 D_VSYNC, D_CSYNC and D_HSYNC .........................................................38 5.2.2 Interlaced and Progressive Inputs.....................................................................39 5.2.3 D_INA and D_INB...........................................................................................40 5.2.4 Graphics Input Active Region ..........................................................................42 5.2.5 External ADC and PLL Support.......................................................................43


Contents Rembrandt-102 Data Sheet

5.2.6 Graphics Port Connection Examples ............................................................... 43 5.3 Display Port ............................................................................................................. 45

5.3.1 OP_A and OP_B .............................................................................................. 45 5.3.2 Display Lock Modes ........................................................................................ 45 5.3.3 OP_HSYNC, OP_VSYNC and OP_ENABLE................................................ 46 5.3.4 Progressive and Interlaced Outputs.................................................................. 47 5.3.5 OP_FIELD_3D ................................................................................................ 49 5.3.6 Power Up Sequence ......................................................................................... 49

5.4 SDRAM port ............................................................................................................ 49 5.5 Control Port.............................................................................................................. 52

5.5.1 JTAG port ........................................................................................................ 54

6 Typical Application System .......................................................................................... 55

7 RM102 Register Tables ................................................................................................. 57 7.1 General Registers ..................................................................................................... 57 7.2 NL Scale Tables ....................................................................................................... 59 7.3 Video Path Registers................................................................................................ 59

7.3.1 General ............................................................................................................. 59 7.3.2 Video Port Interface ......................................................................................... 60 7.3.3 Video In Filter.................................................................................................. 60 7.3.4 Video Out Filter ............................................................................................... 60 7.3.5 Video CTI ........................................................................................................ 61 7.3.6 Video Down Scaler .......................................................................................... 61 7.3.7 Video Up Scaler ............................................................................................... 62 7.3.8 Video De-interlacer (DI).................................................................................. 62

7.4 Graphics Path (or Data Path) Registers.................................................................... 62 7.4.1 General ............................................................................................................. 62 7.4.2 Graphics Port Interface .................................................................................... 63 7.4.3 Graphics CTI.................................................................................................... 64 7.4.4 Graphics Filter.................................................................................................. 64 7.4.5 Graphics Down Scaler ..................................................................................... 65 7.4.6 Graphics Up Scaler .......................................................................................... 65

7.5 Output Path Registers............................................................................................... 66 7.5.1 Output Windows .............................................................................................. 66 7.5.2 YUV Lookup Tables........................................................................................ 66 7.5.3 RGB Lookup Tables ........................................................................................ 67 7.5.4 Palette Tables ................................................................................................... 67 7.5.5 RGB Color Space Converters .......................................................................... 67 7.5.6 General Output Path......................................................................................... 68 7.5.7 OSD.................................................................................................................. 68 7.5.8 Keystone........................................................................................................... 68 7.5.9 Dither ............................................................................................................... 68 7.5.10 Display Interface .............................................................................................. 69

7.6 SDRAM Control ...................................................................................................... 70 7.7 Measurement Unit.................................................................................................... 71 7.8 Miscellaneous........................................................................................................... 73

8 Package Information ..................................................................................................... 75

9 Reflow Profile ................................................................................................................. 77

10 Appendix 1: RM102 Comparison to RM1A............................................................ 79


Rembrandt-102 Data Sheet Contents

Figures Figure 1: RM102 Internal Block Diagram ...............................................................................11 Figure 2: RM102 Pin Out Schematic .......................................................................................17 Figure 3: RM102 Pin Out Location – Bottom View ................................................................23 Figure 4: Video Port Connection for 16/8 Bit Modes ..............................................................36 Figure 5: Video Port Timing For CBLANK = '1'.....................................................................37 Figure 6: Video Port Timing For CBLANK = '0'.....................................................................37 Figure 7: INTERLACE_MODE and FIELD Generation Circuitry .........................................40 Figure 8: Graphics Port Interface - Data Flow Block Diagram................................................41 Figure 9: Graphics Port Active Region Parameters..................................................................42 Figure 10: CLAMP Timing ......................................................................................................43 Figure 11: Graphics Port Connection Examples ......................................................................44 Figure 12: Display Port Timing-Free Run Mode, Interlaced Display, VSYNC_OFFSET=0..48 Figure 13: SDRAM Connection Diagram with 64 Bit Wide Frame Buffer.............................51 Figure 14: SDRAM Connection Diagram with 80 Bit Wide Frame Buffer.............................51 Figure 15: Shadow Register Structure......................................................................................53 Figure 16: Typical Application System....................................................................................55 Figure 17: SMD Reflow Profile ...............................................................................................77 Tables Table 1: RM102 Functional Ball Table....................................................................................24 Table 2: RM102 Functional Ball Table (Continued) ...............................................................25 Table 3: RM102 - Power and Ground Ball Table ....................................................................25 Table 4: Graphics Port Interface - Data Flow Modes Control .................................................41 Table 5: Display Port Lock Modes and Display Control Sources............................................46 Table 6: Examples of Suitable SDRAM Parts for Frame Buffer .............................................49 Table 7: JTAG Test Instructions ..............................................................................................54


Contents Rembrandt-102 Data Sheet

Blank Page


Rembrandt-102 Data Sheet RM102 Overview

1 RM102 Overview

1.1 Description Rembrandt-102 is an innovative digital display controller on a single chip designed for projection systems, flat panel displays, TVs, LCD monitors and emerging digital display applications. The controller enables video and computer graphics inputs and displays in virtually any format and resolution.

1.2 Features

Video Input Port • Standard YUV 4:2:2 input from any video or

DVD decoder, supporting PAL, NTSC, or SECAM video formats.

• Glueless interface: 16 bits, 8 bits or ITU-R BT.656.

• Interlaced or progressive inputs.

Graphics and HDTV Input Port • Glueless interface to most graphics grade

ADCs. • Interface to DVI/TMDS, LVDS receivers and

HDTV decoders. • Pixel resolution of up to WUXGA 1920x1200,

and all HDTV formats up to 1080P. • Support for RGB, YUV 4:4:4 or YUV 4:2:2

input formats. • Single and dual pixel input modes (24/48 bits). • Input pixel rate up to 150 Mpixel/s in single

pixel mode, 280 Mpixel/s in dual pixel mode. • Progressive or interlace inputs. • Horizontal interlace mode.

Display Output Port • Glueless interface to digital display devices,

DACs, DVI /TMDS and LVDS transmitters. • Display resolutions up to WUXGA (1920x1200)

at 60 Hz, and SXGA (1280x1024) at 85 Hz. • RGB or YUV 4:4:4 output formats. • Single and dual output pixel modes

(24/48 bits). • Output pixel rate up to 150 Mpixel/s in single

pixel mode and 220 Mpixel/s in dual pixel mode.

• Built in programmable display controller. • Dithering logic for 5, 6 or 8 bits for each

color component. • Lock modes to external signals - Vsync,

Hsync and/or pixel enable signals. • Progressive or interlace output modes. • Separate or composite sync outputs.

Scaling and Zooming • Downscaling to 1/16 in graphics and

1/32 in video. Upscaling to x128 for both video and graphics.

• Independent scale factors in vertical and horizontal directions.

• Horizontal and vertical non-linear scaling for aspect ratio conversion.

• Powerful “continuous” zoom and pan for video and graphics.

Video De-interlacing • High quality video de-interlacer, incorporating

an automatic motion adaptive algorithm.

Color and Luminance Control • Independent control for video and graphics. • Brightness, contrast, hue and saturation

control. • Independent saturation control per color

component. • Programmable filters for sharpness control. • 10 bit loadable gamma correction table. • Programmable luminance and chrominance

lookup tables (YUV LUTs). • Color transition improvement (CTI). • Luma transition improvement (LTI).

Frame Rate Conversion • Non-tearing frame rate conversion supporting

independent input and output frame rates.

On Screen Display (OSD) • Integrated processor for two OSD windows, up

to full screen size. • Support for 240 colors and programmable

transparency masks through a loadable palette. • Tool for advanced animation effects.

Picture In Picture (PIP) • Graphics window on video background, video

window on graphics background. • Separate graphics and video windows, with

arbitrary size and position.

Measurement Unit • Measuring graphics port input parameters for

automatic sampling and detection control. • Measured parameters: Hsync, Vsync, active

region, min/max, interlaced/progressive. • Measuring video port luminance min/max for

automatic gain control, and active region for letter-box detection.


RM102 Overview Rembrandt-102 Data Sheet

Special Functions • Keystone correction, providing high-quality

digital image reshaping for projectors. • 3D display modes for video and graphics. • Chip concatenation mode for multi panel

display.

Frame Buffer Interface • Glueless connection to external SDRAM chips,

1 M x 16 bit, 4 M x 16 bit, 1 M x 32 bit or 2 M x 32 bit each

• 16, 48, 64 or 80 bit data width, at 125 MHz clock rate for high memory bandwidth.

• Unified memory architecture - storing video, graphics and OSD in a single controlled memory.

• Memory freeze mode for video and graphics.

CPU Interface • Standard interface to 8-bit data bus for fast

CPU access.

Development Support • Evaluation board, incorporating flexible video,

graphics and output modules. • Designer development kit, including PCCS

(PC Control Software), OSD builder, Flash Loader, hardware and software reference design documentation.

Physical • Package: 352 PBGA, 35 x 35 mm • Voltage: 1.8 V core, 3.3 V I/O, 5 V tolerant

Testing • IEEE-1149.1 (JTAG) boundary scan test port

for in-circuit testing.

1.3 Applications • Projection Systems (LCD, DLP, LCOS) • Plasma Display Panels (PDP) • LCD Monitors and TVs • Multi-Panel Displays, Video Walls

1.4 Ordering Information

Item Description Part Number RM102 Temp. Range 0 - 70°C Package PBGA352


Rembrandt-102 Data Sheet Functional Overview

2 Functional Overview

Vide

oPo

rtIn

terfa

ce

Vide

oC

TI

Vide

oD

own

Scal

er

Gra

phic

sPo

rtIn

terfa

ceC

SCG

raph

ics

CTI

Vide

oIn

Filte

r

Gra

phic

sD

own

Scal

er

Gra

phic

sFi

lter

Mea

sure

men

tU

nit

CPU

Inte

rface

Mem

ory

Con

trol

OSD

load

Inte

rnal

con

trol

bus

FIFO

SDR

AMby

pass

mod

e

Gra

phic

sU

pSc

aler

Pale

tteR

AM

OSD

sele

ct

OSD

a

OSD

b

Vide

oD

e -

inte

rlace

r

Vide

oO

utFi

lter

Vide

oU

p Sc

aler

OSD

Ove

rlay

Keys

tone

RG

BLo

okup

Tabl

eD

ither

Dis

play

Inte

rface

SDR

AMPo

rt

Vide

oPo

rt

Gra

phic

s(D

ata)

Port

CPU Po

rt

Dis

play

Port

Clo

ckG

ener

ator

mcl

k (m

emor

y cl

ock)

pclk

(pro

cess

clo

ck)

oclk

(dis

play

clo

ck)

YUV

Look

upTa

ble

CSC

&Pi

ctur

eC

ontro

l

YUV

Look

upTa

ble

CSC

&Pi

ctur

eC

ontro

l

PIP

Exte

rnal

Clo

cks

Figure 1: RM102 Internal Block Diagram


Functional Overview Rembrandt-102 Data Sheet

2.1 Functional Description RM102 is a multimedia processing system on a chip, internally comprising four major blocks:

• Video Path • Graphics Path • Output Path • Services

The Video Path, Graphics Path and Output Path blocks incorporate the pixel processing flow, with each block having its own processing units. The Services block encompasses the global services and auxiliary functions within the system as memory controller, CPU interface, measurement unit and clock generators.

2.2 Video Path The Video Path processes the incoming interlaced or progressive video input and generates the required video image. This path comprises the following modules:

• Video Port Interface - A glueless interface to most video decoders, DVD decoder and external de-interlacer, such as the Oplus Matisse-1A. The Video Port interface supports standard interlaced component input (YUV or YCbCr) in 4:2:2 format, in standard 16 or 8 bit format, as well as BT.656 8 bit format. Progressive standard resolution video is also supported in 16 or 8 bit format. Video port input is able to handle inputs up to 768 pixels/line, with pixel clock (VCLK) up to 75 MHz.

• Video Down and Up Scalers - Two independent scalers can be used to convert the resolution of the incoming video fields or frames to the required video displayed image. The video down-scaler can be used to scale down the incoming fields or frames. The video up-scaler can be used to up-scale the de-interlaced frame as well as the input frame. In each scaler, horizontal and vertical scale factors are independently controlled. Scale factors down to 1/32 in the down-scaler and up to x128 in the up-scaler can be programmed. The up-scaler can also perform vertical downscaling to a scale factor of 1/2. For interlaced displays the up-scaler generates the required odd and even fields. Output resolutions of up to WUXGA and HDTV1080P are supported in addition to other standard and non-standard resolutions. Both scalers support a non-linear (NL) scaling mechanism for aspect ratio conversion.

• Video De-interlacer - The video de-interlacer uses an automatic motion adaptive temporal/spatial algorithm to maximize image quality in dynamic and static areas, using per pixel motion/static detection. This algorithm uses two video fields read from external memory for its adaptive algorithms. The de-interlacer can also be configured to work in spatial or temporal modes.

• Video Filters - Up to two programmable 3x3 filters can be used for the scaling process and for user sharpness control. The video-in filter is located just before the down scaler and is usually used to optimize scaler operation according to scale factor. The video-out filter is located just before the up-scaler, and is usually used for image sharpness control. The center tap coefficient can be programmed with a coefficient range of -8.0 to +7.984. The other eight coefficients can be programmed with a coefficient range of -2.0 to +1.984. The filters have overshoot limiter control to enhance sharpness, improve luminance transients (LTI) and per pixel filter bypass control to reduce noise in high pass filters.

• Color Transition Improvement (CTI) - The CTI module can be used to improve limited bandwidth input chrominance transitions, reducing color transition artifacts. This module is positioned just after the video interface module.

• YUV Lookup Table - Three loadable 256x8 tables, one for each component (Y, U and V) for luminance and chrominance control. Non-linear contrast control can be achieved using the Y table. Independent saturation control of Red, Green, Blue and Yellow color components can be achieved using the U and V tables.

• Color Space Converter (CSC) and Picture Control - A programmable CSC matrix is used for YUV to RGB color space conversion. In addition, a programmable bias can be added to the Y component. This matrix and the bias can also be used for linear picture controls, such as brightness, contrast, hue and saturation, as well as independent gain control on each output color component.



2.3 Graphics Path The Graphics Path processes the incoming graphics port input image, generating the required graphics image display. The path comprises the following modules:

• Graphics Port Interface - This module provides a glueless interface to most graphics grade ADCs, TMDS, and LVDS receivers, HDTV decoders and video decoders. The interface logic is very flexible and suitable for many types of external sampling devices and modes of operation. Pixel sampling control is determined internally or externally. Internal pixel sampling control is accomplished by controlling the external ADC sampling rate (using the external PLL division factor) and internal active region parameters, using measurement results of the incoming control and data signals. External pixel sampling control is accomplished by external devices (for example, TMDS receiver), signaling the active pixel region and providing a correctly synchronized sampling clock. The graphics interface can handle interlaced and progressive inputs up to 1920 pixels per line, as well as supporting sampling of high-resolution inputs at a half-pixel rate, using low cost ADCs - usually referred to as horizontal interlaced (H-interlace) mode. The Graphics Port Interface can accept one or two pixels per clock for up to 150 Mpixel/sec in single pixel mode, and up to 280 Mpixel/sec in dual pixel mode. The graphics port can accept any one of the following inputs: 24/48 bits RGB, 24/48 bits YUV 4:4:4 or 16 bit YUV 4:2:2.

• Graphics Down and Up Scalers - Two independent scalers are used to obtain resolution conversion of the incoming graphics frames to the required graphics display. A graphics down-scaler scales down the incoming frames before storage in the external frame buffer. A graphics up-scaler upscales the frames read from the frame buffer or from internal FIFO in SDRAM bypass mode when frame rate conversion is not required. Horizontal and vertical scale factors of each scaler are independently controlled. The scale factor ranges from 1/16 for the down-scaler and up to x128 for the up-scaler. The up-scaler can also perform vertical downscaling to a scale factor of 1/2. For interlaced displays the up-scaler generates the required odd and even fields. Input and output resolutions of up to WUXGA and HDTV1080P are supported in addition to other standard and non-standard resolutions. As with the video scalers, both up and down scalers support programmable non-linear scaling mechanism for aspect ratio conversion. Both scalers can handle interlaced inputs, and generate progressive outputs using spatial de-interlacing.

• Graphics Filter - A programmable 3x3 filter located just before the down-scaler can be used to optimize scaler operation as well as provide user sharpness control. The center tap coefficient can be programmed with a coefficient range of -8.0 to +7.984. The other eight coefficients can be programmed with a coefficient range of -2.0 to +1.984. The filter’s overshoot limiter control enhances sharpness, improves luminance transients (LTI) and per pixel filter bypass control to limit noise in high pass mode.

• Color Transition Improvement (CTI) - The CTI module can be used to improve input chrominance transitions, reducing color transition artifacts. This is usually required for standard resolution video input. This module is positioned just after the RGB to YUV CSC module.

• YUV Lookup Table - Three loadable 256x8 tables, one for each component (Y, U and V) for luminance and chrominance control. Non-linear contrast control can be achieved using the Y table. Independent saturation control of Red, Green, Blue and Yellow color components can be achieved using the U and V tables.

• Color Space Converter (CSC) and Picture Control - A programmable CSC matrix is used for YUV to RGB color space conversion. In addition, a programmable bias can be added to the Y component. This matrix and the bias can also be used for linear picture controls, such as brightness, contrast, hue and saturation, as well as independent gain control on each output color component.

2.4 Output Path The Output Path combines images from video and graphics paths with two OSD overlays for interfacing to various digital displays. This path comprises the following modules: • PIP (Picture In Picture) - The PIP unit combines both video and graphics windows superimposed on a

programmable background to form a single displayed image. The size and positioning of the video and graphics windows within the active display area are programmable.



• OSD - Two independent OSDs can overlay the image originating from the PIP unit. These OSDs are selected from up to four stored OSDs in the external SDRAM frame buffer memory. Each OSD eight bit pixel read from the memory passes through a 24-bit palette RAM loaded for color and masking effects. Up to 240 different colors (from a palette of 16.7 M colors) and up to 15 masking effects can be obtained, as well as full transparency effect. Each OSD pixel can be displayed without any zoom, or can be duplicated in horizontal and/or vertical directions before overlaying by a factor of 2 or 4. The external CPU loads OSD pixels to external memory in bit map format. The user can then select to display the entire OSD or only a selected portion (OSD window). OSD displayed size is programmable, with a maximum size of 1920 pixels by 1200 lines.

• Keystone - The keystone unit provides high quality vertical keystone correction for projection systems. A correction range of ±12 degrees covers most projector positioning angles in floor or ceiling modes.

• RGB Lookup Table (Gamma Table) - Three 256x10 bit lookup tables, one for each red, green and blue color component, can be loaded and used for gamma correction and white balance. A 10-bit table enables more colors to be displayed while still preserving the gamma response. Later, these 10 bit pixels are dithered down to 8 bits or less in the dither block.

• Dither - This block provides the required bits per pixel for the display device. Each 10 bit component from the gamma table can be reduced to 8, 6 or 5 bits, using a two dimensional error diffusion algorithm, calibrated for the best visual response.

• Display Interface - This module provides a glueless interface to most digital display devices. All control signals are locally generated in free run mode, or externally supplied, depending on the selected lock mode. Display vertical sync (OP_VSYNC) can be locked to either the video or graphics input vertical syncs, to the delayed video or graphics vertical syncs, or to externally supplied vertical sync. Display horizontal sync (OP_HSYNC) and pixel enable signals (OP_ENABLE) can be locked to externally supplied signals. Display pixel clock (OCLK_OUT) is generated locally - either free run or locked to an externally supplied clock (OCLK_IN).

All control signal timing (Hsync and Vsync polarity, pulse width and cycle, Hsync to Vsync delay), and active region size and position are fully programmable. Separate Hsync and Vsync, or composite sync can be generated. Pixels emerge at the display port either in single pixel or in dual pixel per clock. Maximum display clock rate is 150 MHz in single pixel mode and 110 MHz in dual pixel mode, enabling peak pixel rate of up to 150 Mpixel/sec or 220 Mpixel/sec respectively. This module supports interlaced display with a field indicator signal (OP_FIELD), and with Hsync to Vsync relationship control. The display interface also generates a three dimensional control signal (OP_FIELD_3D), driving an external infrared emitter that can control the shutter of LCD glasses.

2.5 Services • Memory Controller - Frame rate conversion is obtained through an external frame buffer used for storage

of video and graphics fields or frames and OSD frames. The memory controller includes an arbiter serving requests for memory transactions and SDRAM interface to external memory devices. Memory data word size options are 16, 48, 64 and 80 bits, where 16 bits is sufficient for video only applications, 64 bits can be used for most applications, and 80 bits is required only for high rate video and graphics applications. Any standard SDRAM device (16/32/64 Mbit) rated for 125 MHz clock with 6 ns maximum access time can be used. The memory controller supports read access to the stored frames in two modes: full frame access mode and memory window access mode. The memory window access mode provides zoom and pan functions in video, graphics and OSD display windows. External memory is organized in programmable size sections. Three video sections, two graphics sections (each divided to two sub-sections) and four OSD sections are provided. For the graphics path, the memory controller can implement temporal de-interlacing of computer originated interlaced images by storing both fields in one memory section.

• Host Interface - RM102 can be controlled by any micro controller through a generic 8-bit data bus. All functions within the chip, each function with its own set of registers, are programmable. Scale, zoom, pan and picture control functions are controlled through shadow registers for artifact-free display during parameter changes.



• Measurement Unit - The measurement unit receives the graphics port input sync signals and pixel data, enabling the software to auto-detect the input data format, and to adjust the ADC sampling rate and PLL phase. In addition, the measurement unit receives video port luminance (Y) for gain control. The unit can measure:

• External horizontal sync and vertical sync timing and polarity. • Input active region size and position within a programmable area of interest. • Minimum and maximum luminance and RGB component values within the selected area of interest.

The measurement unit also provides for interlace detection and field indicator reconstruction from the incoming sync signals.

• Clock Generators - RM102 generates all clocks needed for the memory interface, internal pixel processing and display interface (mclk, pclk and oclk respectively) using three internal PLLs. All clock frequencies are fully programmable.



Blank Page


Rembrandt-102 Data Sheet Functional Signal Definition

3 Functional Signal Definition

3.1 Pin Out Schematic

V_IN (15:0)

V_VSYNC

V_HSYNC

V_FIELD

V_ACTIVE

V_VALID

VCLK

D_INA (23:0)D_INB (23:0)D_VSYNCD_HSYNC

D_FIELDD_ACTIVED_VALIDDIN_CLK

GP0

GP1

D_CSYNC

AD (7:0)

DB (7:0)

RD_N

WR_N

CS_N

IRQ

RST_N

MPLL_CLK_IN

PPLL_CLK_IN

OCLK_IN

TEST

PPLL_DISABLE

RM102

MEM_A (10:0)

MEM_A11/MEM_BS1

MEM_BS0

MEM_CAS_N

MEM_RAS_N

MEM_CS_N

MEM_WE_N

MEM_DQM_L

MEM_DQM_U

MEM_DQ (15:0)

MEM_DQ (47:16)

MEM_DQ (79:48)

MCLK_OUT

MCLK_OUT_B

MCLK_IN

OP_A (23:0)

OP_B (23:0)

OP_ENABLE

OP_FIELD

OP_FIELD_3D

OP_HSYNC

OP_VSYNC

OCLK_OUT

INVCOAST/MCONF1CLAMP/MCONF0

TDO

TDI

TMS

TCLK

NTRST

Video Input Port

Misc

General Purpose

JTAG Interface

Display Port

SDRAM Port

PLL Inputs

CPU Port

Graphics Input Port

Figure 2: RM102 Pin Out Schematic


Functional Signal Definition Rembrandt-102 Data Sheet

3.2 Pin Descriptions Notations used in the following tables are:

I Input pin O Output pin I/O Pin used for Input and Output PD Internally pulled down PU Internally pulled up

All Inputs and I/O pins are 5 V tolerant, and use Schmitt trigger input threshold scheme.

3.2.1 Graphics Input Port Name No. I/O Type Description

DIN_CLK B8 I PD Graphics port input clock. Graphics port control and data signals D_INA, D_INB, D_HSYNC, D_VALID and D_ACTIVE are sampled on the active transition of this signal. The active clock edge (rising / falling) is programmable.

D_INA[23..16] D_INA[15..8] D_INA[7..0]

G4, F2, E1, E3, E4, E2, D1, D3 D2, C1, C2, B1, A3, C4, B3, C5 A4, D5, B4, C6, A5, B5, C7, A6

I PD Primary data input port. Input pixel data in single pixel mode or even (left) pixel in dual pixel mode. When Y_ON_GREEN = '0’ (RM1A compatible mode) : D_INA[23..16] = RED[7..0] in RGB mode or Y[7..0] in YUV modes. D_INA[15..8] = GREEN[7..0] in RGB mode or U[7..0] in YUV 4 :4 :4 mode or UV[7..0] in YUV 4 :2 :2 single pixel mode. D_INA[7..0] = BLUE[7..0] in RGB mode or V[7..0] in YUV 4 :4 :4. When Y_ON_GREEN = ‘1’ (recommended): D_INA[23..16] = RED[7..0] in RGB mode or V[7..0] in YUV 4 :4 :4. D_INA[15..8] = GREEN[7..0] in RGB mode or Y[7..0] in YUV modes. D_INA[7..0] = BLUE [7..0] in RGB mode or U[7..0] in YUV 4 :4 :4 mode or UV[7..0] in YUV 4 :2 :2 single pixel mode.

D_INB[23..16] D_INB[15..8] D_INB[7..0]

P4, P2, M3, N1, N2, L3, M1, M2 L1, K3, L2, K1, J3, K2, J1, J2 H3, H1, H2, G3, G1, G2, F1, F3

I PD Secondary data input port, used for odd (right) pixel in dual pixel mode. Can be left open in single pixel mode : When Y_ON_GREEN = '0’ (RM1A compatible mode) : D_INB[23..16] = RED[7..0] in RGB mode or Y[7..0] in YUV 4:4:4 mode. D_INB[15..8] = GREEN[7..0] in RGB mode or U[7..0] in YUV 4 :4 :4 mode. D_INB[7..0] = BLUE [7..0] in RGB mode or V[7..0] in YUV 4 :4 :4. When Y_ON_GREEN = ‘1’ (recommended): D_INB[23..16] = RED[7..0] in RGB mode or V[7..0] in YUV 4 :4 :4. D_INB[15..8] = GREEN[7..0] in RGB mode or Y[7..0] in YUV 4:4:4 mode. D_INB[7..0] = BLUE [7..0] in RGB mode or U[7..0] in YUV 4 :4 :4 mode.

D_ACTIVE C9 I PD Active line of pixels at the data input port, when EXT_ACTIVE = ‘1’. The polarity is programmable.

D_VALID

A8 I PD Clock qualifier signal when DIN_VALID_ENABLE = ‘1’. Input pixel (D_INA and D_INB) is sampled on DIN_CLK active edge only when this clock qualifier is '1'. The polarity is programmable.

D_FIELD B7 I PD Input field indicator, when input is interlaced. ‘0’ indicates odd input field. ‘1’ indicates even input field. The polarity is programmable.



Name No. I/O Type Description D_VSYNC A9 I PD Vertical sync signal indicating start of a frame or field at the

data input port. The polarity is programmable.

D_HSYNC C10 I PD Horizontal sync signal indicating start of a line at the data input port. It should be synchronized to DIN_CLK input. This input is also used for field extraction of interlaced inputs by the measurement unit when RAW_HSYNC_MSR_SELECT = '0'.

D_CSYNC

B9 I PD Composite sync input used by the measurement unit for HV_Parameters measurements when: RAW_HSYNC_MSR_SELECT = ‘1’. Usually connected to ADC Sync on Green output.

CLAMP / MCONF0

A10 I/O PD Dual function pin: Output during normal operation: CLAMP – Programmable pulse to the ADC generated every line start, if enabled. Polarity controlled. Input during power up reset: MCONF0 – Sampled during power up sequence and can be read at STATUS register. Connect external pull up resistor for logic ‘1’ or leave open for logic ‘0’.

COAST / MCONF1

C12 I/O PD Dual function pin: Output during normal operation: DPLL_COAST – Output to the PLL, generated during D_VSYNC pulse period, if enabled. Polarity controlled. Input during power up reset: MCONF1 – Sampled during power up sequence and can be read at STATUS register. Connect external pull up resistor for logic ‘1’ or leave open for logic ‘0’.

INV D10 O PD Signals the ADC to invert its sampling clock. In horizontal interlace mode (HINTERLACE_MODE = ‘1’) this signal is toggled every input frame. When HINTERLACE_MODE = ‘0’, INV pin output is fixed at logic level defined by INV_SET control bit. Output polarity is programmable.

3.2.2 Video Input Port

Name No. I/O Type Description VCLK W1 I PD Video input port clock used to sample the pixel data when

V_ACTIVE and V_VALID are active. Sampling clock edge (rising / falling) is programmable.

V_IN[15..8] W2, V1, U3, V2, U1, T3, U2, R4

I PD Video data input, Y[7..0] in 16 bit format or YUV[7..0] in 8 bit format.

V_IN[7..0] T1, R3, T2, R1, P3, R2, N3, P1

I PD Video data input, UV[7..0] in 16 bit format. Can be left open in 8 bit format.

V_VSYNC AA2 I PD Vertical sync input indicating start of a video field or frame. The polarity is programmable.

V_HSYNC W3 I PD Horizontal sync input indicating start of a video line. The polarity is programmable.

V_ACTIVE Y2 I PD Indicates active video line when CBLANK = '1', or vertical active lines when CBLANK = '0'. The polarity is programmable.

V_VALID V3 I PD VCLK qualifier indicating valid pixels during active video lines when CBLANK = '1', or horizontal active pixels when CBLANK = '0'. The polarity is programmable.

V_FIELD Y1 I PD Odd/Even field indicator: ‘0’ = Odd, ‘1’ = Even. Odd field is defined as the upper field, while even field is defined as lower field. The polarity is programmable.



3.2.3 Display Port

Name No. I/O Type Description OCLK_OUT AE9 O Display output clock used by the display to sample pixel data

and control signals. External sampling clock edge (rising/falling) is programmable, as well as enabling zero hold time mode (OP_ZERO_HOLD = '1'). Clock edge causing output change is programmable.

OCLK_IN AD6 I PLL input clock, used as an input to OCLK PLL. The clock source driving this input should be stable before RST_N goes inactive. OCLK PLL frequency is programmable by setting PLL division factor. When the division factor is set to 1, OCLK_IN can be used to sample external input control signals (OP_HSYNC, OP_VSYNC and OP_ENABLE) according to display lock mode. The sampling edge polarity is programmable.

OP_A[23..16] OP_A[15..8] OP_A[7..0]

AF9, AE10, AD9, AF10, AE11, AD10, AF11, AE12 AF12, AD11, AE13, AC12, AF13, AD12, AE14, AC14 AF14, AD13, AE15, AD14, AF15, AE16, AD15, AF16

O Display primary output port, used in single pixel mode, or in dual pixel mode for the even (left) pixel. When Y_ON_GREEN = '0' (RM1A compatible mode): OP_A[23..16] = RED[7..0] in RGB mode or Y[7..0] in YUV

mode. OP_A[15..8] = GREEN[7..0] in RGB mode or U[7..0] in

YUV mode. OP_A[7..0] = BLUE[7..0] in RGB mode or V[7..0] in YUV

mode. When Y_ON_GREEN = '1' (recommended): OP_A[23..16] = RED[7..0] in RGB mode or V[7..0] in YUV

mode. OP_A[15..8] = GREEN[7..0] in RGB mode or Y[7..0] in

YUV mode. OP_A[7..0] = BLUE[7..0] in RGB mode or U[7..0] in YUV

mode.

OP_B[23..16] OP_B[15..8] OP_B[7..0]

AC15, AE17, AD16, AF17, AC17, AE18, AD17, AF18 AE19, AF19, AD18, AE20, AF20, AD19, AE21, AF21 AF23, AD22, AE24, AD23, AF24, AE26, AD25, AD26

O Display secondary output port, used for odd (right) pixel in dual pixel mode. In single pixel mode outputs are driven low. When OP_SKEW = '1', OP_B and OP_A are driven with 1.2 ns skew, to reduce current. When Y_ON_GREEN = '0' (RM1A compatible mode): OP_A[23..16] = RED[7..0] in RGB mode or Y[7..0] in YUV

mode. OP_A[15..8] = GREEN[7..0] in RGB mode or U[7..0] in

YUV mode. OP_A[7..0] = BLUE[7..0] in RGB mode or V[7..0] in YUV

mode. When Y_ON_GREEN = '1' (recommended): OP_A[23..16] = RED[7..0] in RGB mode or V[7..0] in YUV

mode. OP_A[15..8] = GREEN[7..0] in RGB mode or Y[7..0] in

YUV mode. OP_A[7..0] = BLUE[7..0] in RGB mode or U[7..0] in YUV

mode.

OP_VSYNC AC5 I/O PD Vertical sync, indicating start of display frame or field. Can be configured as output or input, according to the display-locking mode. After reset Initialized to input. The polarity is programmable for input and output modes.

OP_HSYNC AD5 I/O PD Horizontal sync, indicating start of display line. Can be configured as output or input, according to the display-locking mode. After reset Initialized to input. Signal can be programmed as composite sync when COMP_SYNC = '1'. The polarity is programmable, for input and output modes.



Name No. I/O Type Description OP_EANBLE AF5 I/O PD Data enable period indicating active pixel data at OP_A and

OP_B ports. Can be configured as output or input, according to the display-locking mode. After reset initialized to input. The polarity is programmable for input and output modes.

OP_FIELD AE6 I/O PD Indicates field in or out for interlaced display. Can be configured as input or output. Output (OP_FIELD_SOURCE = '0'): OP_FIELD – Output to display. Input (OP_FIELD_SOURCE = ‘1’ and OP_FIELD_SIGNAL = ‘1’): OP_FIELD – Input from external source. Internally OP_FIELD is ‘0’ for odd field and ‘1’ for even field. Polarity is programmable for input and output modes.

OP_FIELD_3D AC7 I/O PD Indicates left field or right field in case the RM102 is in 3D mode. This signal is used to drive an external device (such as an IR emitter) to control the shutter of LCD glasses. Internally OP_FIELD_3D is ‘0’ for left field and ‘1’ for right field. Polarity is programmable for input and output modes.

3.2.4 SDRAM Port

Name No. I/O Type Description MCLK_OUT B12 O SDRAM clock generated by MCLK PLL. CKE (Clock Enable)

inputs of the SDRAM chips should be connected to VDD_IO.

MCLK_OUT_B B11 O Buffered MCLK_OUT, should be connected externally to MCLK_IN.

MCLK_IN A11 I PD Feedback clock. Must be connected to MCLK_OUT_B.

MEM_DQ[79..48]

MEM_DQ[47..16] MEM_DQ[15..0]

M25, P24, N26, N23, N25, R24, P26, R23, P25, T24, R26, R25, T26, U24, T25, U26, V24, U25, V26, V25, W24, W26, W25, Y24, Y26, Y25, AA26, AA24, Y23, AA25, AB26, AB24 B17, A18, B18, C19, A19, B19, C20, A20, B20, A21, C21, D20, B21, A22, C22, D22, B22, C23, A23, B23, A24, B24, A25, C26, D24, C25, E24, D26, F25, H24, G26, G25 J24, H26, H25, J26, K24, J25, K23, K26, L24, K25, M23, L26, M24, L25, M26, N24

I/O PD SDRAM data bus. MEM_DQ[15..0] are used for 16 bit access. MEM_DQ[47..0] are used for 48 bit access. MEM_DQ[79..16] are used for 64 bit access. MEM_DQ[79..0] are used for 80 bit access. Unused pins can be left open.

MEM_A[10..0] A17, B16, C17, A16, B15, A15, C16, B14, D15, A14, C15

O

SDRAM address bus.

MEM_A11 / MEM_BS1

B6 O SDRAM address line A11, used for 2Mx16 two bank SDRAM devices, or second bank select bit for four bank SDRAM devices. Active when SDRAM_A11_ENABLE = '1'. Forced to '0' when SDRAM_A11_ENABLE = '0'.

MEM_BS0 C18 O SDRAM bank select.

MEM_CS_N C13 O SDRAM chip select, active low.

MEM_RAS_N A12 O SDRAM row address strobe, active low.

MEM_CAS_N C14 O SDRAM column address strobe, active low.

MEM_WE_N A13 O SDRAM write enable, active low.

MEM_DQM_L D13 O SDRAM lower byte data qualifier.

MEM_DQM_U B13 O SDRAM upper byte data qualifier (internally connected to MEM_DQM_L).



3.2.5 CPU Port

Name No. I/O Type Description DB[7..0] AE5,AF4, AD4, AE4,

AF3, AE3, AF2, AD1 I/O Bi-directional data bus.

AD[7..0] AC3, AD2, AB3, AC1, AB4, AC2, AA3, AB1

I Address bus, used to select (for write or read) internal register, register file or table.

CS_N AA1 I PU Chip select, active low. Enable read or write commands.

WR_N AB2 I PU Write command, active low.

RD_N Y3 I PU Read command, active low.

IRQ AD8 O PD Interrupt request output. Active polarity is programmable. External pull up resistor should not be used.

3.2.6 MISC

Name No. I/O Type Description RST_N AF8 I PU General chip reset input, active low. Should be activated after

power up to initialize the device. Reset is internally extended up to 1 ms after RST_N is deactivated, during that time CPU access is ignored.

GP0 A7 I/O General purpose I/O pin: Output when GP0_CONFIG = ‘1’ Input when GP0_CONFIG = ‘0’ Rising edge at GP0 can cause an interrupt if it is not masked.

GP1 C8 I/O General purpose I/O pin: Output when GP1_CONFIG = ‘1’ Input when GP1_CONFIG = ‘0’

PPLL_DISABLE D12 I PD During power up reset this pin is sampled to control PCLK PLL operation. Connect an external 1K pull up resistor for logic ‘1’. Leave open for logic ‘0’. Pin status can be read at STATUS register. When ‘0’: PCLK PLL is enabled. When ‘1’: PCLK PLL is disabled and PCLK (processing clock) is internally connected to MCLK (memory clock).

TEST F26 I PD Should be connected to GND.

3.2.7 PLL Inputs

Name No. I/O Type Description MPLL_CLK_IN G24 I

MCLK PLL input, in range of 25-33 MHz. The clock source driving this input should be stable before RST_N goes inactive.

PPLL_CLK_IN AD20 I PCLK PLL input, in range of 25-33 MHz. Connect to GND if PPLL_DISABLE = '1’

3.2.8 JTAG Port Interface

Name No. I/O Type Description TCLK AC25 I PU JTAG port clock input.

NTRST AB23 I PD JTAG port reset, active low.

TMS AB25 I PU JTAG port mode select.

TDI AC24 I PU JTAG port data input.

TDO AC26 O PU JTAG port data output.



3.2.9 Pin Out Location

Bottom

View

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

1234567891011121314151617181920212223242526

1234567891011121314151617181920212223242526

GND

VDD_CORE (1.8V)

VDD_IO (3.3V)

PLL_AGND

PLL_AVCC

N.C.

VIDEO PORT

DISPLAY PORT

SDRAM PORT

GRAPHICS PORT

CPU PORT

JTAG PORT

Figure 3: RM102 Pin Out Location – Bottom View



3.2.10 Functional Ball Table

Ball # Pin Name Ball # Pin Name Ball # Pin Name G4 D_INA[23] A10 CLAMP / MCONF0 AF9 OP_A[23] F2 D_INA[22] D10 INV AE10 OP_A[22] E1 D_INA[21] W2 V_IN[15] AD9 OP_A[21] E3 D_INA[20] V1 V_IN[14] AF10 OP_A[20] E4 D_INA[19] U3 V_IN[13] AE11 OP_A[19] E2 D_INA[18] V2 V_IN[12] AD10 OP_A[18] D1 D_INA[17] U1 V_IN[11] AF11 OP_A[17] D3 D_INA[16] T3 V_IN[10] AE12 OP_A[16] D2 D_INA[15] U2 V_IN[9] AF12 OP_A[15] C1 D_INA[14] R4 V_IN[8] AD11 OP_A[14] C2 D_INA[13] T1 V_IN[7] AE13 OP_A[13] B1 D_INA[12] R3 V_IN[6] AC12 OP_A[12] A3 D_INA[11] T2 V_IN[5] AF13 OP_A[11] C4 D_INA[10] R1 V_IN[4] AD12 OP_A[10] B3 D_INA[9] P3 V_IN[3] AE14 OP_A[9] C5 D_INA[8] R2 V_IN[2] AC14 OP_A[8] A4 D_INA[7] N3 V_IN[1] AF14 OP_A[7] D5 D_INA[6] P1 V_IN[0] AD13 OP_A[6] B4 D_INA[5] W1 VCLK AE15 OP_A[5] C6 D_INA[4] V3 V_VALID AD14 OP_A[4] A5 D_INA[3] Y2 V_ACTIVE AF15 OP_A[3] B5 D_INA[2] Y1 V_FIELD AE16 OP_A[2] C7 D_INA[1] W3 V_HSYNC AD15 OP_A[1] A6 D_INA[0] AA2 V_VSYNC AF16 OP_A[0] P4 D_INB[23] AC3 AD[7] AC15 OP_B[23] P2 D_INB[22] AD2 AD[6] AE17 OP_B[22] M3 D_INB[21] AB3 AD[5] AD16 OP_B[21] N1 D_INB[20] AC1 AD[4] AF17 OP_B[20] N2 D_INB[19] AB4 AD[3] AC17 OP_B[19] L3 D_INB[18] AC2 AD[2] AE18 OP_B[18] M1 D_INB[17] AA3 AD[1] AD17 OP_B[17] M2 D_INB[16] AB1 AD[0] AF18 OP_B[16] L1 D_INB[15] AE5 DB[7] AE19 OP_B[15] K3 D_INB[14] AF4 DB[6] AF19 OP_B[14] L2 D_INB[13] AD4 DB[5] AD18 OP_B[13] K1 D_INB[12] AE4 DB[4] AE20 OP_B[12] J3 D_INB[11] AF3 DB[3] AF20 OP_B[11] K2 D_INB[10] AE3 DB[2] AD19 OP_B[10] J1 D_INB[9] AF2 DB[1] AE21 OP_B[9] J2 D_INB[8] AD1 DB[0] AF21 OP_B[8] H3 D_INB[7] AA1 CS_N AF23 OP_B[7] H1 D_INB[6] Y3 RD_N AD22 OP_B[6] H2 D_INB[5] AB2 WR_N AE24 OP_B[5] G3 D_INB[4] AD8 IRQ AD23 OP_B[4] G1 D_INB[3] AC24 TDI AF24 OP_B[3] G2 D_INB[2] AC25 TCLK AE26 OP_B[2] F1 D_INB[1] AC26 TDO AD25 OP_B[1] F3 D_INB[0] AB25 TMS AD26 OP_B[0] C10 D_HSYNC AB23 NTRST AC5 OP_VSYNC A9 D_VSYNC F26 TEST AD5 OP_HSYNC B8 DIN_CLK D12 PPLL_DISABLE AF5 OP_ENABLE C12 COAST / MCONF1 A7 GP0 AE6 OP_FIELD B9 D_CSYNC C8 GP1 AC7 OP_FIELD_3D B7 D_FIELD A8 D_VALID C9 D_ACTIVE

Table 1: RM102 Functional Ball Table



Ball # Pin Name Ball # Pin Name Ball # Pin Name M25 MEM_DQ[79] B20 MEM_DQ[39] C18 MEM_BS0 P24 MEM_DQ[78] A21 MEM_DQ[38] B6 MEM_A11 / MEM_BS1 N26 MEM_DQ[77] C21 MEM_DQ[37] A17 MEM_A[10] N23 MEM_DQ[76] D20 MEM_DQ[36] B16 MEM_A[9] N25 MEM_DQ[75] B21 MEM_DQ[35] C17 MEM_A[8] R24 MEM_DQ[74] A22 MEM_DQ[34] A16 MEM_A[7] P26 MEM_DQ[73] C22 MEM_DQ[33] B15 MEM_A[6] R23 MEM_DQ[72] D22 MEM_DQ[32] A15 MEM_A[5] P25 MEM_DQ[71] B22 MEM_DQ[31] C16 MEM_A[4] T24 MEM_DQ[70] C23 MEM_DQ[30] B14 MEM_A[3] R26 MEM_DQ[69] A23 MEM_DQ[29] D15 MEM_A[2] R25 MEM_DQ[68] B23 MEM_DQ[28] A14 MEM_A[1] T26 MEM_DQ[67] A24 MEM_DQ[27] C15 MEM_A[0] U24 MEM_DQ[66] B24 MEM_DQ[26] B13 MEM_DQM_U T25 MEM_DQ[65] A25 MEM_DQ[25] D13 MEM_DQM_L U26 MEM_DQ[64] C26 MEM_DQ[24] A13 MEM_WE_N V24 MEM_DQ[63] D24 MEM_DQ[23] C13 MEM_CS_N U25 MEM_DQ[62] C25 MEM_DQ[22] C14 MEM_CAS_N V26 MEM_DQ[61] E24 MEM_DQ[21] A12 MEM_RAS_N V25 MEM_DQ[60] D26 MEM_DQ[20] B12 MCLK_OUT W24 MEM_DQ[59] F25 MEM_DQ[19] B11 MCLK_OUT_B W26 MEM_DQ[58] H24 MEM_DQ[18] A11 MCLK_INPUT W25 MEM_DQ[57] G26 MEM_DQ[17] AD20 PPLL_CLK_IN Y24 MEM_DQ[56] G25 MEM_DQ[16] G24 MPLL_CLK_IN Y26 MEM_DQ[55] J24 MEM_DQ[15] AE9 OCLK_OUT Y25 MEM_DQ[54] H26 MEM_DQ[14] AD6 OCLK_IN AA26 MEM_DQ[53] H25 MEM_DQ[13] AF8 RST_N AA24 MEM_DQ[52] J26 MEM_DQ[12] AF7 OPLL_AGND Y23 MEM_DQ[51] K24 MEM_DQ[11] AD7 OPLL_AVCC AA25 MEM_DQ[50] J25 MEM_DQ[10] AD21 PPLL_AGND AB26 MEM_DQ[49] K23 MEM_DQ[9] AE23 PPLL_AVCC AB24 MEM_DQ[48] K26 MEM_DQ[8] F24 MPLL_AGND B17 MEM_DQ[47] L24 MEM_DQ[7] D25 MPLL_AVCC A18 MEM_DQ[46] K25 MEM_DQ[6] F4 Not connected B18 MEM_DQ[45] M23 MEM_DQ[5] L4 Not connected C19 MEM_DQ[44] L26 MEM_DQ[4] T4 Not connected A19 MEM_DQ[43] M24 MEM_DQ[3] B10 Must leave open B19 MEM_DQ[42] L25 MEM_DQ[2] C11 Must leave open C20 MEM_DQ[41] M26 MEM_DQ[1] A20 MEM_DQ[40] N24 MEM_DQ[0]

Table 2: RM102 Functional Ball Table (Continued)

3.2.11 Power and Ground Ball Table Function Ball #

GND

A1, A2, A26, B2, B25, B26, C24, C3, D14, D17, D19, D23, D4, D7, D9, E23, E26, G23, H4, J23, K4, N4, P23, U23, V4, W23, Y4, AC10, AC13, AC18, AC20, AC22, AC23, AC4, AC8, AD24, AD3, AE1, AE2, AE25, AE7, AE8, AF1, AF22, AF25, AF26

VDD CORE (1.8V) D18, D8, E25, H23, J4, V23, W4, AC19, AC9, AE22, AF6 VDD IO (3.3V) D11, D16, D21, D6, F23, L23, M4, T23, U4, AA23, AA4, AC11,

AC16, AC21, AC6

Table 3: RM102 - Power and Ground Ball Table



Blank Page


Rembrandt-102 Data Sheet Electrical Specification

4 Electrical Specification

4.1 Absolute Maximum Ratings Parameter Value

Digital core supply voltage (VDD_CORE to GND) -0.3 V to 2.0 V

Digital I/O supply voltage (VDD_IO to GND) -0.3 V to 4.0 V

Digital I/O input voltages (all input and I/O pins are 5 V tolerant) -0.3 V to 5.5 V

Digital output current IRQ pin All other output pins

14 mA 30 mA

Maximum power dissipation without heat sink, in still air 2.0 W

Operating temperature range 0 ºC to 70 ºC

Storage temperature range -40 ºC to 150 ºC

Maximum junction temperature 125 ºC

Maximum ball temperature (Soldering 10 s) 250 ºC

4.2 DC Electrical Specifications

4.2.1 Power Supplies Parameter Notes Min Typ Max Units

VDD CORE supply voltage 1.7 1.8 1.9 V VDD_IO supply voltage 3.0 3.3 3.6 V MPLL_AVCC, PPLL_AVCC, OPLL_AVCC

3.0 3.3 3.6 V

Core supply current 1 mA I/O supply current 1 mA Thermal resistance in still air, ΘJA 27 ºC/W

4.2.2 Digital Inputs Parameter Notes Min Typ Max Units

Input voltage, High VIH 1 2.0 V Input voltage, Low VIL 1 0.8 V

Input leakage current, IL 1,2 -10 ±1 10 uA Internal pull up or pull down resistance 1 40 75 190 KΩ Input capacitance 1 5.2 pF

4.2.3 Digital Outputs Parameter Notes Min Typ Max Units

Output voltage, High VOH 1,9 2.4 V Output voltage, Low VOL 1,9 0.4 V Output current, High IOH All outputs excluding IRQ IRQ pin

1,10 -5.5 -2.0

mA

Output current, Low IOL All outputs excluding IRQ IRQ pin

1,10 6.0 2.0

mA

Output capacitance 1 5.2 pF


Electrical Specification Rembrandt-102 Data Sheet

4.3 AC Electrical Specifications

4.3.1 Graphics Input Port

DIN_CLK

TDINCLK

D_INA[23..0],D_INB[23..0],D_HSYNC,D_ACTIVE,D_VALID,

TDPHTDPSU

Parameter Notes Min Typ Max Units DIN_CLK TDINCLK (single pixel mode) 1 6.7 ns TDINCLK (dual pixel mode) 1 7.2 ns D_INA[23..0], D_INB[23..0], D_VALID, D_ACTIVE, D_HSYNC,

TDPSU 1, 3 2.0 ns TDPH 1, 3 1.0 ns

4.3.2 Video Input Port

VCLK

TVCLK

V_IN[15..0],V_ACTIVE,V_VALID

TVPHTVPSU

Parameter Notes Min Typ Max Units

VCLK TVCLK 1 13.3 ns V_IN[15..0], V_ACTIVE, V_VALID

TVPSU 1, 3 2.0 ns TVPH 1, 3 0 ns



4.3.3 Display Port

OCLK_OUT

TOCLKO

TOPOH1TOPOS1

TOCLKI

TOPHTOPSU

TOCLKIO

Outputs: OP_A OP_B OP_ENABLE OP_HSYNC

OCLK_IN

Inputs: OP_ENABLE, OP_HSYNC, OP_VSYNC

TOPOH2TOPOS2

TSKEW TSKEW

OP_B

OP_SKEW = '0'OP_ZERO_HOLD = '0'



Parameter Notes Min Typ Max Units OCLK_IN TOCLKI 1 6.7 ns OCLK_OUT TOCLKO (dual pixel mode) 1 9.1 100.0 ns TOCLKO (single pixel mode) 1 6.7 100.0 ns TOCLKIO1 (OP_ZERO_HOLD = 0) 1, 3, 8 4.5 8.6 ns TOCLKIO2 (OP_ZERO_HOLD = 1) 1, 3, 8 3.5 6.6 ns OP_A[23..0], OP_B[23..0], (OP_SKEW=0) OP_HSYNC, OP_ENABLE (Outputs)

TOPOS1 (OP_ZERO_HOLD=0) 1, 3, 4 1.0 ns TOPOH1 (OP_ZERO_HOLD=0) 1, 3, 4 2.5 ns TOPOS2 (OP_ZERO_HOLD=1) 1, 3, 4 0.0 ns TOPOH2

(OP_ZERO_HOLD=1) 1, 3, 4 4.5 ns OP_B[23..0] (OP_SKEW=1) TSKEW 1,4 0.8 1.2 2.0 ns OP_HSYNC, OP_ENABLE (Inputs)

TOPSU 1, 3, 4 2.0 ns TOPH 1, 3, 4 0 ns



4.3.4 SDRAM Port

MCLK_OUT

TMCLKO

MEM_BS,MEM_RAS_N,MEM_CAS_N,MEM_WE_N,

MEM_DQM_L,MEM_DQM_U

TMCOH

TMCOV

TMDQOH

TMDQOV

MEM_A11,MEM_A[10..0]

MEM_DQ[79..0]OUT

TMAOV

TMAOH

MEM_DQ[79..0]IN

TMDQH

TMDQV


MCLK_OUT TMCLKO 1, 6 8.0 ns MEM_BS, MEM_CS_N, MEM_RAS_N, MEM_CAS_N, MEM_WE_N, MEM_DQM_L, MEM_DQM_U

TMCOH 1, 5, 6 1.5 ns TMCOV 1, 5, 6 6.0 ns MEM_A11, MEM_A[10..0]

TMAOH 1, 5, 6 1.5 ns TMAOV 1, 5, 6 6.0 ns MEM_DQ[79..0] TMDQOH 1, 5, 6, 7 1.5 ns TMDQOV 1, 5, 6, 7 6.0 ns TMDQH 1, 5, 6, 7 1.5 ns TMDQV 1, 5, 6, 7 TMCLKO - 2.0 ns



4.3.5 CPU Port

WR_N

CS_N

AD[7..0]

TWRPW TWRGAP

TCSSU TCSH

DB[7..0]

TADH

TDBH

TADSU

TDBSU

RD_N

CS_N

AD[7..0]

TRDPW TRDGAP

TCSSU TCSH

TADH

TDBOH

TADSU

TDACC

CONTROL PORT WRITE CYCLE

CONTROL PORT READ CYCLE

TDBZ

DB[7..0]



Parameter Notes Min Typ Max

T WRPW 1 ns T WRGAP 1 2 x max (T , T ) MCLK PCLK

RD_N T DACC

Units WR_N

2 x max (T , T ) MCLK PCLK

ns

1 T (max) RDPW ns TRDGAP 1 2 x max (TMCLK, TPCLK) ns CS_N TCSSU 1 0 ns T 1 0 ns AD[7..0] TADSU 1 -2.0 ns TADH 1 -2.0 ns DB[7..0] TDBSU 1 -2.0 ns TDBH 1 0.0 ns TDACC (register) 1 2 x TMCLK + 30 ns TDACC (table) 1 2 x TMCLK +

4 x TPCLK + 30 ns

TDBOH 1 2.0 ns TDBZ 1 6.0 ns

CSH

4.3.6 Miscellaneous

MPLL_CLK_IN,PPLL_CLK_IN

TMCLKIN, TPCLKIN

TMCLKIN = 1 / FMCLKIN TMCLK = 1 / FMCLK TPCLKIN = 1 / FPCLKIN TPCLK = 1 / FPCLK


MPLL_CLK_IN FMCLKIN 1 25 33 MHz PPLL_CLK_IN FPCLKIN 1 25 33 MHz Internal MCLK FMCLK 1 125 MHz Internal PCLK FPCLK 1 160 MHz



Notes: 1. VDD_CORE = 1.7 V to 1.9 V, VDD_IO = 3.0 V to 3.6 V. Ambient temperature = 0 °C to 70 °C,

in free air without heat sink. 2. Input leakage current does not include current through internal weak pull up and pull down

resistors. 3. Setup and hold times are related to the programmable active edge of the CLK. 4. Output port timing is specified for fast slew rate mode. 5. MCLK_OUT_B externally connected to MCLK_IN. 6. MCLK_OUT, control and address capacitance load range: 6 – 25 pF. 7. MEM_DQ[i] capacitance load range: 4 - 10 pF. 8. TOCLKIO is the delay from active edge of OCLK_IN to the active edge of OCLK_OUT, when

OPLL division factor is 1. 9. VOH is defined for IOH ≤ IOH max. VOL is defined for IOL ≤ IOL max. 10. IOH is defined for VOH ≥ VOH min. IOL is defined for VOL ≤ VOL max.



Blank Page


Rembrandt-102 Data Sheet RM102 Interfaces

5 RM102 Interfaces RM102 includes five ports for interface to the external world and one test port, as follows:

• Video port • Graphics port • Display port • Memory port • Control port • JTAG port (for production testing)

The first four ports were designed to support several configurations and modes of operation. Control registers give the user full flexibility over the port configuration and its mode of operation. Port hardware interfaces, and configuration setups will be discussed in the following paragraphs.

5.1 Video Port Interface The video port provides a glueless interface to most known video decoders and external video processors, for example Matisse-1A. The chip video port interface consists of the following input signals:

• V_IN (15:0) - 16 bit data input. • VCLK - Clock for data and control sampling. • V_VSYNC - Vertical sync pulse. • V_HSYNC - Horizontal sync pulse. • V_FIELD - Vertical field indicator, signaling odd or even field. • V_ACTIVE - Active line indicator. • V_VALID - Valid pixel indicator.

All control signals are polarity controlled through the VIN_POLARITY register and should be inverted if input signal is active low. Sampling of data and control signals can be done on the VCLK rising or falling edge using the VIN_POLARITY.VCLK control bit. Three data input formats are supported: 16 bit YUV 4:2:2, 8 bit YUV 4:2:2 and ITU-R BT.656. YUV format is also referred to as YCbCr format, where Cb replaces U and Cr replace V. Format selection is done using VMODE656 and VIN_8BIT control bits in VIN_CONTROL register:

Video Format VMODE_656 VIN_8BIT 16 bit 0 0 8 bit 0 1 ITU-R BT.656 1 N/A

In 8 bit input format and in 656 mode, data input should be connected to V_IN(15..8) while V_IN(7..0) is ignored and can be left unconnected. Pixel component order in 8 bit input format: U0, Y0, V0, Y1, U2, Y2, V2, Y3, .... V_VSYNC, V_HSYNC and V_FIELD are the vertical, horizontal and field indicator signals respectively (not required in 656 mode), with the V_FIELD indicating odd or even field. Even field is defined as the shifted down field relative to the odd field, and its polarity should be adjusted such that V_FIELD is '1' in even fields and '0' in odd fields. The V_FIELD signal should be stable before the 3rd V_HSYNC pulse after V_VSYNC falling edge. For progressive video, the internal field indicator should be fixed to '1'. Therefore, where the V_FIELD input pin is '1' do not invert V_FIELD (FIELD polarity = '0'), and where the V_FIELD input pin is '0' or not connected (pulled down internally), invert the V_FIELD by setting FIELD polarity to '1'. V_ACTIVE and V_VALID input signals provide data sampling information (unused in 656 mode) and define the active video lines and active pixels within these lines for sampling. Two cases are supported, based on CBLANK (composite blank) bit in the VIN_CONTROL register.


RM102 Interfaces Rembrandt-102 Data Sheet

CBLANK = '0': pixels should be sent continuously from the video decoder to be used in two sub cases: a) V_ACTIVE is '1' along the active video lines, and V_VALID is '1' along the active pixel region. b) V_ACTIVE is '1' along the active lines but only during the active pixel region. V_VALID is unused and should be connected to '1' (or left open with polarity invert).

CBLANK = '1': V_ACTIVE is '1' along the active lines during the active pixel region. Pixels sent from the video decoder are valid only when V_VALID = '1'. This case is usually selected for most video decoders.

The video decoder defines the video input resolution - the number of active lines between two V_VSYNC pulses and the number of active pixels in a line. RM102 tracks this information, which can be read by the CPU using VIN_ACTIVE_PIXELS and VIN_ACTIVE_LINES registers. Maximum number of allowable active pixels in a line is 768. Maximum number of allowable active lines is 1023.

VideoDecoder

or

External VideoProcessor

(Matisse - 1A)

RM102Y[7..0] in 16 bit modeYUV [7..0] in 8 bit modes

UV[7..0] in 16 bit modeIgnored in 8 bit mode

VCLK

V_ACTIVE

V_VALID (optional)

V_VSYNC

V_HSYNC

V_FIELD

V_IN[15..8]

V_IN[7..0]

VCLK

V_ACTIVE

V_VALID

V_VSYNC

V_HSYNC

V_FIELD

Figure 4: Video Port Connection for 16/8 Bit Modes



V_HSYNC

V_VSYNC

V_FIELD

V_ACTIVE

VIN_ACTIVE_LINES

EVEN_FIELD

VIN_ACTIVE_LINESN LINES N LINES

ODD_FIELD

VCLK

V_HSYNC

V_ACTIVE

Y0 Y1 Y2 Y3 Y4 Y703Y702Y701

U0 V0 U2 V2 U4 V702U702V700

V_IN(15..8) for 16 BIT FORMAT

V_IN(7..0) for 16 BIT FORMAT

V_IN(15..8) for 8 BIT FORMAT U0 Y0 V0 Y1 U2 Y703V702Y702

V_VALID

In This Example:

VIN_ACTIVE_PIXELS = 704In 16 Bit and 8 Bit formats

Y5 Y6

V4 V6

V2 Y3

U6

Y7

Y2

Y700

U700

U702

V698

Y699

Y701

Figure 5: Video Port Timing For CBLANK = '1'

V_HSYNC

V_VSYNC

V_FIELD

V_VALID

VIN_ACTIVE_LINES

EVEN_FIELD

VIN_ACTIVE_LINESN LINES N LINES

ODD_FIELD

VCLK

V_HSYNC

V_ACTIVE AND V_VALID

Y0 Y1 Y2 Y3 Y4 Y639Y638Y637

U0 V0 U2 V2 U4 V638U638V636

V_IN(15..8) for 16 BIT format

V_IN(7..0) for 16 BIT format

V_IN(15..8) for 8 BIT format U0 Y0 V0 Y1 U2 Y639V638Y638

In This Example:

VIN_ACTIVE_PIXELS = 640In 16 Bit and 8 Bit formats

Y5 Y6

V4 V6

V2 Y3

U6

Y7

Y2

Y636

U636

U638

V634

Y635

Y637

V_ACTIVE

VIN_ACTIVE_PIXELS in 16 BIT format2 * VIN_ACTIVE_PIXELS in 8 BIT format

Figure 6: Video Port Timing For CBLANK = '0'



5.2 Graphics (Data) Port Interface The graphics port provides glueless interface to most analog to digital converters (ADCs) suitable for graphics and video sampling and to any external decoder converting incoming signals (examples: HDTV, TMDS, LVDS or standard video) to YUV 4:2:2, YUV 4:4:4 or RGB formats. The graphics port interface consists of the following signals:

Inputs: • D_INA (23:0) - 24 bit data input port A (primary port). • D_INB (23:0) - 24 bit data input port B (optional secondary port). • DIN_CLK - Sampling clock for data and control. • D_VSYNC - Vertical sync pulse. • D_HSYNC - Horizontal sync pulse. • D_CSYNC - Composite sync pulse usually connected to stripped Sync On Green (optional). • D_FIELD - Vertical field indicator for interlaced input (optional). • D_ACTIVE - Active line indicator (optional). • D_VALID - Valid pixel indicator used in external flow control (optional).

Outputs: • INV - Invert signal to ADC, for inversion of sampling clock within the ADC. • COAST - Coast signal for external PLL. • CLAMP - Programmable clamp pulse for ADC clamping circuitry.

Most I/O control signals are polarity controlled through DIN_POLARITY0 and DIN_POLARITY1 registers. Active low input signals should be inverted. DIN_CLK input is used to sample data and control signals, and its sampling edge (rising or falling) is determined by the DIN_CLK polarity control bit. From hereon it is assumed that the sampling edge is the rising edge and all inputs are active high. Two types of input flow control are supported:

• Internal Flow Control (EXT_ACTIVE = '0'): This mode is usually used when external circuitry does not provide any framing information regarding active lines and active pixels. In a typical application, an external ADC is used to sample analog RGB or YUV (YPbPr). Input format, as well as active lines and active pixels information is gathered from the integral measurement unit and should be programmed to the DIN_ACTIVE_REGION_GRP registers by the CPU.

• External Flow Control (EXT_ACTIVE = '1'): This mode is usually used when external circuitry provides framing information regarding active lines and active pixels. Typical applications are external HDTV decoder, TMDS (DVI) or LVDS receiver, video decoder or video processor (e.g. Matisse-1A), that provide the active lines and active pixels framing signals - D_ACTIVE and D_VALID. When CBLANK_N = '0', D_ACTIVE should be stable along the active lines during the active portion of the line. D_VALID input is optional, and may be used to qualify every sampling clock (DIN_CLK) cycle if the D_VALID_ENABLE control bit is set. When CBLANK_N = '1' the D_ACTIVE and D_VALID signals act as active lines and active pixels indicators respectively, as CBLANK = '0' for the Video Port.

5.2.1 D_VSYNC, D_CSYNC and D_HSYNC D_VSYNC is the vertical sync input pulse. Its polarity can be detected by the measurement unit and should be inverted if input polarity is active low. The measurement unit also measures cycle time and pulse width. The internal programmable Vsync delay unit can be used to remove ambiguity in setting the first active line when the Hsync rising edge coincides with the Vsync falling edge. D_CSYNC is generated by the ADC, and can usually be selected from one of the following sources: 1) Horizontal sync or composite sync, typically generated by computer source. 2) Stripped Sync On Green (SOG) pulse generated by the ADC from the Green (G) or Luminance (Y) component inputs carrying the sync signal.



In both cases D_CSYNC is the "raw" Hsync source (compared to D_HSYNC which is PLL generated), and can be selected as the source for the measurement unit (HSYNC_RAW_MSR_SELECT = '1') to measure its cycle time, pulse width and polarity. D_CSYNC is not synchronized to DIN_CLK, and its sole use is for measurement purposes during the format detection period. After the format is detected D_HSYNC should be directed to the measurement unit (HSYNC_RAW_MSR_SELECT = '0') because it is better suited for interlaced detection and field extraction. D_HSYNC is the horizontal sync pulse generated by the PLL (within the ADC) when EXT_ACTIVE = '0', or directly received from external source when EXT_ACTIVE = '1'. When EXT_ACTIVE = '0', D_HSYNC must be synchronized to DIN_CLK, and its rising edge marks the beginning of the input line, and cause the pixel counter to reset. This pixel counter (together with the line counter reset on D_VSYNC falling edge) is used to mark the active pixels and active lines using DIN_ACTIVE_REGION_GRP parameters. D_HSYNC together with D_VSYNC are used to detect if input is interlaced or progressive, and to extract the field indicator if the input is interlaced. D_HSYNC is usually directed to the measurement unit (when HSYNC_RAW_MSR_SELECT = '0') for measuring its cycle time, pulse width and polarity, and for field indicator and interlaced status detection.

5.2.2 Interlaced and Progressive Inputs The chip supports progressive and interlaced inputs. Interlace detection circuitry within the measurement unit can generate a DIN_INTERLACED status bit, which can be read by the CPU through the MSR_STATUS register. This bit can be used to control the INTERLACE_MODE within the graphics path, either automatically (without CPU intervention) when INTERLACED_DETECT_ENABLE = '1', or by explicitly control of the INTERLACE_MODE control bit when INTERLACED_DETECT_ENABLE = '0'. The interlaced detection circuitry sets the INTERLACE_MODE status bit and Field internal signal according to the position of the D_VSYNC rising edge between two consecutive Hsync falling edges, where Hsync is selected from D_HSYNC or D_CSYNC according to HSYNC_RAW_MSR_SELECT. Internally detected D_FIELD can also be inverted using the D_FIELD polarity control bit. The interlaced detection circuitry will work correctly only when Hsync is not composite. Therefore, with composite sync, D_HSYNC should be directed to the measurement unit and not D_CSYNC, by setting RAW_HSYNC_MSR_SELECT to '0'. Note: to correctly generate field indicator from D_HSYNC and D_VSYNC signals, the ADC should use the trailing edge (and not leading edge) of external Hsync to the PLL to generate D_HSYNC. In interlace mode, the field indicator (Field) can be generated internally when EXTERNAL_FIELD = '0' or can be externally supplied at the D_FIELD input pin when EXTERNAL_FIELD = '1'. In both cases, Field polarity should be controlled by the D_FIELD polarity control bit such that its logic level is '1' during even field period. As with the video input port, the even field is defined as the shifted down field. The D_FIELD input signal should be stable before the D_VSYNC trailing edge if the VSYNC_DELAY_ENABLE control bit is '0', or before the 2nd D_HSYNC trailing edge after the D_VSYNC trailing edge if the VSYNC_DELAY_ENABLE control bit is '1'. See Figure 7 below.



D_HSYNCXOR

DIN_POLARITY_0.D_HSYNC

EXTERNAL_FIELD

1

0

D_VSYNCXOR

DIN_POLARITY_0.D_VSYNC

InterlaceDetectionCircuit in

MeasurementUnit

detectedFIELD

DIN_INTERLACEDstatus bit

INTERLACED_DETECT_ENABLE

1

0

INTERLACE_MODE

INTERLACE_MODEsignal

D_FIELD

XOR

DIN_POLARITY_0.D_FIELD

FIELD signal

1

0

D_CSYNC

RAW_HSYNC_MSR_SELECT

VsyncDelay Unit

D_VSYNC_DELAY

Figure 7: INTERLACE_MODE and FIELD Generation Circuitry

5.2.3 D_INA and D_INB D_INA and D_INB are the pixel data inputs to the graphics port. In dual pixel mode (DUAL_INPUT = '1') the D_INA pixel always precedes the D_INB pixel. D_INB is unused in single pixel input mode (DUAL_INPUT = '0') and can be left open. Data input is sampled during the active edge of the DIN_CLK selected by the DIN_CLK polarity control bit ('0' for rising edge, '1' for falling edge). Input pixel format can be RGB, YUV 4:4:4 or YUV 4:2:2, based on DIN_YUV_422 and YUV_CSC_BYPASS control bits in the DATA_CONFIG register, according to the following table:

Input Format DIN_YUV_422 YUV_CSC_BYPASS RGB 4:4:4 X 0 YUV 4:4:4 0 1 YUV 4:2:2 1 1

YUV 4:2:2 is only supported in single pixel mode. YUV (or YCbCr/YPbPr) can be connected in two pin arrangements controlled by the Y_ON_GREEN bit. If Y_ON_GREEN = '0', YUV position is compatible to Rembrandt-1A, where Y on Red, U on Green and V on Blue. If Y_ON_GREEN = '1', YUV position is the conventional order as follows: Y on Green, U on Blue and V on Red. For new designs use the conventional arrangement. The graphics port data flow is organized in such a way that various data source schemes can be realized by setting a few control bits. Figure 8 below shows the block diagram of the interface data flow, and Table 4 below provides a summary of the various graphics port input data flow modes, and the required setup of control bits for each mode respectively. Note that DIN_CLK in Figure 8 below is after polarity correction.



TFF

DIN_PARALLEL

Right Pixel

Left Pixel

BI_PHASE_CLK DCLK_DIV DUAL_INPUT

D_INA

DIN_CLK

D_INB

1

d q q

qd

d1

1

1

'1'

e

e

Figure 8: Graphics Port Interface - Data Flow Block Diagram

Input Pins / Control Bit

Single Single Bi-Phase

Dual Parallel

Dual Bi-Phase

Dual Shifted

Single H-interlace

DIN_CLK D_INA D_INB

DCLK_DIV 1 0 0 0 1 0

DUAL_INPUT 0 0 1 1 1 0

DIN_PARALLEL 0 0 1 0 0 1

BI_PHASE_CLK 0 1 0 1 0 0

Table 4: Graphics Port Interface - Data Flow Modes Control



5.2.4 Graphics Input Active Region In internal flow control mode the CPU should program the active region at the input - where the active lines and active pixels are located relative to the D_VSYNC falling edge and D_HSYNC rising edge. The measurement unit within RM102 provides information to aid the CPU in this task. Figure 9 below presents the timing diagram of the active region within the graphics input port in the internal flow control mode. Active region parameters in the DIN_ACTIVE_REGION_GRP registers should be programmed relative to parameters in Figure 9 as follows: ACTIVE_LINE_START = lines_to_start - vsync_width ACTIVE_LINES = active_lines ACTIVE_PIXEL_START = 2 * (clks_to_start - 15) if DCLK_DIV = '0' clks_to_start -15 if DCLK_DIV = '1' ACTIVE_PIXELS = 2 * active_clks if DCLK_DIV = '0' active_clks if DCLK_DIV = '1' lines_to_start = Lines from D_VSYNC rising edge to first active line. vsync_width = D_VSYNC pulse width in lines. clks_to_start = DIN_CLK cycles from the D_HSYNC rising edge to the first active pixel. active_clks = Number of DIN_CLK cycles within the active line period. The DIN_ACTIVE_REGION_GRP parameters can also be set in accordance with the active region measurement results that can be read in the MSR_ACTIVE_REGION_GRP registers. See section 7.7 Measurement Unit, page 71 Note: Set ACTIVE_PIXEL_START_LSB_ENABLE to '1' to enable the least significant bit of ACTIVE_PIXEL_START register.

D_HSYNC

D_VSYNC

D_INA / D_INB

D_INA / D_INB

D_HSYNC

DIN_CLK

vsync_width

lines_to_start active_lines

clks_to_start active_clks

a

Figure 9: Graphics Port Active Region Parameters



5.2.5 External ADC and PLL Support All graphics grade triple ADCs also include integral PLL to generate the pixel-sampling clock for the ADC. Most of these devices also provide sync processing circuitry and clamping circuitry. RM102 provides the following support functions: COAST: Command for the external PLL, active when D_VSYNC is '1' up to the first D_HSYNC after the

D_VSYNC pulse. The COAST_ENABLE control bit enables this function. CLAMP: Programmable pulse sent every input line to the ADC or to its analog input circuitry, for clamping

the analog input back porch to zero volt level or mid scale level for color components (U and V). Its position relative to the D_HSYNC rising edge and its width are programmable, using the CLAMP_START and CLAMP_WIDTH control registers. See Figure 10 below.

The INV output pin controls the sampling clock within the ADC, on condition the ADC supports clock inversion. When the INV is active, the sampling clock within the ADC is inverted, effectively advancing the sampling position by 1/2 sampling clock cycle. The INV signal is active in H-Interlace mode (HINTERLACE_MODE = '1') during the even pixels field, or when INV_SET = '1' for constant inversion. In H-Interlace mode, the INV signal switches just after the trailing edge of each D_VSYNC pulse.

D_HSYNC

CLAMP

4 + 2 * CLAMP_START(din_clk cycles)

2 * CLAMP_WIDTH (din_clk cycles)

Figure 10: CLAMP Timing

5.2.6 Graphics Port Connection Examples Typical connection schemes are demonstrated in Figure 11 below.

Scheme A: A triple ADC with integral PLL is used. The ADC can sample triple RGB sources with separate Hsync and Vsync, with Composite sync or with Sync embedded in the Green color component. It can also sample the YPbPr component input with sync embedded in the Y component. The ADC provides to the RM102 single or dual pixel per DIN_CLK cycle, D_CSYNC (raw Hsync) from its Hsync input or stripped from Green or Y components, D_HSYNC from the PLL synchronized to DIN_CLK, and D_VSYNC from its Vsync input, or stripped from the composite sync or from Green or Y components. RM102 can optionally supply clamp (CLAMP) or coast (COAST) signals if these functions are not implemented within the ADC unit. Horizontal interlaced mode can only be realized in single pixel mode by providing the INV signal to control sampling clock inversion within the ADC. This scheme uses internal flow control, meaning that active lines and active pixels are internally controlled and programmed using information gathered by the CPU from the measurement unit.

Scheme B: In scheme B, an external device provides the flow control - in this case a DVI receiver. In addition to pixel data (D_INA and D_INB), pixel clock (DIN_CLK), D_HSYNC and D_VSYNC, the D_ACTIVE signal should be supplied to signal the start and end of an active pixel data within a line. An optional D_VALID signal can be connected to mark the active pixels within the active line period.



RM102

D_HSYNCHSOUT

Tripple ADCwith PLL

G

B

D_INA (23..0)

COAST

D_VSYNCVSOUT

Scheme A: ADC with integrated PLL and RM102 in internal flow control (EXT_ACTIVE = '0')

CLAMP

D_INB (23..0)

INV

R

Pb

Pr

Y

Hsync

Vsync

SOGOUT

DATACKD_CSYNC

DIN_CLK

OUTA

COAST

RM102

D_HSYNCHSYNC

D_INA (23..0)

D_VSYNCVSYNC

D_INB (23..0)

ODCK DIN_CLK

QE

QO (1)

D_ACTIVEDE

DVI Receiver

Scheme B: DVI Receiver and RM102 in external flow control (EXT_ACTIVE = '1')

DVI

CLAMP

CKINV

OUTB (1)

(1) For dual pixel mode.

Figure 11: Graphics Port Connection Examples



5.3 Display Port The display port provides a glueless interface to most digital displays, to LVDS, TMDS (DVI) or other digital display drivers, as well as to digital to analog converters (DAC) used for analog display drivers. The display port generates all control signals in free run mode, or can be locked to external control signals to remove motion artifacts or for applications such as video walls, multi panel display, external display windowing, etc. Thus all control signals can be configured as inputs or outputs. Display port pinout interface consist of the following signals:

Outputs: • OP_A (23:0) - 24 bit display port A (primary port). • OP_B (23:0) - 24 bit display port B (optional secondary port for two pixels per clock mode). • OCLK_OUT - Display clock, for external data and control sampling.

Inputs: • OCLK_IN - Input clock for internal PLL, used to generate OCLK_OUT

Bi-directional: • OP_VSYNC - Vertical sync pulse. • OP_HSYNC - Horizontal sync pulse. • OP_ENABLE - Display active pixels indicator. • OP_FIELD - Field indicator, optionally used for interlaced output. • OP_FIELD_3D - 3D field indicator used in 3D modes to control LCD glass shutter.

All control signals are polarity controlled. Active edges (rising or falling) of OCLK_IN and OCLK_OUT are also programmable.

5.3.1 OP_A and OP_B Pixel data output can be sent in one or two pixels per clock, using the OP_A and OP_B ports. The DUAL_PIXEL control bit should be set to '0' for single pixel per clock mode and to '1' for two pixels per clock mode. Pixel format can be RGB or YUV 4:4:4, controlled by the YUV_FORMAT bit. Y/U/V (Y/Cb/Cr or Y/Pb/Pr) output components can be positioned on R/G/B components (respectively) when Y_ON_GREEN = '0' for compatibility with RM1A, or on G/B/R (respectively) when Y_ON_GREEN = '1' for conventional positioning. Each color component can be represented in 5, 6 or 8 bits, independently, controlled by the DITHER_CONTROL register. For example: 8:8:8, 6:6:6, 5:6:5, and 5:5:5 resolutions can easily be realized. When the number of active bits in a pixel component is less than 8 bits, the active bits are positioned in the high order bits. Each color component is internally represented by 10 bits at the gamma look up table, and by using dithering with 2D error diffusion algorithm the chip performs resolution reduction, without degrading image luminance and without introducing extra digital noise. OP_A, OP_B and other pixel control signals (OP_HSYNC, OP_VSYNC, OP_ENABLE) are synchronized to the falling edge of OCLK_OUT, so a display or external device can sample the signals on the rising edge of OCLK_OUT. OCLK_OUT polarity can be inverted if external sampling is required on the falling edge of OCLK_OUT. To reduce current switching (and reduce EMI) the user can decrease the output port slew rate by setting the OP_SLEW_RATE control bit, or in dual pixel mode by introducing a skew of about 1.2 ns (typical) by setting the OP_SQEW control bit. Pixel data output is valid when the OP_ENABLE signal is active. Outside the valid region black pixels are sent out (0 : 0 : 0 in RGB, 0 : 0x80 : 0x80 in YUV).

5.3.2 Display Lock Modes The display interface is designed to support several lock modes, providing maximum flexibility for the OP_VSYNC, OP_HSYNC and OP_ENABLE signal sources. LOCK_MODE and VSYNC_SOURCE control bits are used for controlling the lock mode and pixel control signals source. see Table 5 below. Lock Mode 0 is used in free run mode, where all control signals are internally generated and are fully programmable in terms of timing and polarity.



Lock Mode 1 is used to lock the display frame rate to externally supplied vertical sync selected by OUT_VSYNC_SOURCE control bits - either from the OP_VSYNC pin or from the V_VSYNC or D_VSYNC input pins. If the lock is to V_VSYNC or D_VSYNC, a display frame will be triggered on the trailing edge of the selected vertical sync input. Delayed D_VSYNC as well as delayed V_VSYNC can be used as a frame trigger to reduce frame delay through RM102. Use DIN_LINE_TRIG for delayed D_VSYNC and V_VSYNC_DELAY for delayed V_VSYNC. If the selected vertical sync source does not exist, there will be no frame trigger and OP_VSYNC will not be generated. The OP_HSYNC and OP_ENABLE control signals are internally generated based on DISPLAY_FRAME_GRP parameters. The OP_HSYNC internal cycle counter can run uninterrupted when HSYNC_CONTINUOUS_MODE = '1', or is reset at frame trigger (when the selected external vertical sync occurs) when HSYNC_CONTINUOUS_MODE = '0'. In this case the last line length will usually be shorter than the required line cycle, but the first OP_HSYNC pulse is not generated, eliminating this short line. In Lock Mode 2, OP_HSYNC and OP_VSYNC are both externally supplied, and OP_ENABLE and active data is sent out based on the active region timing parameters in the DISPLAY_FRAME_GRP registers. In Lock Mode 3, OP_HSYNC, OP_VSYNC and OP_ENABLE are all externally supplied - for full external control of the display port timing. This mode enables external control on the display window position and size relative to horizontal and vertical syncs using the OP_ENABLE signal. In this mode all display parameters in DISPLAY_FRAME_GRP are ignored.

Sources LOCK_MODE VSYNC_SOURCE

OP_VSYNC OP_HSYNC OP_ENABLE 0 = FREE RUN N/A internal internal internal

0 external internal internal 1 D_VSYNC internal internal 2 V_VSYNC internal internal

1 = LOCK_VS

3 Delayed D_VSYNC internal internal 2 = LOCK_VHS N/A external external internal 3 = LOCK_VHB N/A external external external

Table 5: Display Port Lock Modes and Display Control Sources

5.3.3 OP_HSYNC, OP_VSYNC and OP_ENABLE OP_VSYNC, OP_HSYNC and OP_ENABLE signals are fully controlled using the DISPLAY_FRAME_GRP, DISPLAY_HV_DELAY_0 and DISPLAY_HV_DELAY_1 registers. All horizontal parameters in these registers are defined in terms of pixels (or pixel equivalent) and not OCLK_OUT clock cycles - to make display setting independent of pixel mode (single / dual). This means that all horizontal timing parameter are defined in terms of OCLK_OUT cycles in a single pixel mode, and in 1/2 OCLK_OUT cycles in dual pixel mode. Both OP_VSYNC and OP_HSYNC are generated from an internal pixel counter and line counter in free run lock mode. HSYNC_CYCLE and HSYNC_WIDTH parameters define OP_HSYNC timing. VSYNC_CYCLE and VSYNC_WIDTH parameters define OP_VSYNC timing. DISPLAY_HV_DELAY_0 and DISPLAY_HV_DELAY_1 define the delay from the leading edge of OP_HSYNC to the leading and falling edges of OP_VSYNC (see also next section). The OP_VSYNC output can be delayed several lines after the frame trigger, based on the VSYNC_OFFSET parameter. This delay may be required if OP_VSYNC should be advanced closer to the first active line (to reduce vertical back porch) as there is a minimum limit on "ACTIVE_LINE_START" parameter. This delay may also be required if the OP_FIELD signal should be valid before the OP_VSYNC leading edge. OP_ENABLE signals the active pixels. The ACTIVE_LINE_START and ACTIVE LINES registers define active lines, starting from the frame trigger. The ACTIVE_PIXEL_START and ACTIVE_PIXELS registers define the active pixels, starting from the OP_HSYNC leading edge. The ACTIVE_LINE_START parameter should have a minimum value, to enable internal pipe loading. The minimum required values for video and data paths are 14 and 7 respectively. If the minimum value is not met, the display will be blanked and DISPLAY_DATA_MISS interrupt will be generated (if enabled). OP_ENABLE is active during the active pixel interval on active lines, signaling valid pixels at the display port. The OP_ENABLE signal can be advanced by 1,2 or 3 OCLK_OUT cycles before valid data is sent out. OP_ENABLE_LATENCY controls this latency.



When OP_ENABLE or OP_HSYNC are inputs in lock mode 2 or 3, they are sampled internally at the active edge of OCLK_IN (dictated by OCLK_IN polarity control bit), and should follow setup and hold time requirements (see Display Port timing data). These modes require that the internal OCLK PLL (OPLL) be set such that OCLK_OUT frequency equals OCLK_IN frequency (division factor = 1), and OPLL_CLK_DESKEW_DISABLE be set to '0'. Internal latency of OP_ENABLE and OP_HSYNC signals in these modes is 8 OCLK_OUT clock cycles. OP_HSYNC can be configured to generate Composite Sync when COMP_SYNC = '1', as required by component output modes to support external ADC. Control parameters for Hsync and Vsync timing and polarity still holds. In most cases Hsync polarity should be set in reverse to the Vsync polarity bit.

5.3.4 Progressive and Interlaced Outputs Progressive and interlaced displays are supported and controlled by the INTERLACE_MODE control bit. In progressive display (INTERLACE_MODE = '0'), the OP_FIELD signal is not active and the delay between OP_HSYNC and OP_VSYNC is fixed and is determined by the DISPLAY_HV_DELAY_1 register. In interlaced display (INTERLACE_MODE = '1'), two vertical fields are generated - odd and even fields. As with the input ports, the odd field is defined as the "upper" field (lines 1,3,5,...) and the even field is defined as the "lower" field (lines 2,4,6,...). The Field indicator can be internally or externally generated based on the OP_FIELD_SOURCE control bit. Internally generated field indicator (OP_FIELD_SOURCE = '0') is usually generated in lock modes 0 and 1, and can be provided:

1. When OP_FIELD_LOCK = '0': from internal field generator, by toggling the field indicator every other field.

2. When OP_FIELD_LOCK = '1': from the selected video or graphics port field indicator, when OP_VSYNC is locked to interlaced D_VSYNC or interlaced V_VSYNC input. (LOCK_MODE = 1 and VSYNC_SOURCE not equal to 0).

The OP_FIELD signal toggles just (4 OCLK_OUT cycles) before the second OP_HSYNC pulse after the frame trigger. If VSYNC_OFFSET = 0 the rising edge of OP_VSYNC will precede OP_FIELD toggling, and if VSYNC_OFFSET > 0 the rising edge of OP_VSYNC will follow OP_FIELD toggling. If OP_FIELD_SIGNAL = '0', the OP_VSYNC leading edge delay relative to the OP_HSYNC leading edge is independently programmable for the odd and even fields, using the DISPLAY_HV_DELAY_0 register for the odd field, and the DISPLAY_HV_DELAY_1 register for the even field. Correct programming can provide the required field information for the display device. If lock mode is not equal to free run, the first OP_HSYNC pulse is not generated in HSYNC_CONTINUOUS_MODE = '0' to disable short line just before the frame trig (see above). It is recommended in this case to set VSYNC_OFFSET ≥1 to guarantee OP_VSYNC rising and falling edges positioning relative to OP_HSYNC as programmed. If the OP_FIELD_SIGNAL = '1,' the OP_HSYNC to OP_VSYNC delay is determined only by the DISPLAY_HV_DELAY_1 register - as in progressive mode. Externally generated field indicator (OP_FIELD_SOURCE = '1'), usually generated when OP_VSYNC is externally supplied and can be provided:

1. When OP_FIELD_SIGNAL = '0': from OP_HSYNC to OP_VSYNC delay using an internal field detector in the Measurement Unit. Detection is based on measuring the position of the OP_VSYNC leading edge between two consecutive OP_HSYNC trailing edges.

2. When OP_FIELD_SIGNAL = '1': from OP_FIELD pin. The field signal should be valid before the third OP_HSYNC after frame trig.

Figure 12 below presents the timing diagram of the display port data and control signals. The frame trigger starts every frame (or field) according to the timing parameters, and is obtained internally in free run mode or externally in all other lock modes. In lock mode 1, the first OP_HSYNC pulse (marked with an *) is not generated when HSYNC_CONTINUOUS_MODE = '0'. All vertical parameters in this diagram are given in terms of OP_HSYNC lines, and all horizontal parameters in terms of OCLK_OUT cycles. Display frame parameters in DISPLAY_FRAME_GRP and DISPLAY_HV_DELAY registers should be programmed according to parameters in Figure 12 as follows:



VSYNC_CYCLE = vsync_cycle VSYNC_WIDTH = vsync_width HSYNC_CYCLE = hsync_cycle if DUAL_PIXEL = 0 2 * hsync_cycle if DUAL_PIXEL = 1 HSYNC_WIDTH = hsync_width if DUAL_PIXEL = 0 2 * hsync_width if DUAL_PIXEL = 1 ACTIVE_LINE_START = lines_to_start + 1 ACTIVE_LINES = active_lines ACTIVE_PIXEL_START = clks_to_start if DUAL_PIXEL = 0 2 * clks_to_start if DUAL_PIXEL = 1 ACTIVE_PIXELS = active_clks if DUAL_PIXEL = 0 2 * active_clks if DUAL_PIXEL = 1 DISPLAY_HV_DELAY_i = (hv_delay_i - 2) / 16 if DUAL_PIXEL = 0 (hv_delay_i - 2) / 8 if DUAL_PIXEL = 1 i = 0 for odd field. i =1 for even field in interlace mode, and for progressive scan mode.

OP_HSYNC

OP_VSYNC

OP_ENABLE

OP_ENABLE

OP_HSYNC

OCLK_OUT

vsync_width

lines_to_start active_lines

clks_to_start active_clks

hv_delay_0 hv_delay_1 hv_delay_1

vsync_cycle - odd field

hv_delay_0

lines_to_start

OP_A Black 0 1 2 102310221021 Black

hsync_width

hsync_cycle

vsync_cycle - even field

OP_FIELD

frame trigger frame trigger

OP_A Black 0 2 4 102210201018 Black

OP_B Black 1 3 5 102310211019 BlackDUAL_PIXEL = '1'

DUAL_PIXEL = '0'

* *

vsync_width

Figure 12: Display Port Timing-Free Run Mode, Interlaced Display, VSYNC_OFFSET=0

Parameters in above figure are defined as follows: vsync_cycle = OP_VSYNC cycle in lines. vsync_width = OP_VSYNC pulse width in lines. hsync_cycle = OP_HSYNC cycle in OCLK_OUT clocks. hsync_width = OP_HSYNC pulse width in OCLK_OUT clocks. lines_to_start = Lines from frame trigger to first active line. active_lines = Number of active lines in one display field.



clks_to_start = OCLK_OUT clock cycles from OP_HSYNC leading edge to leading edge of OP_ENABLE and data out. In lock mode 2, the value 9 should be subtracted before being used for ACTIVE_PIXEL_START, to compensate for the internal delay.

active_clks = Number of OCLK_OUT cycles within active line period.

5.3.5 OP_FIELD_3D The chip supports 3D mode to drive separate displayed left/right fields, one for the left eye and one for the right eye. Signal OP_FIELD_3D is generated to indicate left/right field for external LCD glass control ('1' indicates right field, polarity controlled). OP_FIELD_3D can be generated internally, or supplied externally using the OP_FIELD_3D_SOURCE control bit. When OP_FIELD_3D_SOURCE = 0, OP_FIELD_3D is internally generated, and is toggled on every frame trig. When OP_FIELD_3D_SOURCE = '1', OP_FIELD_3D should externally be supplied, and should be toggled before the 2nd OP_HSYNC after every frame trig.

5.3.6 Power Up Sequence After power up reset, all five control signals are driven to 3-state (with pull down internal resistor) to avoid contention if one or more control signals are externally driven. The CPU should first program all signal source control bits (LOCK_MODE, VSYNC_SOURCE, OP_FIELD_SOURCE and OP_FIELD_3D_SOURCE), signal polarities, OCLK PLL and all other controls and timing parameters. Only then can DISPLAY_PORT_OE be set to '1,' enabling the control signals to drive the display. The DISPLAY_ENABLE control bit controls pixel data out flow. When this bit is initialized to 0, this causes black pixels to be sent out. This bit can be set to '1' only when a visible display is required.

5.4 SDRAM port The SDRAM port is the interface to the external frame buffer, used to store video fields, data frames and up to four OSD images. This storage is required for frame rate conversion, memory window for zoom and pan and for video de-interlacing. The SDRAM port is designed to work with standard commodity SDRAM devices rated for at least 125 MHz – available from many vendors. Memory data bus width and memory depth are user selectable parameters - based on the application. The user can select from one of four different data bus sizes: 16, 48, 64 and 80 bit - according to the memory required bandwidth. The user can choose the memory depth according to the required storage size. Two common SDRAM devices that can be used:

• 16 Mbit part: 16 bit/word, 1 M addresses organized in 2 banks of 512 K words/bank. • 64 Mbit part: 32 bit/word, 2 M addresses organized in 4 banks of 512 K words/bank.

Examples of SDRAM devices suitable for connection to RM102:

Configuration Manufacturer Part Number MICRON MT48LC1M16A1S-7 HUNIX HY57V161610BTC-7 SAMSUNG K4S161622E-TC70

16 Mbit: 512 K x 16 bit x 2 bank

WINBOND W981616BH-7 MICRON MT48LC2M32B2-7 HUNIX HY57V643220BTC-7 SAMSUNG K4S643232F-TC70

64 Mbit: 512 K x 32bit x 4 bank

WINBOND W986432DH-7

Table 6: Examples of Suitable SDRAM Parts for Frame Buffer Memory clock, address and control signals are generated by RM102 internal SDRAM controller, and should be connected to all SDRAM parts with a minimum length in a daisy chain scheme.



The memory port pinout interface consists of the following signals:

Bi-directional: • MEM_DQ (79:0) - 80 bit memory data bus.

Inputs: • MPLL_CLK_IN - Input clock for internal memory clock (mclk) PLL, used to generate

MCLK_OUT and MCLK_OUT_B. Frequency range: 25 to 33 MHz. • MCLK_IN - Memory clock (MCLK) input. Externally connected to MCLK_OUT_B.

Outputs: • MCLK_OUT - Memory clock, driving all SDRAM clock inputs. • MCLK_OUT_B - Buffered version of MCLK_OUT, connected externally to MCLK_IN. • MEM_A(10:0) - Address bus driving SDRAM address pins A0 to A10. • MEM_A11/MEM_BS1 - Optional high order address bit (A11), when using memory devices with

1 Mword/bank or driving second high order bank select bit (BS1) in 4-bank devices.

• MEM_BS - Drive SDRAM bank select input. In 4-bank devices drive low order bank select bit (BS0).

• MEM_CS_N - Drive SDRAM chip select. Active low. • MEM_RAS_N - Drive SDRAM row address strobe. Active low. • MEM_CAS_N - Drive SDRAM column address strobe. Active low. • MEM_WE_N - Drive SDRAM write enable. Active low. • MEM_DQM_L - Drive SDRAM lower byte DQM in 16 bit devices, or DQM0 and DQM1 in

32 bit devices. • MEM_DQM_U - Drive SDRAM upper byte DQM in 16 bit devices, or DQM2 and DQM3 in

32 bit devices. RM102 connection diagram to external SDRAM devices:

Data Connection: • For 16 bits data bus, connect pins MEM_DQ(15:0). • For 48 bits data bus, connect pins MEM_DQ(47:0). • For 64 bits data bus, connect pins MEM_DQ(79:16). • For 80 bits data bus, connect pins MEM_DQ(79:0).

Address Connection: • For 512 K x 16 bit x 2 bank SDRAM devices:

Connect MEM_A(10:0) to memory address and MEM_BS to memory bank select (BS). • For 512 K x 32 bit x 4 bank SDRAM devices:

Connect MEM_A(10:0) to memory address, MEM_BS to BS0 and MEM_A11 to BS1.

Control Connection: MCLK_OUT and all other address and control signals should be connected to all SDRAM devices in a daisy chain manner with a serial resistor (33 ohms) close to RM102. SDRAM CKE inputs should be connected to VCC. Connect MCLK_OUT_B to MCLK_IN, close to the package pins. Maintain same trace length on MCLK_OUT, control and address lines from RM102 to every memory device. Figure 13 shows a SDRAM connection diagram for a 64 bit wide frame buffer with 64 Mbit (512 K x 4 bank x 32 bit) SDRAM parts, and Figure 14 for an 80 bit wide frame buffer with 16 Mbit (512 K x 2 bank x 16 bit) SDRAM parts.



#2

#1RM102

MEM_CS_NMEM_CAS_N

MEM_RAS_N

MEM_WE_NMEM_DQM_L

MEM_A(10:0)

MEM_A11

MEM_BS

A(10:0)

BS1

CS#

BS0

RAS#

CAS#

DQM0, DQM1

WE#

DQ(31:0)

DQ(31:0)

MEM_DQ(47:16)

MEM_DQ(79:48)

MEM_DQ(15:0)open

MEM_DQM_UDQM2, DQM3

MCLK_OUTB

MCLK_OUT

MCLK_INCKEVDD

CLK 64 MbitSDRAM

Figure 13: SDRAM Connection Diagram with 64 Bit Wide Frame Buffer

#5

DQ(31:0)

#4

DQ(31:0)

#3

DQ(31:0)

#2 #1

MCLK_OUTB

RM102

CLKMCLK_OUT

MCLK_IN

MEM_CS_N

MEM_CAS_N

MEM_RAS_N

MEM_WE_N

MEM_DQM_L

MEM_A(10:0)

MEM_BS

MEM_DQM_U

CKEVDD

A(10:0)

CS#

BS

RAS#

CAS#

LDQM

WE#

UDQM

DQ(31:0)MEM_DQ(15:0)

DQ(31:0)MEM_DQ(31:16)

MEM_DQ(47:32)

MEM_DQ(63:48)

MEM_DQ(79:64)

16 MbitSDRAM

Figure 14: SDRAM Connection Diagram with 80 Bit Wide Frame Buffer



5.5 Control Port The control port provides a simple interface to any generic parallel CPU bus. The control port pinout interface consists of the following signals:

• DB (7:0) - 8-bit bi-directional data bus, used for byte transfer in write and read operations. • AD (7:0) - 8-bit input address bus, used to select internal registers and tables. • CS_N - Chip select input. Active low. • WR_N - Write command input. Active low. • RD_N - Read command input. Active low. • IRQ - Interrupt request output. Polarity controlled.

The device includes registers, register groups and tables.

Register A register is defined by a unique address and is used for byte storage. Most registers are accessed for write and read operations, but status registers are read-only type, and a few command registers used to trigger an internal operation within the device are write-only type.

Register Group A register group (also called register file) is an orderly group of registers sharing the same address. Grouping registers is convenient when registers share the same functionality, same module or are updated together. All registers within a group have the same data width - which can be one or two bytes. If the registers within the group are two bytes wide, the least significant byte in each register should be accessed first. For each register group, an internal byte pointer is used to select the byte currently accessed. Before accessing the register group for write or read, the pointer should be cleared by a CLEAR_ADDR command. This pointer is automatically incremented after every read or write access.

Tables The device include several tables (or internal memory blocks) that can be written or read by the CPU, as follows:

• Three YUV_LUT tables: LUT_Y, LUT_U, LUT_V • Three RGB_LUT tables: LUT_R, LUT_G, LUT_B • Three PALETTE LUT tables: PALETTE_R, PALETTE_G, PALETTE_B • Two non linear scaling tables: NL_X, NL_Y

Each table is accessed for write and read by the same mechanism used in the register group. Each table has a byte pointer that should be cleared using the ADDR_CLEAR command before accessing. The table is then loaded (or read) byte by byte, with the l.s.byte first, if each table address contains more than one byte of data (RGB_LUT tables use 10 bits of data - stored in two consecutive bytes). When a double bank is used (in the non linear scaling tables), table loading should be followed by a switch bank command to activate bank switching.

Shadow Registers Changing the contents of registers and/or register groups, thus influencing display window sizing, scaling, window positioning and image colors, is undesirable during active image region and should be enabled only during the vertical blanking interval. To accomplish this goal with minimum user intervention, a load shadow mechanism is used. Each defined register contains an internal shadow resister for loading. After all shadow registers are loaded, a LOAD_SHADOW command should be issued, causing the operational registers to be loaded with the content of the shadow registers during the appropriate vertical sync, selected by the LOAD_SHADOW command parameter. The CPU always reads the operational register and not the shadow register (except DISPLAY_CONTROL_0 register). The load shadow command parameter selects one of the following modes: load shadow immediate: Operational registers will be loaded immediately without waiting for the vertical

sync. Usually used for chip initialization. load shadow vin: Operational registers at the video_in path will be loaded at V_VSYNC trailing edge. load shadow din: Operational registers at the data_in path will be loaded at D_VSYNC trailing edge. load shadow vout: Operational registers at the video_out path will be loaded at the display frame

trigger, (this trigger causes assertion of display Vsync - OP_VSYNC). load shadow dout: Operational registers at the data_out path will be loaded at the display frame trigger.



load shadow video path: Combined load shadow vin and load shadow vout. load shadow data path: Combined load shadow din and load shadow dout. During the time period from load shadow command activation to functional register loading, the LOAD_SHADOW_BUSY flag is high, signaling that the functional registers have not been loaded yet. This flag can cause an interrupt, and can be read in the STATUS2 register.

Functionalregister

Shadowregister

To process

Load shadow(immediate or

at VSync)

CPUwrite

Data bus (read)

Data bus (write)

Figure 15: Shadow Register Structure

IRQ The device can generate an interrupt request signal to the CPU by asserting IRQ pin. IRQ output polarity is programmable using an IRQ_POL control bit. Each interrupt source can be masked individually, using an IRQ_MASK register. The interrupt sources and their bit position within the IRQ_REG and IRQ_MASK registers is listed below:

IRQ Sources: 1. MEASURE_READY - Completion of measurement cycle. 2. FLAGS_SUM - Assertion of one of the internal flow control error

flags, which can be read by the flag register. 3. OP_VSYNC - Display frame trigger. 4. D_VSYNC - Graphics port vertical sync trailing edge. 5. V_VSYNC - Video port vertical sync trailing edge. 6. DISPLAY_DATA_READY_MISS - Display blanking due to missing data (improper

register setting). 7. LOAD_SHADOW_DONE - Completion of load shadow internal process. 8. GP0 - Rising edge of external GP0 input.

IRQ is asserted on the rising edge of an unmasked IRQ source. The CPU can check the interrupt status and IRQ source by reading the IRQ_SOURCE register, and clearing the IRQ_SOURCE register and the IRQ output pin by the IRQ_CLEAR command. If more than one source triggers the interrupt before the CPU reads the IRQ_SOURCE register - all activated source bits will be set. The user should follow each IRQ_SOURCE read command by IRQ_CLEAR command to reduce the probability of an unnoticed interrupt.



5.5.1 JTAG port The JTAG port fully supports IEEE1149.1 for printed circuit board testing, and can be used to verify board assembly and In/Out pin functionality. The JTAG port of RM102 include the following pins:

Inputs: • TDI - Test data input. • TMS - Test mode select. • TCK - Test clock. • NTRST - Test reset, active low (optional).

Outputs: • TDO - Test data output.

During normal operation, NTRST must be pulled low or left open (NTRST has an internal pull down resistor). When the test port is connected to a JTAG tester, TDI and TDO are connected through a test chain to the tester, while TMS, TCK and optionally NTRST pins are directly connected to the tester. The chip supports the following test instructions (instruction = 4 bits):

Test Instruction Instruction Code BYPASS "1111" HIGHZ "0101" CLAMP "0100" IDCODE "0001" EXTEST "0000" SAMPLE "0010"

Table 7: JTAG Test Instructions The Boundary-Scan Description Language (BSDL) file will be provided on request to customers to help them design their test program.


Rembrandt-102 Data Sheet Typical Application System

6 Typical Application System

Figure 16: Typical Application System


Typical Application System Rembrandt-102 Data Sheet

Blank Page


Rembrandt-102 Data Sheet RM102 Register Table

7 RM102 Register Tables The following pages describing the RM102 registers, contain the following notations:

• (S) – Denotes Shadow registers or shadow register group. • N/A - Not Applicable. • Reserved – Contains a ‘0’ for write mode and is ignored for read mode.

7.1 General Registers Address Register Name Bits Bit Group Name Reset

Value 0 VIDEO_ENABLE 0 1 DATA_ENABLE 0 2 OSDA_ENABLE 0 3 OSDB_ENABLE 0 4 VIDEO_FREEZE 0 5 DATA_FREEZE 0 6 DATA_TOP 0

0x00 OUTPUT_CONTROL

7 OSDB_TOP 0 0 GP0_CONFIG 0 1 GP1_CONFIG 0 3..2 SDRAM_CONFIG 0x2 4 SHUT_OCLK_PLL 0 5 IRQ_POL 0 6 SDRAM_A11_ENABLE 0

0x01 CONFIG1

7 Reserved N/A 0 VIN_FILTER N/A 1 VOUT_FILTER N/A 2 DIN_FILTER N/A 3 DIN_ACTIVE_REGION N/A 4 SDRAM_CONTROL N/A 5 MEASUREMENT N/A 6 VIN_CTI N/A

0x02 ADDR_CLEAR_0 (Write only)

7 DIN_CTI N/A 0 YUV_LUT N/A 1 RGB_LUT N/A 2 PALETTE N/A 3 CSC N/A 4 OUTPUT_WINDOWS N/A 5 DISPLAY_FRAME N/A 6 BACKGROUND N/A

0x03 ADDR_CLEAR_1 (Write only)

7 NL_TABLES N/A 2..0 MODE N/A 0x04 LOAD_SHADOW

(Write only) 7..3 Reserved N/A 0 MEASURE_READY 0 1 FLAGS_SUM 0 2 OP_VSYNC 0 3 D_VSYNC 0 4 V_VSYNC 0 5 DISPLAY_DATA_MISS 0 6 LOAD_SHADOW_DONE 0

0x05 IRQ_SOURCE (Read only)

7 GP0 0 0x06 IRQ_MASK 7..0 Same as IRQ_SOURCE 0xFF

0 Clear IRQ and IRQ_SOURCE register N/A 0x07 IRQ_CLEAR (Write only) 7..1 Reserved N/A


RM102 Register Table Rembrandt-102 Data Sheet

Address Register Name Bits Bit Group Name Reset

Value 0 VIN_OVERWRITE 0 1 DIN_OVERWRITE 0 2 DISPLAY_OVERREAD 0 3 OSD_IN_OVERWRITE 0 4 IDATA_OVERREAD 0 5 Reserved 0 6 VIDEO_CROSSING 0

0x08 FLAGS (Read only)

7 DATA_CROSSING 0 0 FLAGS_CLR N/A 0x09 FLAGS_ CLEAR

(Write only) 7..1 Reserved N/A 0 GP0 0 1 GP1 0

0x0A GP_OUTPUT

7..2 Reserved N/A 0 GP0 N/A 1 GP1 N/A 2 MCONF0 (1) 3 MCONF1 (1) 4 PPLL_DISABLE (1)

0x0B STATUS1 (Read only)

7..5 Reserved N/A 0 NL_Y_SWITCH_BUSY 0 1 NL_X_SWITCH_BUSY 0 2 LOAD_SHADOW_BUSY 0 3 OSD_LOAD_BUSY 0

0x0C STATUS2 (Read only)

7..4 Reserved N/A 0x0D MPLL_MDIV_L (S) 7..0 0x02

1..0 0x0 0x0E MPLL_MDIV_H (S) 7..2 Reserved N/A

0x0F MPLL_NDIV (S) 7..0 0x00 0x10 PPLL_MDIV_L (S) 7..0 0x03

1..0 0x0 0x11 PPLL_MDIV_H (S) 7..2 Reserved N/A

0x12 PPLL_NDIV (S) 7..0 0x00 0x13 OPLL_MDIV_L (S) 7..0 0x00

1..0 0x0 0x14 OPLL_MDIV_H (S) 7..2 Reserved N/A

0x15 OPLL_NDIV (S) 7..0 0x00 0 VIN_FILTER_C4_10BITS 0 1 VOUT_FILTER_C4_10BITS 0 2 DIN_FILTER_C4_10BITS 0 3 Must be '0' 0 4 Must be '0' 0 5 Must be '0' 0 6 VIDEO_FILTERS_LIMITER_ENABLE 0

0x16 CONFIG2

7 DIN_FILTER_LIMITER_ENABLE 0 0 OP_ZERO_HOLD 0 1 OP_SKEW 0 2 Must be '0' 0 3 OP_SLEW_RATE 1

0x17 PINS_CONTROL

7..4 Reserved N/A 3..0 POST_DIV 0x0 4 FRANGE 0 5 DESKEW_DISABLE 0

0x18 OPLL_CONTROL

7..6 Reserved N/A Note (1): Reset value is set by configuration resistors.



7.2 NL Scale Tables Address Register Name Bits Bit Group Name Reset

Value 1..0 NL_Y_SELECT 0x1 3..2 NL_X_SELECT 0x1 4 NL_Y_FORMAT 0

0x1A NL_CONTROL

7..5 Reserved N/A 0 NL_Y_TABLE N/A 1 NL_X_TABLE N/A

0x1B NL_SWITCH (Write only)

7..2 Reserved N/A 0x1C NL_X

(1920 registers, 8 bits each) 7..0 N/A

0x1D NL_Y (1200 registers, 8 bits each)

7..0 N/A

7.3 Video Path Registers

7.3.1 General Address Register Name Bits Bit Group Name Reset

Value 0 VIN_FILTER_BYPASS 1 1 VDSCALER_BYPASS 1 2 VUSCALER_BYPASS 1 3 DI_BYPASS 1 4 VOUT_FILTER_BYPASS 1 5 CLK_BLOCK_MODE 0

0x1E VIDEO_CONFIG

7..6 Reserved N/A 1..0 RATE_RELATION 0x2 2 Must be ‘0’ 0 3 THRESHOLD_DISABLE 1 4 STORE_ONE_FIELD 0 5 THRESHOLD_MODE 0

0x1F VIDEO_SC

7..6 Reserved N/A



7.3.2 Video Port Interface Address Register Name Bits Bit Group Name Reset

Value 0 V_VSYNC 0 1 V_HSYNC 0 2 V_ACTIVE 0 3 V_VALID 0 4 V_FIELD 0 5 VCLK 0

0x20 VIN_POLARITY

7..6 Reserved N/A 0 VMODE656 0 1 VIN_8BIT 0 2 CBLANK 0

0x21 VIN_CONTROL

7..3 Reserved N/A 0x22 VIN_ACTIVE_PIXELS_L

(Read only) 7..0 N/A

0x23 VIN_ACTIVE_LINES_L (Read only)

7..0 N/A

0x24 VIN_FLAGGED_LINE_L (Read only)

7..0 N/A

1..0 VIN_ACTIVE_PIXELS_H N/A 2 VIN_ACTIVE_LINES_H N/A 3 VIN_FLAGGED_LINE_H N/A

0x25 VIN_REGS_MSBITS (Read only)

7..4 Reserved N/A

7.3.3 Video In Filter Address Register Name Bits Bit Group Name Reset

Value 7..0 C0 0x00 7..0 C1 0x00 7..0 C2 0x00 7..0 C3 0x00 7..0 C4 0x40 7..0 C5 0x00 7..0 C6 0x00 7..0 C7 0x00 7..0 C8 0x00 1..0 C4_LSB 0x00 7..0 CORING_LEVEL 0x00

0x26 VIN_FILTER_GRP (12 registers group)

7..0 YDIF_LEVEL 0x00

7.3.4 Video Out Filter Address Register Name Bits Bit Group Name Reset


0x27 VOUT_FILTER_GRP (12 registers group)




7.3.5 Video CTI Address Register Name Bits Bit Group Name Reset

Value 0 Reserved N/A 2..1 COEF_RANGE 0x2 3 CTI_ENABLE 0

0x28 VIN_CTI_CONTROL

7..4 Reserved N/A 7..0 C0 0x20 7..0 C1 0x00 7..0 C2 0x00 7..0 C3 0x00 7..0 C4 0x00

0x29 VIN_CTI_GRP (6 registers group)

7..0 C5 0x00

7.3.6 Video Down Scaler Address Register Name Bits Bit Group Name Reset

Value 0x2A VDSCALER_TOUTX_L

(S) 7..0 0x00

2..0 0x0 0x2B VDSCALER_TOUTX_H (S) 7..3 Reserved N/A

0 Y_BYPASS 1 1 X_BYPASS 1 2 NL_Y_ENABLE 0 3 Reserved N/A 4 Must be '0' 0

0x2C VDSCALER_CONTROL (S)

7..5 Reserved N/A 0x2D VDSCALER_DELTAX_L

(S) 7..0 0x00

0x2E VDSCALER_DELTAX_H (S)

7..0 0x08

0x2F VDSCALER_DELTAY_L (S)

7..0 0x00

0x30 VDSCALER_DELTAY_H (S)

7..0 0x08

5..0 0x00 0x31 VDSCALER_Y0 (S) 7..6 Reserved N/A

5..0 0x00 0x32 VDSCALER_X0 (S) 7..6 Reserved N/A

0x33 VDSCALER_TOUTY_L (S)

7..0 0x00

2..0 0x0 0x34 VDSCALER_TOUTY_H (S) 7..3 Reserved N/A



7.3.7 Video Up Scaler Address Register Name Bits Bit Group Name Reset

Value 0 Y_BYPASS 1 1 X_BYPASS 1 2 NL_Y_ENABLE 0 3 NL_X_ENABLE 0

0x35 VUSCALER_CONTROL (S)

7..4 Reserved N/A 0x36 VUSCALER_DELTAX_L

(S) 7..0 0x00

3..0 0x8 0x37 VUSCALER_DELTAX_H (S) 7..4 Must be 0x0 0x0

0x38 VUSCALER_DELTAY_L (S)

7..0 0x00

3..0 VUSCALER_DELTAY_H 0x8 5..4 V_VSYNC_DELAY 0x0 6 V_VSYNC_DELAY_TRIG_MODE 0

0x39 VUSCALER_DELTAY_H (S)

7 DOUBLE_DELTAY_MODE 0 5..0 0x00 0x3A VUSCALER_Y0

(S) 7..6 Reserved N/A 5..0 0x00 0x3B VUSCALER_X0

(S) 7..6 Reserved N/A

7.3.8 Video De-interlacer (DI) Address Register Name Bits Bit Group Name Reset

Value 1..0 MODE 0x0 2 Must be '1' 1 3 Must be '0' 0

0x3C DI_CONTROL

7..4 Reserved N/A 0x3D DI_C0 5..0 0x04 0x3E DI_C1 2..0 0x02 0x3F DI_C2 6..0 0x5A 0x40 DI_C3 7..0 0xC5 0x41 DI_C4 4..0 0x0D

7.4 Graphics Path (or Data Path) Registers

7.4.1 General Address Register Name Bits Bit Group Name Reset

Value 0 DIN_YUV_422 0 1 YUV_CSC_BYPASS 0 2 DIN_FILTER_BYPASS 1 3 DDSCALER_BYPASS 1 4 DUSCALER_BYPASS 1 5 SDRAM_BYPASS_MODE 0 6 IDATA_MODE_ENABLE 0

0x42 DATA_CONFIG

7 CLK_BLOCK_MODE 0 1..0 RATE_RELATION 0x2 2 Must be ‘0’ 0 3 THRESHOLD_DISABLE 1 4 STORE_ONE_FIELD 0 5 THRESHOLD_MODE 0 6 DI_AT_MEMORY 0

0x43 DATA_SC

7 Reserved N/A



7.4.2 Graphics Port Interface Address Register Name Bits Bit Group Name Reset

0 1 0 2 D_VALID 0 3 D_FIELD 0 4 D_HSYNC 1 5 D_VSYNC 1 6 INV 0

DIN_POLARITY_0

7 Reserved 0 0 CLAMP 1 COAST 7..2 Reserved N/A

DUAL_INPUT 0 DIN_PARALLEL 0 DCLK_DIV 1 BI_PHASE_CLK 0 Must be '0' 0 Must be '0' 0 D_VALID_ENABLE 0

0x46

EXT_ACTIVE 0 0 Must be '0' 0 1 SAMPLE_SHIFT 0

Value DIN_CLK 0 0x44 D_ACTIVE

0 0

0x45 DIN_POLARITY_1

0 1

DIN_CONTROL_0

2 3 4 5 6 7

0x47 DIN_CONTROL_1

5..2 Must be '0000' 0x2 6 VSYNC_DELAY_ENABLE 0 7 Must be '1' 1 0 HINTERLACE_MODE 0 1 Must be '1' 0 2 INV_SET 0

EXTERNAL_FIELD 0 4 INTERLACE_MODE 0 5 INTERLACED_DETECT_ENABLE 0 6 COAST_ENABLE 0

0x48 DIN_CONTROL_2

7 CBLANK_N 0 0x4B DIN_THRESHOLD

7..0 0x08

0x4C CLAMP_START

7..0 0x00

0x4D CLAMP_WIDTH

7..0 0x00

0x4E DIN_LINE_TRIG

7..0 0x01

0x4F DIN_PIXEL_TRIG

7..0 0x08

7..0 ACTIVE_LINE_START_L 0x0A 2..0 ACTIVE_LINE_START_H 0x0 7..0 ACTIVE_LINES_L 0xE0 2..0 ACTIVE_LINES _H 0x1 7..0 ACTIVE_PIXEL_START_L 0x40 2..0 ACTIVE_PIXEL_START_H 0x0 7..0 ACTIVE_PIXELS_L 0x80

0x50 DIN_ACTIVE_REGION_GRP (4 registers, 11 bits each)

2..0 ACTIVE_PIXELS _H 0x2 0x51 DIN_FLAGGED_LINE_L

(Read only) 7..0 0x00

2..0 0x0 0x52 DIN_FLAGGED_LINE_H (Read only) 7..3 Reserved N/A

3



Address Register Name Bits Bit Group Name Reset Value

0 D_INB_SELECT 0 1 Must be '1' 0 2 Must be '0' 0 3 Y_DIFF_MODE 0 4 RAW_HSYNC_MSR_SELECT 0 5 ACTIVE_PIXEL_START_LSB_ENABLE 0 6 EXT_ACTIVE_NO_CLIPPING 0

0x53 DIN_CONTROL_3

7 Y_ON_GREEN 0 5..0 D_VSYNC_DELAY 0x00 0x54 D_VSYNC_DELAY

7..6 Reserved N/A

7.4.3 Graphics CTI Address Register Name Bits Bit Group Name Reset

Value 0 Must be '1' 1 2..1 COEF_RANGE 0x2 3 CTI_ENABLE 0

0x55 DIN_CTI_CONTROL

7..4 Reserved N/A 7..0 C0 0x20 7..0 C1 0x00 7..0 C2 0x00 7..0 C3 0x00 7..0 C4 0x00

0x56 DIN_CTI_GRP (6 register group)

7..0 C5 0x00

7.4.4 Graphics Filter Address Register Name Bits Bit Group Name Reset


0x57 DIN_FILTER_GRP (12 register group, 8 bits each)




7.4.5 Graphics Down Scaler Address Register Name Bits Bit Group Name Reset

Value 0x58 DDSCALER_TOUTX_L

(S) 7..0 0x00

2..0 0x0 0x59 DDSCALER_TOUTX_H (S) 7..3 Reserved N/A

0 Y_BYPASS 1 1 X_BYPASS 1 2 NL_Y_ENABLE 0

0x5A DDSCALER_CONTROL (S)

7..3 Reserved N/A 0x5B DDSCALER_DELTAX_L

(S) 7..0 0x00

0x5C DDSCALER_DELTAX_H (S)

7..0 0x08

0x5D DDSCALER_DELTAY_L (S)

7..0 0x00

0x5E DDSCALER_DELTAY_H (S)

7..0 0x08

0x61 DDSCALER_TOUTY_L (S)

7..0 0x00

2..0 0x0 0x62 DDSCALER_TOUTY_H (S) 7..3 Reserved N/A

7.4.6 Graphics Up Scaler Address Register Name Bits Bit Group Name Reset

Value 0 Y_BYPASS 1 1 X_BYPASS 1 2 NL_Y_ENABLE 0 3 NL_X_ENABLE 0

0x63 DUSCALER_CONTROL (S)

7..4 Reserved N/A 0x64 DUSCALER_DELTAX_L

(S) 7..0 0x00

3..0 0x08 0x65 DUSCALER_DELTAX_H (S) 7..4 Must be 0x0 0

0x66 DUSCALER_DELTAY_L (S)

7..0 0x00

3..0 DUSCALER_DELTAY_H 0x08 6..4 Reserved 0

0x67 DUSCALER_DELTAY_H (S)

7 DOUBLE_DELTAY_MODE 0 5..0 0x00 0x68 DUSCALER_X0

(S) 7..6 Reserved N/A 5..0 0x00 0x69 DUSCALER_Y0

(S) 7..6 Reserved N/A



7.5 Output Path Registers

7.5.1 Output Windows Address Register Name Bits Bit Group Name Reset

Value 7..0 Y_POSITION_L 0x01 2..0 Y_POSITION_H 0x0 7..0 Y_SIZE_L 0xE0 2..0 Y_SIZE_H 0x1 7..0 X_POSITION_L 0x01 2..0 X_POSITION_H 0x0 7..0 X_SIZE_L 0x80

0x6B VIDEO_WINDOW_GRP (4 registers, 11 bits each) (S)

2..0 X_SIZE_H 0x2 7..0 Y_POSITION_L 0x01 2..0 Y_POSITION_H 0x0 7..0 Y_SIZE_L 0xE0 2..0 Y_SIZE_H 0x1 7..0 X_POSITION_L 0x01 2..0 X_POSITION_H 0x0 7..0 X_SIZE_L 0x80

0x6C DATA_WINDOW_GRP (4 registers, 11 bits each) (S)

2..0 X_SIZE_H 0x2 7..0 Y_POSITION_L 0x01 2..0 Y_POSITION_H 0x0 7..0 Y_SIZE_L 0x00 2..0 Y_SIZE_H 0x0 7..0 X_POSITION_L 0x01 2..0 X_POSITION_H 0x0 7..0 X_SIZE_L 0x00

0x6D OSDA_WINDOW_GRP (4 registers, 11 bits each)

2..0 X_SIZE_H 0x0 7..0 Y_POSITION_L 0x01 2..0 Y_POSITION_H 0x0 7..0 Y_SIZE_L 0x00 2..0 Y_SIZE_H 0x0 7..0 X_POSITION_L 0x01 2..0 X_POSITION_H 0x0 7..0 X_SIZE_L 0x00

0x6E OSDB_WINDOW_GRP (4 registers, 11 bits each)

2..0 X_SIZE_H 0x0

7.5.2 YUV Lookup Tables Address Register Name Bits Bit Group Name Reset

Value 0x6F LUT_Y

(512 registers, 8 bits each, first 256 registers for video, last 256 registers for graphics)

7..0 N/A

0x70 LUT_U (512 registers, 8 bits each, first 256 registers for video, last 256 registers for graphics)

7..0 N/A

0x71 LUT_V (512 registers, 8 bits each, first 256 registers for video, last 256 registers for graphics)

7..0 N/A



7.5.3 RGB Lookup Tables Address Register Name Bits Bit Group Name Reset

Value 7..0 LUT_R_L N/A 0x72 LUT_R

(256 registers, 10 bits each) 1..0 LUT_R_H N/A 7..0 LUT_G_L N/A 0x73 LUT_G

(256 registers, 10 bits each) 1..0 LUT_G_H N/A 7..0 LUT_B_L N/A 0x74 LUT_B

(256 registers, 10 bits each) 1..0 LUT_B_H N/A

7.5.4 Palette Tables Address Register Name Bits Bit Group Name Reset

Value 0x75 PALETTE_R

(256 registers, 8 bits each) 7..0 N/A

0x76 PALETTE_G (256 registers, 8 bits each)

7..0 N/A

0x77 PALETTE_B (256 registers, 8 bits each)

7..0 N/A

7.5.5 RGB Color Space Converters Address Register Name Bits Bit Group Name Reset

Value 0x78 VIDEO_CSC_BIAS

(S) 7..0 0xF0

7..0 C0_L 0xA8 2..0 C0_H 0x4 7..0 C1_L 0x00 2..0 C1_H 0x0 7..0 C2_L 0x99 2..0 C2_H 0x1 7..0 C3_L 0xA8 2..0 C3_H 0x4 7..0 C4_L 0xB1 2..0 C4_H 0x7 7..0 C5_L 0x30 2..0 C5_H 0x7 7..0 C6_L 0xA8 2..0 C6_H 0x4 7..0 C7_L 0x05 2..0 C7_H 0x2 7..0 C8_L 0x00

0x79 VIDEO_CSC_GRP (9 registers, 11 bits each) (S)

2..0 C8_H 0x0 0x7A DATA_CSC_BIAS

(S) 7..0 0x00

0x00 0x4 0x00

2..0 C1_H 0x0 7..0 C2_L 0x67 2..0 C2_H 0x1 7..0 C3_L 0x00 2..0 C3_H 0x4 7..0 C4_L 0xA8 2..0 C4_H 0x7

0x7B

DATA_CSC_GRP (9 registers, 11 bits each) (S)

7..0 C5_L 0x49

7..0 C0_L 2..0 C0_H 7..0 C1_L




2..0 C5_H 0x7 7..0 C6_L 0x00 2..0 C6_H 0x4 7..0 C7_L 0xC6 2..0 C7_H 0x1 7..0 C8_L 0x00

0x7B (cont)

2..0 C8_H 0x0

7.5.6 General Output Path Address Register Name Bits Bit Group Name Reset

Value 0 DITHER_ENABLE 0 1 KEYSTONE_ENABLE 0 2 RGB_LUT_BYPASS 1 3 YUV_LUT_BYPASS 1

CSC_BYPASS 0

0x7C OUT_CONFIG (S)

7..5 Reserved N/A 7..0 BLUE 0xC0 7..0 GREEN 0x00

0x7D BACKGROUND_GRP (3 registers, 8 bits each)

7..0 RED 0x00

4

7.5.7 OSD Address Register Name Bits Bits Group Name Reset

Value 1..0 MULT_Y 0x0 3..2 MULT_X 0x0 4 SHIFT 0 5 GRID 0

0x7E OSDA_CONTROL

7..6 Reserved N/A 1..0 MULT_Y 0x0 3..2 MULT_X 0x0 4 SHIFT 0 5 GRID 0

0x7F OSDB_CONTROL

7..6 Reserved N/A

7.5.8 Keystone Address Register Name Bits Bit Group Name Reset

Value 0 CEILING 0 0x80 KEYSTONE_CONTROL

7..1 Reserved N/A 0x81 KEYSTONE_LINES

(S) 7..0 0xFF

7.5.9 Dither Address Register Name Bits Bit Group Name Reset

Value 1..0 DITHER865_B 0x2 3..2 DITHER865_G 0x2 5..4 DITHER865_R 0x2 6 Must be '1' 0

0x82 DITHER_CONTROL

7 Reserved N/A 0x83 DITHER_C0 7..0 0x3C 0x84 DITHER_C1 7..0 0x38



7.5.10 Display Interface Address Register Name Bits Bit Group Name Reset

Value 1..0 LOCK_MODE 0x0 2 INTERLACE_MODE 0 3 YUV_FORMAT 0 5..4 VSYNC_SOURCE 0x0 6 DUAL_PIXEL 0

DISPLAY_CONTROL_0 (S)

7 HSYNC_CONTINUOUS_MODE 0 OP_FIELD_LOCK 0 1 OP_FIELD_SOURCE 0 2 OP_FIELD_SIGNAL 0 3 OP_FIELD_3D_SOURCE 0

OP_ENABLE_LATENCY 0x0 6 Y_ON_GREEN 0

0x86 DISPLAY_CONTROL_1

7 COMP_SYNC 0 0 DISPLAY_ENABLE 0 1 DISPLAY_PORT_OE 0

0x87 DISPLAY_CONTROL_2

7..2 Reserved N/A 7..0 VSYNC_CYCLE_L 0x1E 3..0 VSYNC_CYCLE_H 0x0

HSYNC_CYCLE _L 0x32 3..0 HSYNC_CYCLE_H 0x0 5..0 VSYNC_WIDTH 0x03 7..6 VSYNC_OFFSET_L 0x0 3..0 VSYNC_OFFSET_H 0x0 7..0 HSYNC_WIDTH_L 0x03 3..0 HSYNC_WIDTH_H 0x0 7..0 ACTIVE_LINE_START_L 0x0D 3..0 ACTIVE_LINE_START_H 0x0 7..0 ACTIVE_LINES_L 0x0A 3..0 ACTIVE_LINES_H 0x0 7..0 ACTIVE_PIXEL_START_L 0x04 3..0 ACTIVE_PIXEL_START_H 0x0 7..0 ACTIVE_PIXELS_L 0x10

0x88 DISPLAY_FRAME_GRP (8 registers, 12 bits each)

3..0 ACTIVE_PIXELS_H 0x0 0x89 DISPLAY_HV_DELAY_0 7..0 0x01 0x8A DISPLAY_HV_DELAY_1 7..0 0x01

0 OP_VSYNC 0 1 OP_HSYNC 0

0 3 OP_ENABLE 0 4 OCLK_OUT 0 5 OCLK_IN 0 6 OP_FIELD_3D 0

0x8B DISPLAY_POLARITY

7 Reserved N/A 0 ENABLE 0 2..1 MODE 0x0 3 SEPARATE_TABLES 0

0x8C CONTROL_3D

7..4 SHIFT 0x0 5..0 0x00 0x8D X0_3D 7..6 Reserved N/A

0x85

0

5..4

7..0

2 OP_FIELD



7.6 SDRAM Control Address Register Name Bits Bit Group Name Reset

Value 7..0 VIDEO0_L

(DIE_VERSION after reset) 0x03

3..0 VIDEO0_H 0x0 7..0 VIDEO1_L 0x00 3..0 VIDEO1_H 0x1 7..0 VIDEO2_L 0x00 3..0 VIDEO2_H 0x2 7..0 LDATA0_L 0x00 3..0 LDATA0_H 0x3 7..0 RDATA0_L 0x00 3..0 RDATA0_H 0x4 7..0 LDATA1_L 0x00

0x5 7..0 RDATA1_L 0x00 3..0 RDATA1_H 0x6 7..0 OSD0_L 0x00 3..0 OSD0_H 0x7 7..0 OSD1_L 0x40 3..0 OSD1_H 0x7 7..0 OSD2_L 0x80 3..0 OSD2_H 0x7 7..0 OSD3_L 0xC0 3..0 OSD3_H 0x7 7..0 IDATA_OFFSET_L 0x60

0x90 SECTION_START_GRP (12 registers, 12 bits each)

3..0 IDATA_OFFSET_H 0x0 7..0 VIDEO_L 0x00 1..0 VIDEO_H 0x0 7..0 DATA_L 0x00 1..0 DATA_H 0x0 7..0 IDATA_L 0x00 1..0 IDATA_H 0x0 7..0 OSD0_L 0x00 1..0 OSD0_H 0x0

0x00 0x0

7..0 OSD2_L 0x00 1..0 OSD2_H 0x0 7..0 OSD3_L 0x00

0x91 LINE_LENGTH_GRP

OSD3_H

(7 registers, 10 bits each)

1..0 0x0 7..0 VIDEO_L 0x00 2..0 VIDEO_H 0x0 7..0 DATA_L 0x00 2..0 DATA_H 0x0 7..0 OSDA_L 0x00

0x0 7..0 OSDB_L 0x00

0x92 WINDOW_LINE_OFFSET_GRP (4 registers, 11 bits each) (S)

2..0 OSDB_H 0x0

3..0 LDATA1_H

7..0 OSD1_L 1..0 OSD1_H

2..0 OSDA_H



Address Register Name Bits Bit Group Name Reset

Value 0x00

1..0 VIDEO_H 0x0 7..0 DATA_L 0x00 1..0 DATA_H

0x00 1..0 OSDA_H 0x0 7..0 OSDB_L 0x00

WINDOW_DELAY_GRP (4 registers, 10 bits each) (S)

1..0 OSDB_H 0x0 7..0 VIDEO_L 0x00 1..0 VIDEO_H 0x0 7..0 DATA_L 0x00 1..0 DATA_H 0x0 7..0 OSDA_L 0x00 1..0 OSDA_H 0x0 7..0 OSDB_L 0x00

0x94 WINDOW_LENGTH_GRP (4 registers, 10 bits each) (S)

1..0 OSDB_H 0x0 7..0 VIDEO_IN 0x80 7..0 VIDEO_OUT 0x20 7..0 DATA_IN 0x20

0x95 SC_THRESHOLD_GRP (4 registers, 8 bits each) (S)

7..0 DATA_OUT 0x20 0x96 OSD_IN_ADDR_L 7..0

7..0 0x00 7..0 1..0 OSDA_OUT 0x0 3..2 OSDB_OUT 0x1 5..4 OSD_IN 0x0

0x99 OSD_SECTIONS

7..6 Reserved N/A 0x9A OSD_IN_DATA

(Write only) 7..0 N/A

0 WEN 0 0x9B OSD_IN_CONTROL 7..1 Reserved (Write only) N/A

0 3..2 DATA_WINDOW 0 5..4 OSDA_WINDOW 0 7..6 OSDB_WINDOW 0 0 MODE_A10 0 1 MODE_BS 0 2 MODE_A11 0

0x9D SDRAM_INIT

7..3 Reserved N/A

(Write only)

0x0 0x9E OSD_IN_ADDR_MSBITS Reserved 7..2 N/A

7..0 VIDEO_L

0x0 7..0 OSDA_L

0x93

0x00 0x97 OSD_IN_ADDR_H 0x98 OSD_IN_BLOCK_LENGTH 0x00

1..0 VIDEO_WINDOW 0x9C SDRAM_WINDOW_CONTROL (S)

1..0 OSD_IN_ADDR_MSBITS

7.7 Measurement Unit Address Register Name Bits Bit Group Name

7..0 LINE_START_L 0x00 5..0 LINE_START_H 0x00 7..0 LINE_END_L 0x00 5..0 LINE_END_H 0x00 7..0 PIXEL_START_L 0x00 5..0 PIXEL_START_H 0x00 7..0 PIXEL_END_L 0x00

0xA0 MSR_AOI_GRP (4 registers, 14 bits each)

5..0 PIXEL_END_H 0x00

Reset Value




0 OUT_PORT_SELECT 0 1 REF_MODE_SELECT 0 2 CLK_SELECT 0 3 VSYNC_CLK_SELECT 1 4 CONTINUOUS_MODE 0 5 STORAGE_MODE 0 6 AOI_LIMIT_DISABLE 1

0xA1 MSR_CONTROL

7 Reserved N/A 0 DIN 0 1 OUT_PORT 0 7..2 Reserved N/A

MSR_STATUS (Read only)

7 HSYNC_WIDTH_L

N/A

N/A N/A N/A

N/A

(5 registers, 14 bits each,

5..0 LINE_START_H N/A 7..0 LINE_END_L N/A 5..0 LINE_END_H N/A 7..0 PIXEL_START_L N/A 5..0 PIXEL_START_H N/A 7..0 PIXEL_END_L

MSR_ACTIVE_REGION_GRP

5..0 0xA7 MSR_MIN

(Read only) 7..0 0xFF

0xA8 MSR_MAX (Read only)

7..0 0x00

1..0 DIN_COMPONENT_SELECT 0x0 2 VIN_MSR_SELECT 0

V_ACTIVE_SIGNAL_SELECT 0

0xA9 MSR_CONTROL2

7..4 Reserved N/A

0xA2 MSR_ENABLE

0 START_MEASURE N/A 1 CLEAR_RESULTS N/A

0xA3 MSR_COMMANDS (Write only)

7..2 Reserved N/A 0 MEASURE_READY N/A 1 DIN_EXIST 0 2 DIN_INTERLACED N/A 3 HSYNC_POLARITY N/A 4 VSYNC_POLARITY N/A 5 VIN_EXIST 0 6 OUT_EXIST 0

0xA4

OUT_INTERLACED N/A 7..0 N/A 5..0 HSYNC_WIDTH_H 7..0 HSYNC_CYCLE_L N/A 5..0 HSYNC_CYCLE_H 7..0 VSYNC_WIDTH_L 5..0 VSYNC_WIDTH_H 7..0 VSYNC_CYCLE_L N/A 5..0 VSYNC_CYCLE_H 7..0 HV_DELAY_L N/A

0xA5 MSR_HV_PARAMETERS_GRP

read only)

5..0 HV_DELAY_H N/A 7..0 LINE_START_L N/A

N/A

0xA6 (4 registers, 14 bits each, read only)

PIXEL_END_H N/A

3



7.8 Miscellaneous Address Register Name Bits Bit Group Name Reset

Value 0xAA CHIP_ID 7..0 CHIP_ID 0x03

0 B_00_DETECT N/A 1 G_00_DETECT N/A 2 R_00_DETECT N/A 3 B_FF_DETECT N/A 4 G_FF_DETECT N/A 5 R_FF_DETECT N/A

0xAB DETECT_FF_00 (Read only)

7..6 Reserved N/A



Page Break


Rembrandt-102 Data Sheet Package Information 8 Package Information

1A


Packaging Information Rembrandt-102 Data Sheet

Blank Page


Rembrandt-102 Data Sheet Reflow Profile

9 Reflow Profile

Ramp: 1.5 - 2 °C/sec

Time (sec)

RoomTemp

VPR: 215 - 219 °CIR/Convection: 220 - 225 °C10 - 20 sec

240 - 300 sec

60 - 120 sec 60 - 150 sec

Max ramp: 6 °C/sec

>183°C

SurfaceTemp(°C)

125 - 150 °C

Figure 17: SMD Reflow Profile


Reflow Profile Rembrandt-102 Data Sheet

Blank Page


Rembrandt-102 Data Sheet Appendix 1: RM102 Comparison to RM1A

10 Appendix 1: RM102 Comparison to RM1A # Function Description Registers in RM102

1 Video CTI Add CTI to the video path for color transition improvement

VIN_CTI_CONTROL VIN_CTI_GRP ADDR_CLEAR_0. VIN_CTI

2 Data CTI Add CTI to the data path for color transition improvement

DIN_CTI_CONTROL DIN_CTI_GRP |ADDR_CLEAR_0. DIN_CTI

3 Filter Overshoot Limiter

Add limiter to all three filters CONFIG2. VIDEO_FILTER_LIMITER_ENABLE CONFIG2. DATA_FILTER_LIMITER_ENABLE

4 Filter C4 (Center Coefficient) Range

For all three filters: Normal range (8 bits): -2 to +1.984 Increased range (10 bit): -8 to +7.984

CONFIG2. VIN_FILTER_C4_10BITS CONFIG2. VOUT_FILTER_C4_10BITS CONFIG2. DIN_FILTER_C4_10BITS VIN_FILTER_GRP. C4_LSB VOUT_FILTER_GRP. C4_LSB DIN_FILTER_GRP. C4_LSB

5 Filter Coring Add coring function to all three filters, to limit noise in low luminance pixels.

VIN_FILTER_GRP. CORING_LEVEL VOUT_FILTER_GRP. CORING_LEVEL DIN_FILTER_GRP. CORING_LEVEL

6 Filter Noise Limiter Add noise limiter function to all three filters, to limit noise in areas with low luminance change.

VIN_FILTER_GRP. YDIF_LEVEL VOUT_FILTER_GRP. YDIF_LEVEL DIN_FILTER_GRP. YDIF_LEVEL

7 Conversion to YUV 4:4:4

Improve YUV 4:2:2 to YUV 4:4:4 conversion.

8 SDRAM Clock Rate and Data Bus Width

Increase SDRAM maximum clock (mclk) rate from 100 MHz to 125 MHz. Add 64 bit bus option.

CONFIG1. SDRAM_CONFIG

9 OSD Size Increase OSD line length from 960 to 1920 pixels. Increase OSD load address range from 64K to 256K memory words.

OSD_IN_ADDR_MSBITS

10 OSD Load Busy Fix OSD_LOAD_BUSY status bit. STATUS2. OSD_LOAD_BUSY 11 Raw Hsync Measure Add pin D_CSYNC for

connection to raw Hsync (SOG of ADC), and add measure of raw Hsync for format detection

DIN_CONTROL_3. RAW_HSYNC_MSR_SELECT

12 Video Measure Add active region and min/max measure (within area of interest) to video luminance input

MSR_CONTROL2. VIN_MSR_SELECT MSR_CONTROL2. V_ACTIVE_REGION_SELECT

13 Data R,G,B Measure Add active region and min/max measure (within area of interest) to selected R/G/B input component.

MSR_CONTROL2. DIN_COMPONENT_SELECT

14 Hsync Measurement Improve Hsync cycle and pulse width measure for graphics input interlaced sources

MSR_HV_PARAMETERS_GRP. HSYNC_WIDTH MSR_HV_PARAMETERS_GRP. HSYNC_CYCLE

15 Y on Green for Data Input Port and for Display Port

Add Y on Green mode, in addition to Y on Red, for both graphics and display ports.

DIN_CONTROL_3. Y_ON_GREEN DISPLAY_CONTROL_1. Y_ON_GREEN

16 One Pixel Resolution at Data Input Positioning

Do not ignore l.s.bit of DIN_ACTIVE_REGION_GRP. ACTIVE_PIXEL_START

DIN_CONTROL_3. ACTIVE_PIXEL_START_LSB_ENABLE

17 Flexible Horizontal Positioning

Enable active pixels to extend beyond next D_HSYNC ("rolling positioning")

18 Fix Two Pixels Clipping in EXT_ACTIVE Mode

Do not clip graphics port first two pixels in a line when EXT_ACTIVE = '1'

DIN_CONTROL_3. EXT_ACTIVE_NO_CLIPPING

19 CBLANK_N When EXT_ACTIVE='1' external source can mark active pixels (D_VALID) and active lines (D_ACTIVE) with two separate input pins.

DIN_CONTROL_2. CBLANK_N

20 D_VSYNC Delay Add programmable delay on D_VSYNC input

D_VSYNC_DELAY

21 DI at Memory Add temporal de-interlacing (DI) in SDRAM, for use with graphics interlaced sources.

DATA_SC. DI_AT_MEMORY


Packaging Information Rembrandt-102 Data Sheet

# Function Description Registers in RM102 22 Load Shadow Done Add interrupt when load shadow

is internally completed IRQ_SOURCE. LOAD_SHADOW_DONE IRQ_MASK. LOAD_SHADOW_DONE

23 Video Crossing Add Flag on Video Crossing - to signal frame tearing.

FLAGS. VIDEO_CROSSING

24 PLL Division Factor NDIV value of all PLLs should not be greater than 12.

MPLL_NDIV PPLL_NDIV OPLL_NDIV

25 OCLK PLL Control Control post div, clock range (FRANGE) and clock de-skew.

OPLL_CONTROL

26 Pins Control - Enable display port skew to reduce current surge and EMI. - Enable fast/slow slew rate on display port pins. - Enable zero hold time for external sampling of display port signals.

PINS_CONTROL

27 Section Control Threshold Mode

For "input higher" rate relation, add a mode where display frame line counter is compared to the threshold

VIDEO_SC. THRESHOLD_MODE DATA_SC. THRESHOLD_MODE

28 OP_HSYNC modes Add continuous OP_HSYNC mode, when lock mode is equal to LOCK_VS. Add Composite sync output.

DISPLAY_CONTROL_0. HSYNC_CONTINUOUS_MODE DISPLAY_CONTROL_1. COMP_SYNC

29 DETECT_FF_00 Detect output pixels with 0xFF and 0x00 value, to assist in dynamic range adjustment

DETECT_FF_00

30 Remove Graphics Port Unused Functions from RM1A

Remove external PLL support. Remove overflow control pins.
