saro: a state-aware reliability optimization technique for

SARO: A State-Aware Reliability Optimization Technique forHigh Density NAND Flash Memory

Myungsuk KimDepartment of Computer Science and Engineering

Seoul National [email protected]

Youngsun SongDepartment of Computer Science and Engineering


Myoungsoo JungSchool of Integrated Technology

Yonsei [email protected]

Jihong KimDepartment of Computer Science and Engineering


ABSTRACTRecent advances in flash technologies, such as scaling and multi-leveling schemes, have been successful to make flash denser andsecure more storage spaces per die. Unfortunately, these technologyadvances significantly degrade flash’s reliability due to a smallercell geometry and a finer-grained cell state control. In this paper, wepropose a state-aware reliability optimization technique (SARO),new flash optimization that improves the flash reliability underdiverse scaling and multi-leveling schemes. To this end, we firstreveal that reliability-related flash errors are highly skewed amongflash cell states, which was not captured by prior studies. Theproposed SARO exploits then the different per-state error behaviorin flash cell states by selecting the most error-prone flash states(for each error type) and by forming narrow threshold voltagedistributions (for the selected states only). Furthermore, SARO isapplied only when the program time gets shorter because of flashcell aging, thereby keeping the program latency unchanged. Ourexperimental results with real MLC and TLC flash devices showthat SARO can reduce a significant number of flash bit errors, whichcan in turn reduce the read latency by 40%, on average.ACM Reference Format:Myungsuk Kim, Youngsun Song, Myoungsoo Jung, and Jihong Kim. 2018.SARO: A State-Aware Reliability Optimization Technique for High DensityNAND Flash Memory. In GLSVLSI’18: 2018 Great Lakes Symposium on VLSI,May 23–25, 2018, Chicago, IL, USA. ACM, New York, NY, USA, 6 pages.https://doi.org/10.1145/3194554.3194591

1 INTRODUCTIONMany recent advances and innovations in flash technologies (suchas 3D flash, 10-nm node process, and TLC cells) enabled dramaticincreases in the flash memory capacity. However, the fundamentalrelationship between the capacity and reliability of flash memoryremains unchanged: the higher the flash chip capacity, the lowerthe flash reliability 1. As the feature size of technologies shrinks,neighboring flash cells are getting closer and located in a smaller1Over 2D flash, 3D flash is more reliable with a higher capacity. However, within 3Dflash, this relationship still holds.

Permission to make digital or hard copies of all or part of this work for personal orclassroom use is granted without fee provided that copies are not made or distributedfor profit or commercial advantage and that copies bear this notice and the full citationon the first page. Copyrights for components of this work owned by others than ACMmust be honored. Abstracting with credit is permitted. To copy otherwise, or republish,to post on servers or to redistribute to lists, requires prior specific permission and/or afee. Request permissions from [email protected]’18, May 23–25, 2018, Chicago, IL, USA© 2018 Association for Computing Machinery.ACM ISBN 978-1-4503-5724-1/18/05. . . $15.00https://doi.org/10.1145/3194554.3194591

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space geometry. Unfortunately, a narrow spacing between adjacentcells tend to be more vulnerable to noise effects such as cell-to-cellinterference, thus lowering the flash reliability [1]. In addition, them-bit multi-leveling technique (e.g., 3-bit triple-level cell (TLC))significantly lowers the flash reliability because it increases thestorage capacity by distinguishing the same threshold voltage (Vth )distribution of a cell transistor with 2m different states. Since ahigherm allows a smaller noise margin (between the adjacent cells),the m-bit multi-leveling technique degrades the flash reliability,compared to the single-level cell (SLC) flash device.

Figure 1 shows how the flash reliability has deteriorated byprocess scaling andm-bit multi-leveling techniques, which havebeen the driving force behind the recent growth in the storagecapacity in flash. For example, while flash’s storage capacity wasincreased from 8G bits to 128G bits, the flash endurance has beenworsened by 10 times. To handle the poor reliability introducedby such advanced techniques, a flash controller should employ40-bit error correction codes (ECC) rather than 4-bit ECC at thesystem-level.

To secure a better reliability in flash, a straightforward approachis to keep Vth distributions of adjacent program states as distantas possible so that the interference between neighboring cells canbe minimized. One simple technique is to reduce the Vth widthof each program state. Although narrowing Vth distributions forprogram states makes program states error-resistant, it slows downthe program speed because a program step voltage (Vispp ) shouldbe reduced for forming a narrow Vth distribution. Since Vispp isinversely proportional to the program latency, it is inevitable tosacrifice the program latency if the reliability is improved in a waythat reducesVispp . Furthermore, many emerging applications (suchas real-time big-data analytics, autonomous cars and virtual-realityapplications) require both high capacity and high performance from

Session 10: Memory Architectures GLSVLSI’18, May 23-25, 2018, Chicago, IL, USA

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Figure 2: Vth distributions of 2m-state flash memory.flash-based storage systems, thus making it even less desirable toimprove the flash reliability by slowing down the program latency.

In this paper, we propose a new NAND flash reliability opti-mization technique that addresses the reliability issue of high den-sity flash memories without sacrificing their program latency. Ourproposed technique, called as state-aware reliability optimization(SARO), is motivated by our key finding that reliability-related flasherrors are highly skewed among program states. That is, not allflash reliability errors occur equally likely among different pro-gram states. To be precise on the per-state error characteristics,we performed comprehensive evaluations using 2x-nm TLC flashchips and validated that a few program states are responsible formost reliability errors. SARO narrows Vth distributions of theseerror-prone states only, thus significantly reducing the overheadsimposed by applying a fine-grained Vispp . Our SARO also exploitsa well-known flash phenomenon that the program latency is de-creased as flash cells get older because of traps in the damagedtunnel oxide [2]. Specifically, we employ a fine-grained Vispp onlywhen the program latency gets shorter, which can in turn makeSARO achieve high flash reliability while keeping the programlatency unchanged.

For the validation of SARO, we built per-state error modelsusing 2x-nm TLC flash chips. Based on the per-state error models,we devise a simple but effective method of selectively modifyingVispp values under given flash cell status (such as P/E cycles). Ourexperimental results show that SARO can improve the reliabilityof MLC and TLC flash devices by 100% and 50%, respectively. Asa direct result of the improved reliability, SARO shortens the readlatency by 40%, on average, by reducing the number of read retryoperations.

The rest of this paper is organized as follows. Before SARO ispresented, we explain the key trade-off relationship between thereliability and program latency in flash devices using real MLC andTLC flash chips. The key schemes of SARO are presented in Section3. Section 4 describes the SARO implementation details. Experi-mental results follow in Section 5, and related work is summarizedin Section 6. Section 7 concludes with a summary and future work.

2 BACKGROUND2.1 Reliability vs. Vth Design ParametersFor writes, flash changes target cell’s Vth states based on the con-tent information (per bit). In the case of reads, flash reconstructsthe content by sensing the Vth state of target cells. Figure 2 illus-trates Vth distributions for 2m-state flash devices, which storesmbits within a cell by using 2m distinct Vth states (i.e.,m is 2 and

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Figure 3: Change patterns inVth distributions depending ondifferent error types.3 for MLC and TLC, respectively). Since the primary Vth designparameters shown in Figure 2 (i.e.,WPi ’s, MPi ’s, Mdist , V Erase

V er if y ,and V Proдram

V er if y ) directly affect both the flash reliability and flashperformance, how to set these parameters is a critical decision forNAND flash manufacturers. Once the Vth design parameters arefixed during the flash design time, the flash reliability largely de-pends on howVth distributions are disturbed by various causes. Biterrors in flash memory occur when theVth distribution of one stateis shifted to neighboring state’sVth regions so that two overlappingVth distributions cannot be distinguished as two different states.

In general, we can categorize bit errors in flash into four groupsas shown in Figure 3. When a page is written, a small number ofbit errors are inevitable as shown in Figure 3(a). These initial errorsare caused by process variations and inherent noise effects (suchas cell-to-cell interference, back pattern dependency, and randomtelegraph noise) [3]. More serious bit errors, which mandate toemploy a strong error-correction scheme (such as LDPC codes) ina flash controller, are related to defects in the tunnel oxide layer offlash cells [4]. As a flash device experiences P/E cycles, the widthof Vth distributions tend to get wider because of traps in tunneloxide layer which are caused by applying a high program/erasevoltage frequently. The traps in the tunnel oxide layer generatedby P/E cycles also exacerbate the program disturbance. When flashcells are programmed, neighboring cells belonging to the E-state aresoftly programmed, so that theirVth move to the right. As shown inFigure 3(b), these errors are called endurance errors. The repeatedread operations also shift Vth of E-state cells to the right. Whenflash cells are read, V Pass

Read (6∼7V) is applied to all the wordlines(WLs) in the same block except for the target wordline 2. Whenpages in the same block are frequently read, E-state cells in theblock are softly programmed, thus shifting their Vths to the right.These errors, as shown in Figure 3(c), are called read-disturb errors.If flash cells are left for a long time after a program operation, acharge loss occurs by the stress-induced leakage current (SILC)through traps in the tunnel oxide layer. These errors, as shownin Figure 3(d), are called retention errors. The charge loss shiftsthe Vth of program states to the left. Furthermore, higher programstates experience a greater amount of the charge loss, and henceshow a larger Vth shift compared to lower program states [5].

WhenVth distributions are sufficiently moved,Vth distributionsmay overlap with read reference voltages (i.e., R1, R2 and R3 inFigure 3), thus producing flash bit errors. For example, the shadedregions in Figure 3 indicate such overlapped Vth distributions. If2The memory cells are packed to form a matrix structure. As shown in Figure 9, cellsshare a wordline (WL) horizontally and a bitline (BL) vertically.

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there is an insufficient Vth margin between the states, flash biterrors sharply increase as Vth distributions are disturbed. Whenthe number of flash bit errors reaches over a pre-defined upper limit,which is generally determined by the error correction capabilityof an ECC engine in a flash controller, the flash page cannot becorrectly read, resulting in a read-failure status. Thus, to guaranteethe reliability of a flash device, sufficientMdist andMPi should besecured considering the maximumVth changes after the maximumnumber of P/E cycles, read cycles, and retention times.

2.2 Reliability vs. Program LatencyTypically, a flash device employs an incremental step pulse program-ming (ISPP) scheme [6] to control the widthWPi of program states.As shown in Figure 4(a), the ISPP scheme gradually increases theprogram voltage byVispp at a time until all their cells in a page arecompletely programmed. For each program loop that takes tLOOP ,once cells are verified to have been sufficiently programmed by averify operation, those cells are excluded from the next programloop. Since the widthWPi of the i-th program state is proportionalto Vispp , a simple solution to ensure sufficientMdist andMpi is tonarrowWPi by reducing Vispp during a program operation. Eventhough the Vispp reduction can improve the flash reliability, itincreases the total number of nLoop of program loops because asmallerVispp value needs to repeat the program loop more to reachVf inal for the maximum program state. Therefore, the programlatency is inversely proportional to Vispp . Figure 4(b) shows thatthe program latency directly increases as Vispp is scaled down.

Figure 5 shows the results of reliability test over various Visppscaling ratios using real 2x-nm node MLC and TLC chips 3. (Fora detailed description on the evaluation settings, refer to Section

3When the Vispp scaling ratio is set to X%, Vispp is reduced by X% of the nominalVispp . We call this Vispp setting by modeX. BASE represents the baseline techniquewhere Vispp scaling ratio is 0%.

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5.) As expected, both the endurance and retention capability weresignificantly improved with a smaller Vispp value. In 2x-nm MLCflash chips, the maximum number of P/E cycles is increased fromless than 7,000 to more than 10,000 when Vispp is reduced by 30%(i.e., mode30). The data retention capability is also increased undermode30 from about 2 years to 5 years 4.

As shown in Figure 4 and 5, there is a trade-off relationshipbetween the flash reliability and the flash program latency whenVispp varies. Our main goal of the proposed SARO technique is toinvestigate if we can achieve the same flash reliability improvementfrom a smaller Vispp value without sacrificing the program latency.

3 SARO: BASIC IDEA3.1 State-Aware Reliability CharacterizationSince the program latency is proportional to nLoop and nLoop is,in turn, inversely proportional to Vispp , reducing Vispp directlyincreases the program latency and vice versa. In order to mitigatethe impact of a smaller Vispp on the program latency, we investi-gated whether flash errors occur in a state-oblivious fashion or in astate-aware fashion using 2x-nm TLC flash chips. Our intention wasthat if flash bit errors occurred differently over different programstates, we can apply a smaller Vispp value only to those states withhigher probability of bit errors while not reducing Vispp for theother states. By combining a smallVispp value with a larger one, wecan effectively lessen the impact of Vispp on the program latencywhile, hopefully, achieving the same reliability improvement.

Figure 6 shows a breakdown of per-state flash bit errors on ourcharacterization study with 2x-nm TLC flash. Our results stronglyindicate that flash bit errors occur in a state-aware fashion. Thatis, different error types occur in different program states. Most ofendurance and read-disturb errors occur between the E and P1 stateby the overlapped Vth distribution of the E-state cell and R1 readreference voltage level. In Figure 6, about 43% of the total enduranceand read-disturb errors occur between E and P1 states. On the otherhand, most of retention errors occur in higher states. In Figure 6,4The data retention capability is measured under the retention temperature of 30◦Cafter the maximum P/E cycles (3,000 for MLC flash and 1,000 for TLC flash) and 1,000read cycles for each block. This evaluation setting is a de facto standard for NANDmanufactures.

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retention errors between the P5 and P6 states account for about31% of the total retention errors while retention errors betweenthe P6 and P7 states are responsible for 50% of the total retentionerrors.

Based on our characterization results, SARO employs a state-aware program scheme, optimizing each program state based onits own reliability requirement. As shown in Figure 7, we apply thereduced Vispp value to most error-prone states (e.g., P1, P5, andP6 in Figure 7) only so that most bit errors can be avoided with asmall increase in the program latency. In addition to the reliabilityoptimization from a finer Vispp control, SARO improves the readlatency as well. For example, in Figure 7, asMP1,MP6, andMP7 getwider, we adjust R1, R6, and R7 accordingly. This adjustment con-tributes to reducing the number of read retry operations required.Furthermore, since P7 has no right-side neighbor, we increase itsVispp so that P7 program latency can be further reduced.

Our SARO technique can be easily generalized to 2m -state flashas follows:• Reduce Vispp and increase the verify and read referencevoltage (Rx) of the lowest program state (i.e., P1) to improvethe endurance and read disturb error.• ReduceVispp of program states from (2m−2) state to 2m−(2m−2+1)state to improve the retention error.• Increase Vispp of (2m−1) (i.e., the highest) program state toreduce the performance degradation.• Decrease Rx of program states from (2m−1) state to (2m−2m−2)state to make the read latency shorter.

3.2 Slack-Aware Adaptive NAND ProgrammingIn order to minimize the performance degradation from reducingVispp , we devised a slack-aware scheme which accurately estimatesthe tPROG acceleration ratio as flash cells get aged. For an accurate

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Figure 8: tPROG speed changes over varying P/E cycles.

estimate of tPROG, we performed a flash characterization studywhile varying the number of P/E cycles. As shown in Figure 8,the average latency for a page programming constantly decreasesas the number of P/E cycles increases. In MLC flash devices, afterapplying 3,000 P/E cycles, the average program latency decreases by13.4%, compared to an initial value (1,300 µs). The average programlatency of TLC flash devices also decreases by 9.6% after 1,000P/E cycles. The effect of tPROG acceleration over P/E cycles can beexplained using traps in the tunnel oxide layer. As the number of P/Ecycles increase, traps also increase because a high program/erasevoltage damages the tunnel oxide layer. As the tunnel oxide layergets damaged, its insulation capability gets worse, thus allowingelectrons to move easily into flash floating gate. As a consequence,programming the aged pages (e.g., experienced a lot of P/E cycles)requires lesser number of program loops to complete the programoperation.

Based on the tPROG acceleration model, SARO applies a finerVispp value only when tPROG gets faster. In order not to introduceany latency overhead, SARO tries to match an increase from afiner Vispp value with a decrease in tPROG. Although this solutionis helpful to improve the flash reliability and easy to implementwithout any hardware modification, if we apply the proposed slack-awareVispp adjustment technique onlywithout exploiting per-stateerror behavior of Section 3.1, its effect on the flash reliability israther limited. Since the decrease of the program latency (even) atthe end of the flash lifetime is about 10% of the default programlatency, Vispp can be reduced up to 10% only. For TLC flash, thereliability improvement is marginal, i.e., about 10% only, as shownin Figure 5(b).

4 SARO: IMPLEMENTATION DETAILS4.1 State-Aware Selective NAND ProgrammingTo support state-aware programming, a flash device should applydifferent Vispp values to cells in the sameWL. Fortunately, sinceNAND flash memory supports a bit-by-bit selective operation withthe self boosting program inhibit (SBPI) scheme [6], state-awareselective programming can be easily implemented by modifyingthe BL operating conditions without an additional hardware modi-fication.

Figure 9 illustrates how the SBPI scheme supports bit-by-bitselective program operations. When a pageWLk is programmed,its i-th cell within the page is selectively programmed dependingon the value of BLi . If BLi is set to 1 (i.e., Vcc), the i-th cell is notprogrammed (i.e., inhibited) because there is an insufficient voltagedifference by channel boosting effect (P1 in Figure 9(a)). If BLi isset to 0 (i.e., 0V), the i-th cell is programmed because there is anenough voltage difference to move the electron into the floating-gate (P6 in Figure 9(b)). Based on a conventional SBPI, when thei-th cell is programmed, the effective Vispp for the i-th cell duringa program operation can be reduced by forcing a specific voltageinto the channel connected to BL. For example, when a program

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Figure 9: Design Schematics to implement state-aware se-lective programming using conventional SBPI scheme andpage buffer operation.

voltage is increased from 18V to 18.4V byVispp (= 0.4V), the effectiveVispp can be reduced to 0.3V by applying 0.1V to the channel. Inour example, P1 state is inhibited (Figure 9(a)), P6 state is normallyprogrammed by 0.4V Vispp (Figure 9(b)), and P5 state in BLn isprogrammed in a state-aware fashion (Figure 9(c)). At the start of P5state programming (assuming that the start program voltage of P5state is 18V), theWL gate is set to 18V by the target row decoder, andthe PBn forces Vcc to the BLn . Since the gate of the pass transistorconnected with BLn is set toVIM+VT (i.e.,VT is a threshold voltageof the pass transistor), the voltage which can be transfered to theBLn becomes VIM . Therefore, the voltage difference between thechannel and floating-gate of P5 state is reduced by VIM , whichindicates that the effectiveVispp is 0.4V−VIM . As the program loopsof the target program state proceed, the gate voltage of the passtransistors is increased by VIM to maintain the reduced effectiveVispp .

4.2 SaFTL: SARO-aware FTLIn order to take advantage of the SARO technique in flash-basedstorage systems, we modified an existing page-level FTL to supportSARO. (We call this modified FTL SaFTL, SARO-aware FTL.) Themain goal of SaFTL is to manage various operating parametersbased on the program latency measured from NAND flash mem-ories. Figure 10 shows an overall organization of SaFTL. SaFTLmonitors the program latency from a flash device. The measuredprogram latency is compared to its initial (non-accelerated) tPROG.Depending on the difference between the measured tPROG and theinitial tPROG, theMode Selectormodule decides a properMode for aprogram request. For example, if the measured tRPOG is faster thanthe initial tPROG by 3%, the next program request is programmedusing Mode 3 entry of the Parameter Table. The Parameter Tablecontains all the necessary values for Vth design parameters for agivenMode type.

In order for SaFTL to properly work, the initial program latencyandMode should be maintained for every programmed page. How-ever, in order to reduce the memory overhead for implementing

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Figure 10: An Organizational overview of SaFTL

SARO, a mode selection is applied in a per-block basis. (That is, allthe pages in the same block is programmed using the sameMode .)Since variations in tPROG within the same block is negligible (e.g.,less than 3 µs in our evaluations), per-block mode selection is aneffective solution to minimize both the memory overhead and thetPROG monitoring overhead.

In order to maintain up-to-date status per each block, SaFTLuses the Per-Block Table which can be implemented with a smallmemory overhead. For example, a flash device with 8,192 blocksneeds extra 22-KB memory for Per-Block Table. The initial programlatency is measured when the flash device is first programmed,and stored in a pre-defined area. The current program latency isdetermined by monitoring only one lastWL per block.

5 EXPERIMENTAL RESULTSWe conducted experiments using 20 real 2x-nm TLC and MLC flashchips, respectively, to evaluate the effectiveness of the proposedoptimization technique. In order to minimize the potential distor-tion of the evaluation results from process variations, we evenlyselected 30 test blocks from each chip at different physical blocklocations, and tested all the pages in each selected test block. As aresult, a total of 115,200 pages (on TLC flash chips) and 76,800 pages(on MLC flash chips) were used to obtain statistically significant ex-perimental results. Using an in-house custom test board (equippedwith a NAND controller and a thermal controller), we conductedcomprehensive reliability and performance evaluations varying keyvariables such as P/E cycles, read cycles, and retention times. Forexample, in MLC flash chips, the endurance test was performedwith increasing the P/E cycles from 0 (an initial condition) to 10,000.Similarly, the retention capability was evaluated by changing theelapsed time (since the program operation) from 1 year to 5 years.

Figure 11 (a) and (b) show how the flash endurance and reten-tion capability change under four different operation modes, BASE,mode10, mode30, and SARO. SARO improves endurance and reten-tion capability by 100% in MLC flash chips and 50% in TLC flashchips over BASE, respectively. To better understand why SAROoutperforms BASE, we measured flash bit errors in each pages. Thenumber of flash bit errors in SARO is reduced by 56.1% in MLCflash chips and 25.2% in TLC flash chips over BASE because SAROincreases the Vth margin between an error-prone adjacent states,thus improving the error tolerance of a flash device. As expected,mode30 shows the best reliability improvement, but it also degradesthe program latency by about 20% as shown in Figure 11(c). SARO,on the other hand, barely affects the program latency. For TLCflash chips, SARO increases the program latency by 1.8% which isnegligible overhead.

In order to understand the impact of the improved reliability onthe read latency, we evaluated how the number of read retry oper-ations changes under SARO. The read retry operation is initiated

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Figure 11: Comparisons of reliability and performance met-rics of four different operation modes.

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Figure 12: Changes in the number of read retry operationsunder SARO over the baseline technique.

when uncorrectable errors are detected, and repeated until errorscan be corrected by the ECC scheme. Since the read latency of aflash device is directly proportional to the number of repeated readretry operations, the read latency is significantly improved whenthe number of read retry operations is reduced. Figure 12 showsthe number of read retry operations under BASE and SARO in MLCand TLC flash chips. SARO reduces the average number of readretry operations by 40% on average over BASE.

6 RELATEDWORKThere have been several studies that attempt to improve the relia-bility of flash devices. Pan et al. [7] proposed a technique which canreduce Vispp with P/E cycles to optimize the reliability and perfor-mance of NAND flash memory. However, this technique changes

Vispp of all program states without considering different error pat-terns among different program states. Therefore, this techniqueis rather limited to apply for high-density flash devices, such asTLC flash devices. Park et al. [8] also proposed a technique whichcan change program operating parameters according to P/E cycles.However, their technique is different from SARO in that they didnot explore per-state error characteristics. In addition, their tech-nique targets SLC flash devices only so that it cannot be applied forhigh-density flash devices. The DPES technique proposed by Jeonget al. [9] is similar to our SARO in that it dynamically changes eraseand program parameters of a flash device. However, unlike SARO,it improves the flash endurance only by reducing a stress to flashcells. SARO is different from this technique in that SARO improvesthe flash reliability in a comprehensive fashion by considering allthe different error types including the endurance errors.

7 CONCLUSIONSWe have presented a new flash reliability optimization technique,SARO, that solves the reliability problem of high-density NANDflash memory without sacrificing the program latency. Our pro-posed technique is based on the state-aware selective programmingscheme, which enables each program state to be programmed by adifferentVispp value. Since SARO improves the error tolerance of aflash device by selectively reducing Vispp for the most error-proneNAND states only, it is an effective solution to maximize the relia-bility improvement while minimizing the performance degradation.In order to keep the performance unchanged, SARO parameters arefine-tunned exploiting the flash characteristics that the programlatency decreases with cell aging. Our evaluation results with realflash chips show that SARO is effective in improving the flash relia-bility thanks to the significant decrease in NAND bit errors. It alsoimproves the read latency by 40% on average due to the reductionof read retry operations.

The current version of SARO can be extended in several direc-tions. For example, since a finer Vispp value is more effective forhigher flash reliability, we plan to better exploit various systemhints (e.g., latency-insensitive program operations) to more aggres-sively reduce Vispp without affecting the program latency.

ACKNOWLEDGMENTThis work was supported by Samsung Research Funding & In-cubation Center of Samsung Electronics under Project NumberSRFC-IT1701-11.

REFERENCES[1] Y. Park et al. 2014. Scaling and Reliability of NAND Flash Devices. In Proc. IEEE

Int. Reliability Physics Symposium.[2] Y. Woo et al. 2013. Diversifying Wear Index for MLC NAND Flash Memory to

Extend the Lifetime of SSDs. In Proc. Int. Conf. on Embedded Software.[3] R. Micheloni et al. 2010. Inside NAND Flash Memories. Springer.[4] N. Mielke et al. 2017. Reliability of Solid-State Drives Based on NAND Flash

Memory. In Proc. IEEE, Vol. 105(9). 1725–1750.[5] Y. Cai et al. 2015. Data retention in MLC NAND flash memory: Characterization,

optimization, and recovery. In IEEE Int. Symposium on High Performance ComputerArchitecture.

[6] K. Suh et al. 1995. A 3.3V 32 Mb NAND Flash Memory with Incremental StepPulse Programming Scheme. In IEEE Tran. on Consumer Electronics, Vol. 30(11).1149–1156.

[7] Y. Pan et al. 2011. Exploiting Memory Device Wear-Out Dynamics to ImproveNAND Flash Memory System Performance. In Proc. USENIX Conf. on File andStorage Technologies.

[8] S. Park et al. 2012. Adaptive Program Verify Scheme for Improving NAND FlashMemory Performance and Lifespan. In IEEE Asian Solid-State Circuits Conf.

[9] J. Jeong et al. 2014. Lifetime Improvement of NAND Flash-based Storage SystemsUsing Dynamic Program and Erase Scaling. In Proc. USENIX Conf. on File andStorage Technologies.

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