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SD – Silicon Detector EM Calorimetry

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SD (Silicon Detector)

• Conceived as a high performance detector for NLC

• Reasonably uncompromised performance• But• Constrained & Rational cost

• We accept the notion that excellent energy flow calorimetry is required, and explore optimization of a Tungsten-Silicon EMCal…

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Silicon DetectorEM Calorimetry

Quadrant View

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Scale of EMCal & Vertex Detector

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Silicon Tungsten EMCal

• Figure of merit something like BR2/ where is the rms sum of Moliere radius of the calorimeter and the pixel size. – Maintain the great Moliere radius of tungsten

(9 mm) by minimizing the gaps between ~2.5 mm tungsten plates. Dilution is (1+Rgap/Rw)

– Could a layer of silicon/support/readout etc fit in a 2.5 mm gap? Even less?? 1.5 mm goal??

• Requires aggressive electronic-mechanical integration!

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EMCal, continued• Diode pixels between 5 – 10 mm square on largest

hexagon fitting in largest available wafer. (6” available now – 300 mm when??) Consider tracking as well as E flow in picking pixel dimension.

• Develop readout electronics of preamplification through digitization, zero suppression and IO on bump bonded chip. Upgrade would be full integration of readout on detector wafer. (R&D opportunity!)

• Optimize shaping time for small diode capacitance. Probably too long for significant bunch localization within train. But some detector element needs good time resolution!!!

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Channel Counts [Forget Them!!]

• We are used to pixel counts in CCD’s …– 3x108 last time, 1x109 this time, no problem

• Silicon Strip Tracker ~5x106 strips (channels??)

• EMCal ~5x107 pixels (channels??)• Don’t even think about multiplying channels

by O($10)……

• Must solve the cluster technology challenges.

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Structure

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Pixels on 6” Wafer

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Zoom to Readout Chip

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Gross System ArchitectureSilicon Diode Array

Readout Chip

Network Interconnect

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Cross Section

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Signal Collection from m2 board

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Preamplifier Architecture

• Charge amplifier and shaper followed by two amplifiers with gains G1,G2 and sample & holds.

• Comparator logic to select appropriate range

• Mux and 12 bit ADC

Shaper

G2

G1

MUX

12 bit ADC

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Noise and Muons

• Assume 300 (400-500 possible) effective e- collection at 80 e-/. signal ~ 24000 e-.

• Assuming diode capacitance of 0.3 pf/mm2, and amplifier noise of 20e-/pf+200e- – noise ~400 e-. S/N ~60, plenty good!

• Pick S/N of 7 (Figure) for minimum performance.

Noise & Muon Distributions

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Plausible Resolution Criteria

• Spread the 0.6% muon into several bins, with enough range for MIP counting to a few.

• Preliminary Monte Carlo indicates peak ionizing track density from a high energy shower to be 2200 µ equivalent. (5 x 107 e- = 8 pC.)

• Do not degrade resolution of calorimeter! Energy resolution of a sampling calorimeter with 2/3 X0 plates will not exceed 12%/√E. Say this peak should be spread over 5 bins, and take no credit for multiple sampling.

• Relaxation of these requirements now being studied with EGS.

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Required Resolution

• High Res Bin Width=1000 e-, Emax=37 GeV,Mips=170• Low Res Bin Width=13200 e-,Emax=512

GeV,Mips=2325

Resolution vs Requirements

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Technical Issues• Assuming integrator full scale voltage of

around 1 V, feedback (and calibration) capacitors need to be ~10 pF. This is large for an integrated capacitor, but doable with substantial real estate.

• Plus is that this makes the bump bond pitch easy!

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Thermal Management

• Cooling is a fundamental problem: GLAST system is ~2 mW/channel. Assume 1000 pixels/wafer and power pulsing duty factor for NLC of 10-3 (10 µsec @120 Hz), for 2 mW average power.

• Assume fixed temperature heat sink (water cooling) at outer edge of an octant, and conduction through a thick (6 oz) copper ground plane in the G10 motherboard.

• ΔT~10C.• This is fine, but it sure doesn’t work without power

pulsing!!! Holding the power down while maintaining the noise/resolution is a serious engineering challenge.

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Plans

• We (Oregon and SLAC) plan to develop this design in more detail and build prototype wafers and chips.

• Test detectors in 5 Tesla field.• If successful, develop board level chip.

• Build 1 wafer wide by about 25 X0 deep calorimeter for test beam.