sdt lab manual - gecdahod.ac.in

1 GOVERNMENT ENGINEERING COLLEGE,DAHOD

PRACTICAL -1

Aim : Introduction to the software PSPICE capture student.

This option of OrCAD Capture is available in the START -> ALL PROGRAMS.


After opening the pspice capture, click on the file menu and create a new project by selecting File -> New -> Project


●After selecting the new project option, dialog box obtained on the screen are as shown above.

●We can give the name of our project like here in the picture name of the project is given as “test”. ●Then we have to select any one option from the given four options according to the need. Here as shown, “Analog or Mixed A/D” is selected. ●Then select the location for the project where it is to be stored. We can select any location as per our requirement.


●This is the screen where we can create our circuit & can run our circuit.

●On just above the blank screen of the software, we have different options like different types of markers, voltage and current probes, run pspice, edit simulation settings, save the file, print option, etc. ●Likewise, on the right side of the screen also we have different options.


●We can select the different types of components by selecting: Place -> Part. All these components are stored in different Libraries according to their feature. So in order to view all the components, first select all library function as shown in the figure. ●We can also select the components from the icons given on the right side of the screen.


●After selecting the component, we can rotate the component by -- Right click (on the component) ->Rotate. So we can create our circuit asper our requirement.


●After selecting the components, we can connect all the components by wire & we can complete our circuit. The option of wire can be available by: Place -> Wire. Or it is also available on the right side of the blank screen.


Here by using different components, the circuit obtained is as shown in the above figure. And in order to simulate the circuit, we need to fix the probes as per our requirement between different components of the circuit as shown in the figure.


After the circuit is formed, select the new simulation profile from and name the simulation as shown in the figure.


Here, we can select the simulation settings as shown in above figure. Here analysis type is selected as ‘DC Sweep’. Also we can select the sweep variable, sweep type, start value, end value & increment as per the requirement. When we run our circuit, we can see the graph as shown in the figure. This phenomenon of running the circuit after making it in software is known as SIMULATION.

Teacher’s Signature


PRACTICAL: 2

Aim: To measure the voltage and current at various node of resistor network.

Software: Or-cad capture, PSPICE

Circuit:

Net list:

* Source RESISTOR-NW

R_R1 N00136 N00122 1000 TC=0, 0

R_R2 N00122 N00115 1000 TC=0, 0

R_R3 0 N00122 1000 TC=0, 0

V_V1 N00136 0 12v

V_V2 N00115 0 12v

Output waveform:

R1

1000

R2

1000

R31000

V112v

V212v

0

VV V


Procedure:

• Open ORCAD CAPTURE.

• Select new project from file menu.

• Select analog and mixed A/D.

• Choose blank project.

• Make circuit as shown in figure.

• Place the voltage marker at appropriate node.

• Create new simulation profile and click on run.

Analysis Type: Bias point


Conclusion:

Hence, from the above practical, we can conclude that the theoretical values of current and voltage is same as the practical values that we get from the ORCAD simulation.



PRACTICAL: 3

Aim: To study the working and construction of half wave rectifier.


Circuit:

Net list:

* source RECTIFIER

X_TX1 N00179 0 N00183 0 SCHEMATIC1_TX1

V_V1 N00165 0

+SIN 0 50 50 0 0 0

R_R1 N00165 N00179 1k TC=0, 0

D_D1 N00183 N00196 D1N4004

R_R2 0 N00196 10k TC=0,0

Theory:

• When the sinusoidal input voltage (V in ) goes positive, the diode is forward-biased and conducts current through the load resistor.

• The current produces an output voltage across the load Rv which has the same shape as the positive half-cycle of the input voltage.

• When the input voltage goes negative during the second half of its cycle. the diode is reverse-biased. There is no current, so the voltage across the load resistor is 0 V.

• The net result is that only the positive half-cycles of the AC input voltage appears across the load.

TX1

V1

FREQ = 50VAMPL = 50VOFF = 0

R1

1k

D1

D1N4004

R210k

0 0


Procedure:








Analysis Type: Transient


Output waveform:

Conclusion:

Hence the half wave rectifier converts ac voltage into dc voltage



PRACTICAL: 4

Aim: To study the working and construction of full wave rectifier.


Circuit:

Net list:

* source FULL WAVE

X_TX5 N03215 0 N03299 0 N03305 XFRM_LIN/CT-SEC PARAMS: LP_VALUE=200

+ LS1_VALUE=50 LS2_VALUE=50 COUPLING=.99 RP_VALUE=0.1 RS_VALUE=0.1

R_R3 N03175 N03215 1k TC=0,0

D_D2 N03299 N03221 D1N4004

D_D3 N03305 N03221 D1N4004

V_V2 N03175 0

+SIN 0 20V 50 0 0 0

R_R4 0 N03221 10k TC=0,0

Theory:

• The positive half-cycle of the input voltage, forward-biases diode D3 and reverse-biases diode D 4 . The current path is through D3j and the load resistor R.

• The negative half-cycle of the input voltage, reverse-biases D j and forward-biases D 2 . The current path is through D4 and load resistance R

• Because the output current during both the positive and negative portions of the input cycle is in the same direction through the load, the output voltage developed across the load resistor is a full-wave rectified de voltage.

V2


R3

1k

D2

D1N4004 R4

10k

0

D3

D1N4004

00Lp

Ls 1

Ls 2

TX5

XFRM_LIN/CT-SEC

V


Procedure:

• Open ORCAD CAPTURE

• Select new project from file menu

• Select analog and mixed a/d

• choose blank project

• make circuit as shown in figure

• place the voltage marker at appropriate node

• create new simulation profile and click on run



Output waveform:

Conclusion:

Hence the full wave rectifier converts ac voltage into dc voltage

Teacher’s Signature:


PRACTICAL: 5

Aim: To study the working and construction of full wave bridge rectifier


Circuit:

Net list:

* source BRIDGE

V_V3 N13268 0

+SIN 0 5 50 0 0 0

D_D7 N13154 N13134 D1N4001

D_D4 0 N13130 D1N4001

D_D5 N13130 N13134 D1N4001

R_R4 0 N13134 10k

X_TX3 N13294 0 N13130 N13154 SCHEMATIC1_TX3

R_R6 N13268 N13294 1k

D_D6 0 N13154 D1N4001

.subckt SCHEMATIC1_TX3 1 2 3 4

K_TX3 L1_TX3 L2_TX3 0.99

L1_TX3 1 2 10H

L2_TX3 3 4 10H

.ends SCHEMATIC1_TX

D4

D1N4001

D5

D1N4001

D6

D1N4001

D7

D1N4001

TX3

R4

10k

V3


R6

1k

00

V

V


Theory:

• The positive half-cycle of the input voltage, forward-biases diode D3 and reverse-biases diode D 4 . The current path is through D3 and the load resistor R.

• The negative half-cycle of the input voltage, reverse-biases D3 and forward-biases D 2 . The current path is through D4 and load resistance R.

• Because the output current during both the positive and negative portions of the input cycle is in the same direction through the load, the output voltage developed across the load resistor is a full-wave rectified DC voltage.

Procedure:










Output waveform:

Conclusion:

Hence the full wave rectifier converts AC voltage into DC voltage.



PRACTICAL: 6

Aim: To analyse negative clipper circuit.


Circuit:

V1


V2


V3


V4


V5


V6


D1

D1N4001

D2

D1N4001

D3D1N4001

D4D1N4001

D5

D1N4001

D6

D1N4001

R11k

R21k

R31k

R4

1k

R5

1k

R6

1k

V7

1

V8

1

0

0

0

V9

1

V10

1

0

0

0


Net list:

* source CLIPPER

D_D4 0 N16723 D1N4001

V_V5 N16781 0

+SIN 0 5 50 0 0 0

V_V3 N16653 0

+SIN 0 5 50 0 0 0

V_V6 N16817 0

+SIN 0 5 50 0 0 0

V_V2 N16609 0

+SIN 0 5 50 0 0 0

V_V4 N16717 0

+SIN 0 5 50 0 0 0

R_R4 N16723 N16717 1k

R_R5 N16791 N16781 1k

R_R1 0 N16577 1k

V_V9 0 N16801 1

D_D5 N16659 N16665 D1N4001

V_V8 N16659 N16653 1

D_D1 N16549 N16577 D1N4001

D_D2 N16637 N16643 D1N4001

D_D6 N16829 N16823 D1N4001

V_V1 N16549 0

+SIN 0 5 50 0 0 0

R_R2 0 N16643 1k

V_V10 N16829 0 1


D_D3 N16801 N16791 D1N4001

V_V7 N16609 N16637 1

R_R6 N16823 N16817 1k

R_R3 0 N16665 1k

Theory:

• Clipper circuits are shown in figure.

• For a positive half cycle of the input, diode d is forwarded.Hence, the voltage waveform looks like a positive half cycle of the input.

• While for negative half cycle of the input, diode D is reverse biased. Hence, it will not conduct.

• So, the negative half cycle will be clipped off.

• The output can be adjusted as per requirement by adding an additional DC voltage source in series with the diode.

Procedure:










Output waveform:

Conclusion:

Hence in negative clipper, negative half of input gets clipped off



PRACTICAL: 7

Aim: To analyse positive clipper circuit.


Circuit:

V11


V12


V13


V14


V15


V16


D8

D1N4001

D9D1N4001

D10D1N4001

D11

D1N4001

D12D1N4001

R71k

R81k

R91k

R10

1k

R11

1k

R12

1k

V17

1

V18

1

0

0

0

V19

1

V20

1

0

0

0

D13

D1N4001

V


Net list:

* source clipper

D_D13 N15200 N15172 D1N4001

D_D10 N15346 0 D1N4001

R_R9 0 N15288 1k

D_D12 N15446 N15452 D1N4001

V_V11 N15172 0

+SIN 0 5 50 0 0 0

R_R10 N15346 N15332 1k

V_V12 N15232 0

+SIN 0 5 50 0 0 0

R_R8 0 N15266 1k

R_R7 0 N15200 1k

V_V18 N15282 N15276 1

V_V17 N15232 N15260 1

V_V20 N15452 0 1

V_V14 N15332 0

+SIN 0 5 50 0 0 0

D_D9 N15414 N15424 D1N4001

V_V16 N15440 0

+SIN 0 5 50 0 0 0

D_D11 N15288 N15282 D1N4001

V_V15 N15404 0

+SIN 0 5 50 0 0 0

R_R12 N15446 N15440 1k

D_D8 N15266 N15260 D1N4001


V_V19 0 N15424 1

V_V13 N15276 0

+SIN 0 5 50 0 0 0

R_R11 N15414 N15404 1k

Theory:

• Clipper circuits are shown in figure.

• For a positive half cycle of the input, diode d is forwarded.Hence,the voltage waveform looks like a positive half cycle of the input.

• While for negative half cycle of the input, diode D is reverse biased. Hence, it will not conduct.

• So, the negative half cycle will be clipped off.

• The output can be adjusted as per requirement by adding an additional DC voltage source in series with the diode.

Procedure:










Output waveform:

Conclusion:

Hence in positive clipper ,positive half of input gets clipped off.



PRACTICAL: 8,9

Aim: Study of negative and positive clamper circuit.


Circuit:

Negative clamper Positive clamper

Net list:

* source CLAMPER

D_D3 N04813 N04751 D1N4001

V_V1 N04405 0

+SIN 0 5 1k 0 0 0

V_V4 N04729 0

+SIN 0 5 1k 0 0 0

C_C3 N04729 N04751 1u

V6

FREQ = 1kVAMPL = 5VOFF = 0

C4

1u

D4D1N4001

R4

1k

0

V7


C5

1u D5D1N4001

R51k

0

V81v dc

V9


C6

1u D6D1N4001

R61k

0

V101v dc

V V1


C1

1u

D1D1N4001

R11k

0

V2


C2

1u D2D1N4001 R2

1k

0

V31v dc

V4


C3

1u D3D1N4001

R31k

0

V51v dc


R_R6 0 N05251 1k

R_R3 0 N04751 1k

C_C2 N04559 N04569 1u

D_D6 N05251 N05313 D1N4001

R_R1 0 N04415 1k

D_D1 0 N04415 D1N4001

D_D4 N04915 0 D1N4001

R_R5 0 N05069 1k

V_V6 N04905 0

+SIN 0 5 1k 0 0 0

C_C6 N05229 N05251 1u

V_V5 0 N04813 1vdc

D_D2 N045230 N04569 D1N4001

V_V9 N05229 0

+SIN 0 5 1k 0 0 0

V_V7 N05059 0

+SIN 0 5 1k 0 0 0

C_C1 N04405 N04415 1u

C_C4 N04905 N04915 1u

R_R4 0 N04915 1k

V_V2 N04559 0

+SIN 0 5 1k 0 0 0

V_V8 N050231 0 1vdc

V_V3 N045230 0 1vdc

D_D5 N05069 N050231 D1N4001

C_C5 N05059 N05069 1u


V_V10 0 N05313 1vdc

R_R2 0 N04569 1k

Theory:

• Clamper is a network constructed of a diode, resistors & capacitor that shift a waveform to a different DC level without changing it.

• Clamping network has a capacitor connected directly from input to output with a resistor in parallel to the output.

• The diode is also in parallel to the output but may or may not have a series DC supply added.

• A clamper is called negative if it shifts the input waveform towards the negative side without changing it & it is called positive if it shifts the waveform towards the positive side.

Procedure:










Output waveform:

• Positive clamper:


• Negative clamper:

Conclusion:

Thus, the positive clamper shifts the input waveform to the positive side & negative clamper shifts it on the negative side.



PRACTICAL:10

Aim: To verify the diode characteristics using ORCAD.


Circuit:

Net list:

* source DIODE CHARE

D_D1 N00092 N00099 D1N4001

R_R1 0 N00099 1k TC=0,0

V_V1 N00092 0 12

Theory:

• When in forward bias, the diode will not conduct initially up to 0.7 V.

• Then, there will be a sudden exponential increase in the current. This voltage is known as knee voltage.

• From cut-in voltage, the diode starts to conduct. The change will be exponential or linear.

• While in reverse bias, diode will not conduct if applied voltage is less. When it is sufficiently increased, breakdown occurs & the current will suddenly increase.

• This region where voltage remains almost constant for different values of current is known as zener region.

D1

D1N4001

R11k

V112

0

I


Procedure:







• Create new simulation profile, select dc sweep analysis and click on run.

Analysis Type: DC SWEEP


Diode Forward characteristics:

Diode Reverse characteristics:

Conclusion:

Hence we have verified the V-I characteristics of diode.



PRACTICAL:11

Aim: To verify the BJT characteristics using ORCAD.


Circuit:

Net list:

* source BJT CHAREC

Q_Q1 N00147 N00162 0 Q2N2222

V_V1 N00126 0 0Vdc

V_V2 N00147 0 0Vdc

R_R1 N00126 N00162 100k TC=0

Theory:

• Bipolar transistors have the following characteristics: • Bipolar transistors are a three-lead device having an Emitter, a Collector, and a Base

lead. • The Bipolar transistor is a current driven device. • A very small amount of current flow emitter-to-base (base current measured in micro

amps - mA) can control a relatively large current flow through the device from the emitter to the collector (collector current measured in milliamps - mA). Bipolar transistors are available in complimentary polarities.

• The NPN transistor has an emitter and collector of N-Type semiconductor material and the base material is P-Type semiconductor material.

• In the PNP transistor these polarities are reversed: the emitter and collector are P-Type material and the base is N-Type material.

• NPN and PNP transistors function in essentially the same way. • The power supply polarities are simply reversed for each type.

Q1

Q2N2222

V10Vdc

V20Vdc

R1

100k

0

I

I


• The only major difference between the two types is that the NPN transistor has a higher frequency response than does the PNP (because electron flow is faster than hole flow).

• Therefore high frequency applications will utilize NPN transistors. • Bipolar transistors are usually connected in the Common Emitter Configuration

meaning that the emitter • Lead is common to both the input and output current circuits.

Procedure:







• Create new simulation profile,select dc sweep analysis and click on run.

Analysis Type: DC SWEEP


Input characteristics of NPN trantister:


Output characteristics of NPN transistor:

Conclusion:

Hence we have verified the V-I characteristics of BJT.



PRACTICAL: 12

Aim: To verify the BJT Amplifier characteristics using ORCAD


Circuit:

Net list:

* source BJT AMPLIFIER

Q_Q1 N00304 N00118 N00311 Q2N2222

C_C1 N00111 N00118 10u TC=0,0

V_V1 N00111 0 DC 0Vdc AC .5mv

R_R1 0 N00118 8.2k TC=0,0

R_R2 0 N00311 1.5k TC=0,0

R_R3 N00118 N00300 56k TC=0,0

C_C2 0 N00311 20uf TC=0,0

R_R4 N00304 N00300 6.8k TC=0,0

V_V2 N00300 0 22

Theory:

• A transistor amplifies current because the collector current is equal to the base current multiplied by current gain β.

• Base current in a transistor is very small compared to the collector and emitter currents because of this; the collector current is equal to the emitter current.

Q1

Q2N2222

C1

10u

V1.5mv0Vdc

R18.2k

0

R21.5k

R356k

C220uf

R46.8k

V222

0

0

V


• The ac collector voltage Vc = Ic*Rc.

• Vb can be considered the transistor ac input voltage where Vb=Vin-(Ib*Rb).

• Av=Vc/Vb=Rc/Re.

Procedure:







• Create new simulation profile, select AC sweep analysis and click on run.

Analysis Type: AC SWEEP

Conclusion:

Hence we have verified the BJT Amplifier characteristics using ORCAD.



PRACTICAL: 13,14

Aim: To implement RC high pass & low pass circuits using ORCAD.


Circuit:

Netlist:

* source RC

R_R2 0 N01329 1k

V_V1 N01481 0

+PULSE 0 5 0 0 0 5m 10m

C_C1 N01487 N01329 1u

V_V2 N01487 0

+PULSE 0 5 0 0 0 5m 10m

R_R1 N01481 N01339 1k

C_C2 0 N01339 1u

Theory:

• As show in Fig. We can implement High Pass and Low Pass Filter using RC.

• Fig.1 is RC High Pass filter, which passes high frequency and block the low frequency.

• Fig.2 is RC Low Pass filter, which passes low frequency and block the high frequency.

R1

1k

R21k

C1

1u

C21u

V1

TD = 0

TF = 0PW = 5mPER = 10m

V1 = 0

TR = 0

V2 = 5

V2

TD = 0

TF = 0PW = 5mPER = 10m

V1 = 0

TR = 0

V2 = 5

0

0

V

V


Procedure:









Conclusion:

Hence, we can conclude that RC High Pass filter, passes high frequency and RC Low Pass filter, passes low frequency.

Teacher’s Signatures


PRACTICAL: 15

Aim: To study all gates.


Circuit:

Netlist:

* source ALL GATES

U_DSTM4 STIM(1,0) $G_DPWR $G_DGND N26535 IO_STM STIMULUS=A

X_U4A N26535 N26551 4 $G_DPWR $G_DGND 7402 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0


S1DSTM3

Implementation = B

2

U4A

7402

2

31

U5A

7404

1 2

U7A

7432

1

23

3

4

5

6

1

S1DSTM4

Implementation = A

7

U1A

7408

1

23

U2A

7486

1

23

U9A

7400

1

23

U10A

7407

1 2





X_U5A N26535 6 $G_DPWR $G_DGND 7404 PARAMS:


U_DSTM3 STIM(1,0) $G_DPWR $G_DGND N26551 IO_STM STIMULUS=B





X_U10A N26551 7 $G_DPWR $G_DGND 7407 PARAMS:


Theory:

• Logic gates are the fundamental blocks of digital system.

• The name logic gates are derived for ability of such a device to make decision in the sense that it produces output when some combination of input level are present.

• There are just three basic gates: AND, OR, NOT.

• There are two universal gates: AND & NOR.

Procedure:

• Create a new blank project in ORCAD Capture and go to stimulus editor.

• In the stimulus editor, make different signals with all possible combinations.

• Create the circuit in ORCAD as shown in figure.

• Create a new simulation profile. In the customise profile, browse the file of stimulus editor and add it to design.

• Keep the probes on each source and output and then, click on run.



Conclusion:

Thus, we can get the required output using different gates in ORCAD.



PRACTICAL: 16

Aim: To implement the given Boolean equation using different gates & verify the output


Circuit:

Function: AB + (BC)’ + C’DE +A’C.

Netlist:

* source FUNTION



U_DSTM3 STIM(1,0) $G_DPWR $G_DGND N00268 IO_STM STIMULUS=C

U_DSTM4 STIM(1,0) $G_DPWR $G_DGND N00313 IO_STM STIMULUS=D

U_DSTM5 STIM(1,0) $G_DPWR $G_DGND N01300 IO_STM STIMULUS=E

X_U8A N00655 N00662 N00687 $G_DPWR $G_DGND 7432 PARAMS:


X_U8B N00669 N00678 N00694 $G_DPWR $G_DGND 7432 PARAMS:


S1DSTM1

Implementation = A

S1DSTM2

Implementation = B

S1DSTM3

Implementation = C

S1DSTM4

Implementation = D

S1DSTM5

Implementation = E

U8A

7432

1

23

U8B

7432

4

56

U8C

7432

9

108

ANS

U9A

7408

1

23 U10A

7408

1

23

U12A

7411

1122

13

U16A

7400

1

23

U17A

7404

1 2

U17B

7404

3 4

V


X_U8C N00687 N00694 ANS $G_DPWR $G_DGND 7432 PARAMS:






X_U12A N00374 N00313 N01300 N00678 $G_DPWR $G_DGND 7411 PARAMS:




X_U17A N00268 N00374 $G_DPWR $G_DGND 7404 PARAMS:


X_U17B N00199 N00543 $G_DPWR $G_DGND 7404 PARAMS:


Procedure:








Timing diagram:

Conclusion:

Thus, we can implement any Boolean function using different gates in ORCAD.



PRACTICAL: 17

Aim: To implement the half adder using ORCAD


Circuit:

Netlist:

* source HALF ADDER

X_U1A N00166 N00173 SUM $G_DPWR $G_DGND 7486 PARAMS:


X_U2A N00166 N00173 CARRY $G_DPWR $G_DGND 7408 PARAMS:




U1A

7486

1

23

U2A

7408

1

23

S1DSTM1

Implementation = A

S1DSTM2

Implementation = B

Sum

Carry

V

V

V

V


Theory:

Half adder adds two 1 bit numbers without considering previous carry

• In half adder, there are two 1-bit inputs and two outputs namely sum & carry.

TRUTH TABLE

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

• Using Kmap equations are

• SUM=A B.

• CARRY=AB

Procedure:








Conclusion:

Hence, we can conclude that half-adder is a combination of Ex-OR and OR gate.



PRACTICAL: 18

Aim: To implement the full adder using ORCAD


Circuit:

Netlist:

* source FULL ADDER





X_U2C N00440 N00343 N00565 $G_DPWR $G_DGND 7408 PARAMS:




U_DSTM3 STIM(1,0) $G_DPWR $G_DGND N00440 IO_STM STIMULUS=C



X_U10B N02275 N00565 CARRY $G_DPWR $G_DGND 7432 PARAMS:


U2A

7408

1

23

U2B

7408

4

56

U2C

7408

9

108

S1DSTM1

Implementation = AS1DSTM2

Implementation = B

S1DSTM3

Implementation = C

Carry

Sum

U10A

7432

1

23

U10B

7432

4

56

U11A

7486

1

23

U11B

7486

4

56V

V

V

V

V




X_U11B N02468 N00440 SUM $G_DPWR $G_DGND 7486 PARAMS:


Theory:

• It adds two 1bit no considering previous carry

• In full adder, there are three 1-bit inputs and two outputs namely sum & carry.

TRUTH TABLE

A B Cin SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

• Using Kmap we get the equations

• SUM=A B Cin.

• CARRY=AB +Cin(A+B)


Procedure:







Conclusion: Hence, we can conclude that full-adder is a combination of Ex-OR and OR gate.



PRACTICAL: 19

Aim: To implement NAND as universal gate.


Circuit:

Netlist:

* source NAND



X_U1A N00568 N00568 NOT $G_DPWR $G_DGND 7400 PARAMS:






X_U1D N00568 N03199 N03229 $G_DPWR $G_DGND 7400 PARAMS:


S1DSTM1

Implementation = A

S1DSTM2

Implementation = B

NOT

AND

OR

U1A

7400

1

23

U1B

7400

4

56

U1C

7400

9

108

U1D

7400

12

1311

U2A

7400

1

23

U2B

7400

4

56

V

V

V

V


X_U2A N03229 N03229 OR $G_DPWR $G_DGND 7400 PARAMS:


X_U2B N03261 N03251 AND $G_DPWR $G_DGND 7400 PARAMS:


Theory:

• NAND can be used as a universal gate as follows

• NAND as NOT A’=(A*A)’

• NAND as AND A*B=(A*B)’’.

• NAND as OR A+B=(A+B)’’=(A’*B’)’.

Procedure:








Conclusion:

Hence, we can conclude that NAND can be used as universal gate



PRACTICAL: 20

Aim: To implement NOR as universal gate.


Circuit:

Netlist:

* source NOR



X_U1A N01462 N01462 NOT $G_DPWR $G_DGND 7402 PARAMS:






X_U1D N01462 N01596 N01626 $G_DPWR $G_DGND 7402 PARAMS:


S1DSTM1

Implementation = A

S1DSTM2

Implementation = B

NOT

AND

OR

U1A

7402

2

31

U1B

7402

5

64

U1C

7402

8

910

U1D

7402

11

1213

U2A

7402

2

31

U2B

7402

5

64

V

V

V

V

V


X_U2A N01626 N01626 AND $G_DPWR $G_DGND 7402 PARAMS:


X_U2B N01664 N01654 OR $G_DPWR $G_DGND 7402 PARAMS:


Theory:

• NOR can be used as a universal gate as follows

• NOR as NOT A’=(A+A)’

• NOR as OR A*B=(A+B)’’.

• NOR as AND A*B=(A*B)’’=(A’+B’)’.

Procedure:








Conclusion:

Hence, we can conclude that NOR can be used as universal gate



PRACTICAL: 21

Aim: To designs PCB layout.

Software: Or-cad capture, Or-cad layout.

Circuit:

Figure 1: schematic diagram

Layout:

Figure 2: Layout diagram


Procedure:

Preparing a Capture design for Layout

• Create new project using PC –BOARD wizard.

• Preparing a Capture design for Layout is a two-part process. First, you must create a valid design and then create a netlist in an .MNL format for Layout. After you have prepared your Capture design, you can create a new Layout design using the .MNL netlist.


• In Capture, create a schematic design.

• As shown in fig.1 • Assign PCB footprints to each of your schematic parts. Use only Layout footprints,

selecting from those shown in the OrCAD Layout for Windows Footprint Libraries, or those in your custom footprint libraries.

• Layout cannot accept PCB footprint names or part values that include spaces. Check your design to eliminate spaces or tabs in these property values. Capture's spreadsheet editor is very useful for this.

• The layer names you use as property values must be among the standard Layout layer names.

• The via names you use as property values must be among the standard Layout via names.

To create a netlist for Layout

• Open the new Capture project. • In the project manager, select the Logical option. or If you intend to perform cross

probing or if you have a complex hierarchy, select the Physical option. • From the Tools menu, choose Create Netlist. The Create Netlist dialog box appears. • Choose the Layout tab. The Layout tab appears.


• In the PCB Footprint group box, ensure that {PCB Footprint} appears in the Combined property string text box.

•

• In the Netlist File text box, ensure that the path to the netlist file is correct. The netlist takes the name of the Capture project and adds an .MNL extension.

• Click OK. Capture processes the netlist, then creates an .MNL file and saves it in the directory specified in step 6.


• After Creating net list, you can either manually route or auto route.

• Click on option menu, and go on post process settings.


• For post- processing, Layout produces hardcopy on printers, and also produces GERBER file, DXF file, and a wide variety of report files.


• You can preview and edit your GERBER files with Layout’s external Gerber editor , which is known as gerb tool.

• After Post process click on windows menu in tile menu. • In the plot output file name column, select the layer you want to preview. Press the

right mouse button to display the pop-up menu, then choose preview. • Now go on auto menu and click on Run Post Processor


Out put file after Run Post Process

Component List (Generic) ***************************** REF DES VALUE PACKAGE FOOTPRINT X LOC Y LOC ROTATION ------------------------------------------------------------------------------------------------------- +5V O/P 2 UNIX2PIN -12.70 mm 17.78 mm 270 230V I/P 2 UNIX2PIN -81.28 mm 15.24 mm 90 C5 10NF/1000V CAP_NP CAP-MOV -78.74 mm 38.10 mm 270 C6 1000UF/25V CAP CAP200-400 -20.32 mm 43.18 mm 270 C9 1000UF/25V CAP CAP200-400 -10.16 mm 30.48 mm 180 D1 1N4007 1N4007 DIODE1N4007 -22.86 mm 55.88 mm 0 D2 1N4007 1N4007 DIODE1N4007 -22.86 mm 50.80 mm 0 T1 230V/9-0-9 1 AMP TRANSFORMER_CT_1 XMER 9-0-9 1AMP -50.80 mm 66.04 mm 270 U4 LM7805 LM7805C/TO VREG -12.70 mm 43.18 mm 0


BOTTOM LAYER

SILKSCREEN TOP LAYER


Conclusion:

Hence, we can conclude that Or-cad Layout is a powerful circuit PCB layout tool that has all the automated function which we need to quickly complete our PCB.


sdt lab manual - gecdahod.ac.in

Documents