semi networking day, milan networking day, milan dr dave thomas marketing director, etch products 20...

The information in the presentation is the property of SPTS and may not be duplicated, disclosed to any third party, or

used for any purpose other than that for which it is supplied without the written consent of SPTS.

‘Silicon etch solutions for emerging MEMS device

fabrication & advanced packaging technologies’

SEMI Networking Day, Milan Dr Dave Thomas

Marketing Director, Etch Products

20 September 2012

2 The information in the presentation is the property of SPTS and may not be duplicated, disclosed to any third

party, or used for any purpose other than that for which it is supplied without the written consent of SPTS.

©SPTS Technologies 2011. All rights reserved

■ About SPTS Technologies

■ Heritage & install base for DRIE

■ DRIE product evolution

■ Emerging Si etch requirements

■ Smaller features & higher ARs

■ Profile & bow control

■ Extendibility to deep sub-µm

■ Scallop control for smoother sidewalls

■ Tilt control

■ Uniformity & end-point control for Via Reveal

■ Summary

Contents




■ Specialise in Etch, CVD, PVD & thermal

processing equipment/process solutions

■ SPTS originally formed by SPP from the

merger in 2009 of STS & Aviza

Technology

■ History back to 1968

■ July 2011 MBO

■ Financed by PE firm Bridgepoint

■ 2 Manufacturing sites

■ Newport UK & San Jose CA

■ ~550 employees World-wide

■ Rapid growth

■ $215M in 2010

■ $296M in 2011

SPTS Technologies




■ SPTS supplies 26 of the top 30 MEMS companies &

all of the top 20 MEMS Foundries

■ >80% market share in ≤200mm DRIE

■ Total DRIE modules = 984

Leadership in DRIE for MEMS

Top 20 MEMS Foundries - 2011

First shipments of Bosch

licensed modules in 1995

Top 30 MEMS Companies - 2011

http://www.yole.fr/pagesAn/products/reports.asp




■ SPTS is PoR for Si etching at …

■ 8 customers producing CMOS

imagers using tapered TSVs on

200mm wafers

■ 3 of the top 5 OSATs using vertical

TSVs on 200mm wafers

■ All of the MEMS IDMs & Foundries

using TSVs on ≤200mm wafers

■ The top 5 Si Foundries

■ 2 of the top 5 OSATs on 300mm

wafers

■ All of the major R&D/Technical

Institutes

Etch Installs for Packaging Applications




SPTS DRIE Product Evolution

Pegasus

Rapier

ICP

HDP source

Decoupled sources

Combined source

ProNova2

Pegasus

DSi

Pegasus

Patented dual source design




Smaller Features, Higher ARs

Established

devices Emerging devices




■ 8 x 180µm trench TSV

Profile Control, Eliminating Bow




■ Ability to cope with future device dimensions

Extendibility to Sub-Micron Features

1µm spacing

150nm

50nm

10µm spacing

■ … and all with a single hardware set




Scallop Control = Smoother Walls

Faster gas switching Modify chemistry

2.7 x 55µm trench

<20nm Sc

10 x 70µm TSV

<30nm Sc

Base

Top

5 x 50µm TSV

~5nm ‘waves’

<20nm Sc <10nm Sc 80 x 500nm trenches

~5nm ‘waves’




■ Rapier dual source ‘lifts’ plasma

density towards wafer edge

■ Controls tilt & maintains high rate

Controlling Profile Tilt

Line of best fit

indicates <±0.05°

A. Double sided optical

200mm wafers

B. Quadrature offset (Qbias)

150mm wafers

8µm x 165µm Trench

PoR (AMMS) Rapier




Process Flexibility for 3D-IC

Interposer TSV Via Middle TSV

Silicon Etching

Dielectric Etching

■ Multiple etches

from single

hardware set

Top

Mid

Base

No oxide

Via Last TSV

Tapered

100 µm diam

No scallops

Via Last TSV

Vertical

Low AR

High AR

50 x 120 µm

<160 nm Sc

20 x 160 µm

<160 nm Sc 10 x 100 µm

<70 nm Sc 5 x 50 µm

<6 nm Sc 50 x 100 µm

<150 nm Sc 20 x 100 µm

<150 nm Sc

Via Last

Oxide liner etch




Via Reveal Process Flow

TSV wafer

Si is ground short of Cu nodes

Carrier wafer

(Si or Glass)

Glue layer

TSVs

Si wafer

Exposed TSVs with

liner oxide intact

Si etch

Dielectric

deposition

No exposure of Si

to Cu in TSVs

- Requires oxide

selectivity

CMP or

dielectric etch

Exposed Cu ready for

metal re-distribution

Low temperature

Typically <180°C




Si Etch for Via Reveal

>5 µm/min

±2.5% 3mm EE

160:1 to blanket oxide

Bulk Si result

Si/Glass bonded TSV wafer

Reveal

height ~5 µm

Successful stop on

liner oxide




■ Before reveal, prior steps contribute to NU

■ TSV etch uniformity

■ Grinding uniformity

■ Use different etch modes of Rapier to adjust NU

2 Step Approach - Dealing with Incoming NU

Rapier mode DSi mode ‘RIE’ mode

Edge fast Centre fast Uniform

2.7µm/min ±4.3%




■ Examples from 2 x Customers – 300mm TSV wafers

REVIA™ Si Etch Endpoint

Customer A

Single step

Rapier mode

5 consecutive wafers

Detection capability

to <0.01% TSV area

Patents applied for

Variable end-point

time due to

differing grind

thicknesses of Si

Customer B

2 step

RIE + DSi mode

2 consecutive wafers




■ SPTS has a leadership position in DRIE for MEMS & Adv

Packaging

■ DRIE module development/evolution has led to a unique dual

source design

■ Emerging devices require increasing levels of process & on-

wafer control

■ Currently it is possible to ….

■ Etch trenches at 0.4µm and 90:1 AR

■ Eliminate bow & control across wafer etch profiles to <0.06° at

22:1 AR

■ Extend DRIE to 50nm feature size

■ Virtually eliminate scalloping by faster switching and chemistry

adjustment

■ Control profile tilt to <±0.1°

■ Reveal TSVs at >5µm/min & ±2.5% uniformity

■ End-point the VR process, eliminating re-work & wafer scrap

Summary

semi networking day, milan networking day, milan dr dave thomas marketing director, etch products 20...

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