semiconductor physics course final presentation...

1

Semiconductor Physics CourseFinal Presentation

“CMOS Fabrication”by Özgür Çobanoğlu

(Turin, 2006)

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

OutlineSections and Contents of the Presentation

2

➢ What is MOS ?➢ The structure of simplest device

➢ How does MOS behave in low level ?➢ MOS capacitor under external bias

➢ Can we produce something useful out of it ?➢ Diode, transistor etc.

➢ How to build an actual MOSFET ?➢ A useful device

➢ Fabrication Process Steps➢ Crystal growth, substrate formation➢ Lithography (Photo resist, Exposure, Development, etching)➢ Ion implantation, passivation, protective layer formation

➢ Example “beasts” we develop➢ Read-out & communication chips for High Energy Physics (HEP) experiments➢ General purpose processors

MOS StructureMetal, Oxide and Semiconductor Capacitor Structure

3

Intrinsic Fermi level

● In the p-silicon we have positively charged mobile holes, and negatively charged fixed acceptors.

● Ef goes down with the effect of

impurities (e.g. Boron as acceptor)

Formation :● Acceptor dep.● Heat treatment● Polysilicon dep.

np=ni2 1

npo≃ni

2

NA

2

ppo≃NA 3

Fp=kTq

ln ni

NA

4

Fp=kTq

ln ND

ni

5

➢ Mass Action Law (1)➢ Electron (2) & hole (3) concentrations➢ Fermi potentials for p-type (4) & n-type (5)

Ef

● [0]

[8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

MOS BiasingThe MOS Capacitor System under External Bias

4

The positive charge pushes the holes away from the region under the gate and uncovers some of the negative charged fixed acceptors. Now the electric field points the other way, and goes from the positive gate charge, terminating on the negative acceptor charge within the silicon.

An electric field develops between the positive holes and the negative gate charge. Note that the gate and the substrate form a kind of parallel plate capacitor, with the oxide acting as the insulating layer in-between them (Accumulation).

EfEf

[8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

MOS Biasing (Cont'd)The MOS Capacitor System under External Bias

5

If the bending increases, Ec the conduction band edge, and Ef the Fermi level start to get closer which means that n the electron concentration, should soon start to become significant. In the situation represented by the first figure, we say we are at the threshold, and the gate voltage Vg at this point is called the threshold voltage Vt.

Even though, we have increased Vg beyond the threshold voltage Vt, and more positive charge appeared on the gate, the depletion region no longer moves back into the substrate. Instead electrons start to appear under the gate region, and the additional electric field lines terminate on these new electrons, instead of on additional acceptors. We have created an inversion layer of electrons under the gate, and it is this layer of electrons which we can use to connect the two n-type regions in a MOS transistor..

[8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

MOS Biasing SummaryThe MOS Field Effect Transistor - Structure

6

Accumulation occurs typically for negative voltages where the negative charge on the gate attracts holes from the substrate to the oxide-semiconductor interface.

Depletion occurs for positive voltages; the positive charge on the gate pushes the mobile holes into the substrate, thereby depleting the semiconductor of the mobile carriers. The voltage separating the accumulation and depletion regime is referred to as the flat-band voltage.

Inversion occurs at more positive voltages which are larger than the threshold voltage. In addition to the depletion layer charge, a negatively charged inversion layerforms at the oxide-semiconductor interface.

[8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

MOSFETThe MOS Field Effect Transistor

7







Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

MOSFET - StructureThe MOS Field Effect Transistor - Structure

8

LW

Principle :

Control the current flowing through Drain-Source terminals by adjusting the electric field the Gate potential creates.

As the Vgs increases, first the depletion region (Vgs<Vth) and then the inversion layer (Vgs>Vth) are formed.

● [0]

[3]

[8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

MOSFET - OperationThe MOS Field Effect Transistor - Operation

9

I DS , SAT=±12N /P COX

WLV GS−V THN , THP

2

I DS , TRI=±N /P COX

WL [V DS V GS−VTHN ,THP−

12

V DS2 ]

V TH=V THN , THPN ∣2FV SB∣−∣2F∣

.....................

.....................

[3]

[5]

[6]

[6]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Non-IdealitiesThe MOSFET “Channel Length Modulation” Effect

10



2 1V DS



2

One of several short channel effects in CMOS scaling, Channel Length Modulation (CLM) is the effect of a pinch-off region forming before the drain under large drain bias. This shortens the channel region, and leaves a gap of un-inverted silicon between the end of the formed inversion layer.

Id expression is valid until the pinch-off point; the additional term comes due to the region between pinch-off point and the drain.

GCA is (Gradual Channel Approximation)Together with the effect of Channel Length Modulation

[3]

[6]

ro

T

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Non-Idealities (Cont'd)The MOSFET “Bulk Effect”

11

V TH=V THN , THPN ∣2FV SB∣−∣2F∣[6]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Down-Scaling EffectsSmall Geometry Effects

12

➔ Constant-Field Scaling Effect● Tries to preserve the magnitude of internal electric fields; dimensions are

scaled down and supply voltage is reduced accordingly.

➔ Constant Voltage Scaling Effect● Dimensions are reduced and the supply voltages remain unchanged; doping

concentrations are increased.

➔ Narrow-Channel Effects● The most significant one is that the threshold voltage of such a device is

larger than the calculated one.

➔ Short-Channel Effects● the limitations imposed on electron drift characteristics in the channel● modification of threshold voltage due to shortening channel length

➔ Other Limitations Imposed by Small-Device Geometries● Sub-threshold conduction (Drain Induced Barrier Lowering DIBL)● Punch-through (Depletion regions of D & S merge, FET melts locally)● Everything can NOT be scaled down arbitrarily like t

ox (pinholes on the oxide

can short an active area to gate, oxide breakdown● Hot carriers can be injected to gate oxide degrading the device

characteristics, injection occurs in the vicinity of drain junction.● Interconnect damage due to electro-migration● Electrostatic discharge (ESD)● Electrical over-stress (EOS)

● [0]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Parasitic DevicesSmall Geometry Effects

13

➢ At least, two arbitrarily selected layer form a “parasitic device”

➢ Parasitic capacitance is inevitable.

Capacitance

M1

M2

[6]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

CMOS FabricationActual Implementation

14







Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Process CycleActual Fabrication via Lithographic Layout Formation Processes

15

The following section will deal with the CMOS fabrication technology which requires both n & p-channel transistors to be built on the same substrate.

The simplified process sequence for the fabrication of CMOS integrated circuits on a p- type silicon substrate is shown.

A grown ingot to be sliced into “wafers”.

The lithographic sequence is repeated for each physical layer used to construct IC. Sequence is always the same:

● Photoresist application● Printing (exposure)● Development● Etching

.

[0]

[2]

[8]

Finalize

.

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

MOS LayoutActual Fabrication via Lithographic Layout Formation Processes

16

To accommodate both nMOS and pMOS devices, special regions must be created in which the semiconductor type is opposite to the substrate type. These regions are called wells or tubs.

A p-well is created in an n-type substrate or, alternatively, an n- well is created in a p-type substrate. In the simple n-well CMOS fabrication technology, the nMOS transistor is created in the p-type substrate, and the pMOS transistor is created in the n-well, which is built-in into the p-type substrate.

Metal

FOX

Active AreaPolysilicon

Substrate

[0]

[8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

One Lithography CycleActual Fabrication via Lithographic Layout Formation Processes

17

Each processing step requires that certain areas are defined on chip by appropriate masks. Consequently, the integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxide. In general, a layer must be patterned before the next layer of material is applied on chip. The process used to transfer a pattern to a layer on the chip is called lithography.

The sequence starts with the thermal oxidation of the silicon surface, by which an oxide layer of about 1 micrometer is created on the substrate, see (b).

The entire oxide surface is covered with a layer of photoresist, which is a light-sensitive, acid-resistant organic polymer, initially insoluble in the developing solution (c).

The photoresist material is exposedto ultraviolet (UV) light, the exposed areas become soluble so that they are no longer resistant to etching solvents (d).

[0]

[0]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

One Lithography Cycle (Cont'ed)Actual Fabrication via Lithographic Layout Formation Processes

18

After hardening the remaining photoresist covered area; a solvent removes (etching) the soluble parts of the applied photresist (e). During this process, oxide layer is also etched down till the substrate layer (f).

After that, photoresist can be removed by another solvent (f) which does not attack the substrate, so that the silicon layer is left patterned as required.

Above is what we achieved during this 7-step process.

[0]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

SummaryActual Fabrication via Lithographic Layout Formation Processes

19

Grow crystalline silicon (1); make a wafer (2–3); grow a silicon dioxide (oxide) layer in a furnace (4); apply liquid photoresist (resist) (5); mask exposure (6); a cross-section through a wafer showing the developed resist (7); etch the oxide layer (8); ion implantation (9–10); strip the resist (11); strip the oxide (12).

Steps similar to 4–12 are repeated for each layer (typically 12–20 times for a CMOS process).

[8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Forming an nMOS TransistorActual Fabrication via Lithographic Layout Formation Processes

20

● Nitride defines the active areas

● FOX is developed

● Nitride is removed by a solvent

● Polysilicon is deposited

[0]

[7]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Forming an nMOS Transistor (Cont'd)Actual Fabrication via Lithographic Layout Formation Processes

21

● Spacer & active field formation

● Dep. of SiO2

● Etching contact holes

● Metal dep.

[0]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Forming an Inverter - 1st StepActual Fabrication via Lithographic Layout Formation Processes

22

● To be able to place nMOS & pMOS devices on the same substrate, so called N-Well process has been developed.

[4]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Forming an Inverter - 2nd StepActual Fabrication via Lithographic Layout Formation Processes

23

Definingactiveareas

n-well

Silicon NitrideStress-relief oxide

p-type

Active mask

[2]

[4]

[7]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Forming an Inverter - 3rd StepActual Fabrication via Lithographic Layout Formation Processes

24

[4]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

n-well

p-type

Polysilicon gatePolysilicon mask

Forming an Inverter - 4th StepActual Fabrication via Lithographic Layout Formation Processes

25

● All the MOSFET gates are defined in a single step

● The polysilicon gate can be doped (n+) while is being deposited to lower its parasitic resistance (important in high speed fine line processes)

[2]

[4]

[7]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu


26

The process is self-aligned

[4]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu


27

Annealing● After the implants are completed a thermal annealing cycle is executed● This allows the impurities to diffuse further into the bulk● After thermal annealing, it is important to keep the remaining process

steps at as low temperature as possible

[2]

[4]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu


28

Mask for contacts

● Contact cuts are defined by etching SiO2 down to the surface to be contacted

● These allow metal to contact diffusion and/or polysilicon regions

● The surface of the IC is covered by a layer of CVD oxide– The oxide is deposited at low temperature (LTO) to avoid that

underlying doped regions will undergo diffusive spreading

[2]

[4]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

[7]


29

• Metals may react with nearby materials, and may have to be encapsulated using nitrides (e.g. Si3N4

or TiN) to prevent unwanted reactions, or partial erosion in subsequent etching procedures. [2]

[4]

Final form

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu


30

[4]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Forming an Inverter - SummaryActual Fabrication via Lithographic Layout Formation Processes

31

Create N-WellDefine actives & FOXPolysilicon dep.

2

S/D implantationSiO

2 dep. & contact etch

M1 dep.

SiO2 dep. & via etch

M2 depositionFinal w/o oxide layers

[0]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

FinalizationOver glass and pad openings

32

Over glass and pad openings● A protective layer is added over the surface:● The protective layer consists of:

– A layer of SiO2

– Followed by a layer of silicon nitride● The SiN layer acts as a diffusion barrier

against contaminants (passivation)● Finally, contact cuts are etched, over metal

2, on the passivation to allow for wire bonding.

[2]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Design RulesImportant Link in the Lithography Chain

33

Designer :● Designing the circuit in

building block and schematic levels

● Drawing the "layer" patterns on a layout editor

Silicon Foundry :● Mask generation from the

layer patterns in the design data base

● Printing: transfer the mask pattern to the wafer surface

● Process the wafer to physically pattern each layer of the IC

Reasons :● Rules originating from the

reliability of the materials and the system they form

[2]

[6] [8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Design Rules (Cont'd)Important Link in the Lithography Chain

34

● Interface between the circuit designer and process engineer

● Guidelines for constructing process masks

● Unit dimension: minimum line width

➢ scalable design rules: lambda parameter

➢ Absolute dimensions: micron rules

● Rules constructed to ensure that design works even when small fab. errors (within some tolerance) occur

● A complete set includes➢ set of layers ➢ intra-layer:relations

between objects in the same layer

➢ inter-layer:relations between objects on different layers

[0]

[2]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Design Rules (Cont'd)Important Link in the Lithography Chain

35

[0] [8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Design Rules (Cont'd)A Couple of Design Tabus

36

● Never put transistors in mixed directions (put all of them preferably vertical)● Substrate is tilted to prevent channeling of dopant ions● Shadowed areas would differ leading to matching problems; even to chip failure

● Never pass-over one of the two transistors with a wire whereas matching is important● Capacitive transistor model changes leading to e.g. different speed characteristics

● Psychology of the devices must be identical● Dummy elements must be used to create the same environment for every

corresponding device; devices are NOT isolated perfectly

Implant

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Design Rules (Cont'd)A Couple of Design Tabus

37

● Never put long wires; switch between different layers via “via”s.

● Never connect a long M1 wire to a gate polysilicon (unless gate is connected to an active)● Etching in the next step can load gate excessively; leading to oxide bread-down● Put short M1 then a long M2; this would prevent gate loading during processing

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

What We HaveState of Art

38

Transceiver Chip

10-Bits D/A Converter Core

Bit Slice

– Up to eight metal levels in modern processes

– Copper for metal levels 2 and higher– Stacked contacts and vias

– Chemical Metal Polishing for technologies with several metal levels

– For analogue applications some processes offer:● capacitors● resistors● bipolar transistors (BiCMOS)● etc.

– Shallow trench isolation– n+ and p+-doped polysilicon gates (low threshold)– source-drain extensions LDD (hot-electron effects)– Self-aligned silicide (spacers)– Non-uniform channel doping (short-channel effects)

[2]

[2]

● Tools for “real simulations” :● Cadence (commercial, for real-world production)● Elektrik (open source, schematic, layout, analog, digital)● Qucs (open source, schematic, limited layout, analog, digital)

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

– Up to eight metal levels in modern processes

– Copper for metal levels 2 and higher– Stacked contacts and vias

– Chemical Metal Polishing for technologies with several metal levels

– For analogue applications some processes offer:● capacitors● resistors● bipolar transistors (BiCMOS)

– Shallow trench isolation– n+ and p+-doped polysilicon gates (low threshold)– source-drain extensions LDD (hot-electron effects)– Self-aligned silicide (spacers)– Non-uniform channel doping (short-channel effects)

What We HaveState of Art

39

Transceiver Chip

10-Bits D/A Converter Core

Bit Slice

[6]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Fabrication DetailsAlternative and/or Advanced Fabrication Steps

40







● Etching types● Wet chemical, dry (plasma assisted), ion

● Lithography types● Optic, electron beam, x-ray, ion beam

● Deposition types● Ion, CVD, PVD

● XXXresist details● Positive, negative, polymers as electron resists

● Advanced Processes● Twin-Tub(Well) CMOS Process● Silicon on insulator (SOI) CMOS Process

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

PhotoresistHowto

41

• Photoresist normally comes in powder form, which is insensitive to light. It is reconstituted into liquid form by adding a solvent, typically alcohol.

•

• The wafer is mounted on a turntable, spinning slowly, and the photoresist is discharged into its center. Centrifugal force spreads the resist outward across the wafer. The thickness that remains on the wafer is a function of the rate of wafer spin and the viscosity of the photoresist. The thickness is monitored by light diffraction, which is used to adjust the spin rate to reach the correct PR thickness.

• After the PR is applied, the wafer is heated (~160C) to evaporate the solvent, leaving a smooth solid coating.

Pha se Interference g iv es Photoresist Thick ness

– The wafer is heated to harden the patterned resist so that it will withstand immersion into acids. A typical hardening bake is ~300C.

– In rare cases, the photoresist is not adequate as a mask itself, and the patterns are processed to make a more robust mask, e.g. of thick SiO2 (for very high energy implants) or Si3N4 for solvent etches which also attack PR.

[1]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Lithography TypesOptic

42

The name optical lithography comes from the early application where the exposing energy was visible light. While those wavelengths can still be used, the push to reduce the size of feature sizes has lead to the use of shorter wavelengths to increase resolution. Ultraviolet (UV) and deep ultraviolet (DUV) sources are now used. Such sources include excimer lasers which operate at wavelengths of 248 nm, 193 nm, and less. Visible wavelengths end in the red at about 400 nm. At these shorter wavelengths, particularly 193 nm, optical materials and even air absorb the energy very well and there are still many problems to be overcome when using this wavelength.

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Lithography Types (Cont'd)X-Ray

43

Collimated x-rays as the exposing energy

Lower in wavelength; better resolution

Allows micro structures with great height to be fabricated, relative to optical lithography

Lithography process uses different materials (e.g. gold as absorber)

Mask substrate is normally a low atomic number material such as diamond, beryllium, or polyimide, or a thin membrane of a higher atomic number material such as silicon or silicon carbide. The substrate is, again, any structural material which fits the particular application and the photoresist of choice is polymethyl methacrylate (PMMA)

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Lithography Types (Cont'd)X-Ray

44

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

(There are also ion & electron beam lithographies other than mentioned here)

EtchingHowto

45

anisotropic etch (ideal)resist

layer 1

layer 2

resist

layer 1

layer 2

isotropic etchundercut

resist

layer 1

layer 2

preferential etchundercut

● Etching :– Process of removing unprotected

material– Etching occurs in all directions– Horizontal etching causes an

under cut– “preferential” etching can be

used to minimize the undercut

● Etching techniques :– Wet etching : uses chemicals to

remove the unprotected materials

– Dry or plasma etching : uses ionized gases rendered chemically active by an rf-generated plasma [1]

[2]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Chemical Vapor DepositionHowto

46

• SiH4(gas) + O2(gas) -> SiO2(solid) + 2H2 (gas)

• SiH4(gas) + H2(gas) +SiH2(gas) -> 2H2(gas) + PolySilicon (solid)

[1]

[8]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

For inexpensive and low-performance chips, one may use a heavily doped substrate and omit one well. The substrate should be doped to about 1016/cm3, with a resistivity of about 1 Ω-cm. This allows simpler construction, with good “Ground Potential” distribution, but the devices are not optimal and there is a chance of latch-up if the voltages are pushed hard.

For high-performance chips, one uses a low doped substrate, 1015/cm3, 10 Ω-cm, and then constructs Two Wells at optimum doping levels (called Tubs in the diagram). Since the substrate is lightly doped, there is less chance for latch-up because of the high resistivity.

Twin-Tub CMOS ProcessHowto

[1]

[8]

47

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

Twin-Tub CMOS Process (Cont'd)Howto

● This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently.

● Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer (~1015/cm3) on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed.

● Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics.

• In the conventional n-well CMOS process, the doping of the well region is typically about one order of magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics (possible latch-up). The twin-tub process, below, avoids this problem.

[8]

48

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

● Rather than using silicon as the substrate material, an insulating substrate will improve process characteristics such as speed and latch-up susceptibility.

● The SOI CMOS technology allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.

● The main advantages of this technology are

– the higher integration density (because of the absence of well regions)

– complete avoidance of the latch-up problem

– lower parasitic capacitances compared to the conventional n-well or twin-tub CMOS processes.

● A cross-section of nMOS and pMOS devices in created using SOI process is shown below.

Silicon On Inculator CMOS ProcessHowto

49

[1]

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

ReferencesThroughout the presentation

● [0] CMOS Digital Integrated Circuit Design - Analysis and Design by S.M. Kang and Yusuf Leblebici

● [1] S.M. Sze, VLSI Technology, New York, NY: McGraw-Hill, 1983.● [2] Paulo Moreira, “ELEC-2002_11Apr02_3.ppt”● [3] Design of Analog CMOS Integrated Circuits by Behzad Razavi, McGraw-

Hill Higher Education; ISBN: 0072380322● [4] CSE/EE 462: VLSI Design Fall 2004, The CMOS Fabrication Process and

Design Rules by Jay Brockman● [5] CMOS Circuit Design, Layout, and Simulation by R. Jacob Baker, Harry

W. Li, David E. Boyce, IEEE Press Series on Microelectronic Systems; IEEE; ISBN: 0780334167

● [6] Web resources, http://www.ph.unito.it/~cobanogl● [7] Bell-Labs, web resources● [8] Anonymous web resources

50

Sem

iconduct

or

Physi

cs C

ours

e (

20

06

)Fi

nal Pre

senta

tion o

n “

CM

OS F

abri

cati

on”

by Ö

zgür

Çobanoğlu

http://www.ph.unito.it/~cobanogl

semiconductor physics course final presentation...

Documents