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ICCAD96IEEE/ACM International Conference on

Computer Aided Design

Red Lion HotelSan Jose, CA

November 10-14, 1996

ICCAD ‘96 Proceedings © 1996 by IEEE. All rights reserved. No part of this book may be reproduced in any form, nor may it be stored in a retrievalsystem or transmitted in any form without written permission of IEEE.

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ICCAD96:

Cover Page Front Matter Table of Contents Session Index Author Index

IEEE Computer Society Press The Institute of Electrical and Electronics Engineers, Inc.

IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN

A CONFERENCE FOR THE EE CAD PROFESSIONAL

I C C A D 96

NOVEMBER 10-14, 1996

RED LION HOTEL

SAN JOSE, CALIFORNIA

IEEE/ACM DIGEST OF TECHNICAL PAPERS

THE INSTITUTE OF ELECTRICALAND ELECTRONICS ENGINEERS, INC.ELECTRON DEVICES SOCIETY

ASSOCIATION FOR COMPUTING MACHINERYSpecial Interest Group on Design Automation

In cooperation with:

Sponsored by:

special interest group on

des ign au tomat ion

®

Technical Committee on Design Automation®

Table of Contents

Foreword.............................................................................................................................. xivConference Committee ........................................................................................................xvTechnical Program Committee........................................................................................ xviReviewers........................................................................................................................... xviiiTutorial 1: IC Interconnect Design Solutions.............................................................. xxiTutorial 2: Circuit Tuning for High-Performance Custom Digital Design ........... xxiiTutorial 3: Design and Test of Core-Based Systems ................................................. xxiiiTutorial 4: Verification of Electronic Systems ...........................................................xxivPanel: Is Corporate CAD Back? ......................................................................................xxvPanel: Intranets and EDA: Impact, Application, and Technology..........................xxvi

Session 1A: Technology MappingModerators: Sujit Dey, C&C Research Labs., NEC USA, Inc., Princeton, NJ Bob Francis, Xilinx, Inc., Toronto, Ontario, Canada

1A.1 Logic Optimization by Output Phase Assignment in Dynamic Logic Synthesis ............................................................................................................... 2

R. Puri, A. Bjorksten, and T.E. Rosser1A.2 A New Method Towards Achieving Global Optimality in Technology Mapping....................................................................................................... 9

W. Xiaoqing and K.K. Saluja1A.3 An Iterative Area/Performance Trade-Off Algorithm for LUT-Based FPGA Technology Mapping ...........................................................................................13

J-D. Huang, J-Y. Jou, and W-Z. Shen

Session 1B: Interconnect Characterization and AnalysisModerators: John Cohn, IBM Corp., Richmond, VT Chandu Visweswariah, IBM Corp., Yorktown Heights, NY

1B.1 An Efficient Approach for Moment-Matching Simulation of Linear Subnetworks with Measured or Tabulated Data ..........................................................20

G. Zheng, Q-J. Zhang, M. Nakhla, and R. Achar1B.2 Automatic Netlist Extraction for Measurement-Based Characterization of Off-Chip Interconnect ....................................................................24

S.D. Corey and A.T. Yang1B.3 Analytical Delay Models for VLSI Interconnects Under Ramp Input ...........................30

A.B. Kahng, K. Masuko, and S. Muddu

Session 1C: High Performance Routing SynthesisModerators: Chung Kuan Cheng, University of California, San Diego, CA Ren-Song Tsay, ArcSys, Inc., Sunnyvale, CA

1C.1 Optimal Non-Uniform Wire-Sizing under the Elmore Delay Model .............................38 C-P. Chen, H. Zhou, and D.F. Wong

1C.2 Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization ................................................................................44

T. Okamoto and J. Cong1C.3 Clock Tree Synthesis for Multi-Chip Modules ...............................................................50

D. Lehther and S.S. Sapatnekar

Session 1D: Sequential Circuit TestingModerators: Janusz Rajski, Mentor Graphics Corp., Wilsonville, OR Sandeep Gupta, University of Southern California, Los Angeles, CA

1D.1 Sequential Redundancy Identification Using Recursive Learning ...............................56 W. Cao and D.K. Pradhan

1D.2 Identification of Unsettable Flip-Flops for Partial Scan and Faster ATPG ..................................................................................................................63

I. Hartanto, V. Boppana, and W.K. Fuchs1D.3 Simulation-Based Techniques for Dynamic Test Sequence Compaction ......................67

E.M. Rudnick and J.H. Patel

Session 2A: Formal Verification IModerators: Jerry Burch, Cadence Design Systems, Inc., Berkeley, CA Felice Balarin, Cadence Berkeley Labs., Berkeley, CA

2A.1 Tearing Based Automatic Abstraction for CTL Model Checking...................................76 W. Lee, A. Pardo, J-Y. Jang, G. Hachtel, and F. Somenzi

2A.2 CTL Model Checking Based on Forward State Traversal .............................................82 H. Iwashita, T. Nakata, and F. Hirose

2A.3 VERILAT: Verification Using Logic Augmentation and Transformations..............................................................................................................88

D.K. Pradhan, D. Paul, and M. Chatterjee

Session 2B: System Design: Synthesis and CompilationModerators: Rajesh K. Gupta, University of Illinois, Urbana, IL Hiroto Yasuura, Kyushu University, Fukuoka, Japan

2B.1 Software Synthesis through Task Decomposition by Dependency Analysis .................98 Y. Shin and K. Choi

2B.2 Synthesis of Reusable DSP Cores Based on Multiple Behaviors .................................103 W. Zhao and C.A. Papachristou

2B.3 Algorithms for Address Assignment in DSP Code Generation....................................109 R. Leupers and P. Marwedel

Session 2C: Timing AnalysisModerators: Marios Papaefthymiou, Yale University, New Haven, CT Thomas G. Szymanski, AT&T Bell Labs./Lucent Technologies, Murray Hill,NJ

2C.1 An Approximate Timing Analysis Method for Datapath Circuits ...............................114 H. Yalcin, J.P. Hayes, and K.A. Sakallah

2C.2 Static Timing Analysis for Self Resetting Circuits ......................................................119 V. Narayanan, B.A. Chappell, and B.M. Fleischer

2C.3 Timing Verification of Sequential Domino Circuits .....................................................127 D. Van Campenhout, T. Mudge, and K.A. Sakallah

Session 2D: Support for High Level DesignModerator: Michaela Guiney, Hewlett-Packard Co., Palo Alto, CA

2D.1 Basic Concepts for an HDL Reverse Engineering Tool-Set .........................................134 G. Lehmann, B. Wunder, and K.D. Müller-Glaser

2D.2 Sensitivity Analysis of Iterative Design Processes ......................................................142 E.W. Johnson, J.B. Brockman, and R. Vigeland

2D.3 Validation Coverage Analysis for Complex Digital Designs........................................146 R.C. Ho and M.A. Horowitz

Session 3A: Power and Performance in High Level SynthesisModerators: Forrest Brewer, University of California, Santa Barbara, CA Wolfgang Rosenstiel, University Tuebingen, Tuebingen, Germany

3A.1 Clock-Driven Performance Optimization in Interactive Behavioral Synthesis...........154 H-P. Juan, D.D. Gajski, and V. Chaiyakul

3A.2 Register-Transfer Level Estimation Techniques for Switching Activity and Power Consumption ................................................................................158

A. Raghunathan, S. Dey, and N.K. Jha3A.3 Exploiting Regularity for Low-Power Design ..............................................................166

R. Mehra and J. Rabaey

Session 3B: High-Performance Circuit OptimizationModerators: Willem Van Bokhoven, Eindhoven University of Technology, Eindhoven, The Netherlands Georges Gielen, Katholieke University, Heverlee, Belgium

3B.1 Optimization of Custom MOS Circuits by Transistor Sizing.......................................174 A.R. Conn, P.K. Coulman, R.A. Haring, G.L. Morrill, and C. Visweswariah

3B.2 An Efficient Approach to Simultaneous Transistor and Interconnect Sizing .............181 J. Cong and L. He

3B.3 Generalized Constraint Generation in the Presence of Non-Deterministic Parasitics.......................................................................................187

E. Charbon, P. Miliozzi, E. Malavasi, and A.L. Sangiovanni-Vincentelli

Session 3C: Circuit PartitioningModerators: Jason Cong, University of California, Los Angeles, CA Rajeev Jayaraman, Xilinx, Inc. San Jose, CA

3C.1 VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques ............................................................................................194

S. Dutt and W. Deng3C.2 Multi-Level Spectral Hypergraph Partitioning with Arbitrary Vertex Sizes..............201

J.Y. Zien, M.D.F. Schlag, and P.K. Chan3C.3 Minimum Replication Min-Cut Partitioning................................................................205

W-K. Mak and D.F. Wong

Session 3D: ATPGModerators: Wolfgang Kunz, Texas A&M University, College Station, TX Dhiraj K. Pradhan, Texas A&M University, College Station, TX

3D.1 Compact and Complete Test Set Generation for Multiple Stuck-Faults .....................212 A. Agrawal, A. Saldanha, L. Lavagno, and A. Sangiovanni-Vincentelli

3D.2 GRASP—A New Search Algorithm for Satisfiability...................................................220 J.P. Marques Silva and K.A. Sakallah

3D.3 Driving Toward Higher IDDQ Test Quality for Sequential Circuits: A Generalized Fault Model and Its ATPG...................................................................228

H. Kondo and K-T. Cheng

Session 4A: Embedded TutorialPresenter: Edward A. Lee, University of California, Berkeley, CA4A Comparing Models of Computation..............................................................................234

E.A. Lee and A. Sangiovanni-Vincentelli

Session 4B: Embedded TutorialPresenters: Nick P. van der Meijs, Delft University of Technology,

Delft, The NetherlandsTheo Smedes, Philips Semiconductor, Nijmegen, The Netherlands

4B Accurate Interconnect Modeling: Towards Multi- Million Transistor Chips as Microwave Circuits .......................................................................................244

N.P. van der Meijs and T. Smedes

Session 5A: Implication-Based Logic SynthesisModerators: Michel Berkelaar, Eindhoven University of Technology, Eindhoven, The Netherlands Albert Wang, Synopsys, Inc., Mountain View, CA

5A.1 A New Method to Express Functional Permissibilities for LUT Based FPGAs and Its Applications ..............................................................................254

S. Yamashita, H. Sawada, and A. Nagoya5A.2 Fast Boolean Optimization by Rewiring ......................................................................262

S-C. Chang, L.P.P.P. van Ginneken, and M. Marek-Sadowska5A.3 Multi-Level Logic Optimization for Low Power Using Local Logic Transformations...........................................................................................................270

Q. Wang and S.B.K. Vrudhula

Session 5B: Advanced Numerical Simulation TechniquesModerators: Chandu Visweswariah, IBM Corp., Yorktown Heights, NY Willem Van Bokhoven, Eindhoven University of Technology, Eindhoven, The Netherlands

5B.1 Reduced-Order Modeling of Large Passive Linear Circuits by Means of the SyPVL Algorithm...............................................................................................280

R.W. Freund and P. Feldmann5B.2 A Coordinate-Transformed Arnoldi Algorithm for Generating Guaranteed Stable Reduced-Order Models of RLC Circuits .......................................288

L.M. Silveira, M. Kamon, I. Elfadel, and J. White

5B.3 Computation of Circuit Waveform Envelopes Using an Efficient,

Matrix-Decomposed Harmonic Balance Algorithm.....................................................295 P. Feldmann and J. Roychowdhury

Session 5C: Robust RoutingModerators: Gary Yeap, Motorola, Inc., Tempe, AZ Takashi Kambe, SHARP Co., Nara, Japan

5C.1 Post Global Routing Crosstalk Risk Estimation and Reduction ..................................302 T. Xue, E.S. Kuh, and D. Wang

5C.2 An Optimal Algorithm for River Routing with Crosstalk Constraints ........................310 H. Zhou and D.F. Wong

5C.3 Jitter-Tolerant Clock Routing in Two-Phase Synchronous Systems ...........................316 J.G. Xi and W.W-M. Dai

Session 5D: BIST and DFTModerators: Yervant Zorian, Lucent Technology, Princeton, NJ Robert C. Aitken, Hewlett-Packard Co., Palo Alto, CA

5D.1 Enhancing High-Level Control-Flow for Improved Testability...................................322 F.F. Hsu, E.M. Rudnick, and J.H. Patel

5D.2 A Design for Testability Technique for RTL Circuits Using Control/Data Flow Extraction......................................................................................329

I. Ghosh, A. Raghunathan, and N.K. Jha5D.3 Bit-Flipping BIST.........................................................................................................337

H-J. Wunderlich and G. Kiefer

Session 6A: Formal Verification IIModerators: Fabio Somenzi, University of Colorado, Boulder, CO Ellen M. Sentovich, Ecole des Mines de Paris, Sophia-Antipolis, France

6A.1 Using Complete-1-Distinguishability for FSM Equivalence Checking........................346 P. Ashar, A. Gupta, and S. Malik

6A.2 Improved Reachability Analysis of Large Finite State Machines................................354 G. Cabodi, P. Camurati, and S. Quer

6A.3 ACV: An Arithmetic Circuit Verifier ............................................................................361 Y-A. Chen and R.E. Bryant

Session 6B: Yield and Technology ModelingModerators: Jacob K. White, Massachusetts Institute of Technology, Cambridge, MA David Ling, IBM Corp., Yorktown Heights, NY

6B.1 Interconnect Yield Model for Manufacturability Prediction in Synthesis of Standard Cell Based Designs ..................................................................368

H.T. Heineken and W. Maly6B.2 Hierarchical Statistical Characterization of Mixed-Signal Circuits Using Behavioral Modeling .........................................................................................374

E. Felt, S. Zanella, C. Guardiani, and A. Sangiovanni-Vincentelli6B.3 A Novel Dimension Reduction Technique for the Capacitance Extraction of 3D VLSI Interconnects ..........................................................................381

W. Hong, W. Sun, Z. Zhu, H. Ji, B. Song, and W. W-M. Dai

Session 6C: Topics in Power and Timing Analysis

Moderators: Thomas G. Szymanski, AT&T Bell Labs./Lucent Technologies, Murray Hill,NJ Marios Papaefthymiou, Yale University, New Haven, CT

6C.1 Inaccuracies in Power Estimation During Logic Synthesis.........................................388 D. Brand and C. Visweswariah

6C.2 Clock Skew Optimization for Ground Bounce Control ................................................395 A. Vittal, H. Ha, F. Brewer, and M. Marek-Sadowska

6C.3 A Power Modeling and Characterization Method for the CMOS Standard Cell Library..................................................................................................400

J-Y. Lin, W-Z. Shen, and J-Y. Jou

Session 6D: Verification and Fault ToleranceModerators: Kunle Olukotun, Stanford University, Stanford, CA Steve Tjiang, Synopsys, Inc., Mountain View, CA

6D.1 Heterogeneous Built-in Resiliency of Application Specific Programmable Processors............................................................................................406

K. Kim, R. Karri, and M. Potkonjak6D.2 Unit Delay Simulation with the Inversion Algorithm.................................................412

W.J. Schilp and P.M. Maurer6D.3 An Observability-Based Code Coverage Metric for Functional Simulation ................418

S. Devadas, A. Ghosh, and K. Keutzer

Session 7A: Extending the Scope of High-Level SynthesisModerators: Don MacMillen, Synopsys, Inc., Mountain View, CA Youn-Long Lin, Tsing Hua University, Taiwan

7A.1 Latch Optimization in Circuits Generated from High-Level Descriptions..................428 E.M. Sentovich, H. Toma, and G. Berry

7A.2 Synthesis Using Sequential Functional Modules (SFMs)............................................436 S. Chaudhuri and M. Quayle

7A.3 An Algorithm for Synthesis of System-Level Interface Circuits..................................442 K-S. Chung, R.K. Gupta, and C.L. Liu

Session 7B: Analog CAD and MethodologyModerators: Georges Gielen, Katholieke University, Heverlee, Belgium John Cohn, IBM Corp., Richmond, VT

7B.1 An Algorithm for Power Estimation in Switched-Capacitor Circuits ..........................450 C. Young, G. Casinovi, J. Fowler, and P. Kerstetter

7B.2 Semi-Analytical Techniques for Substrate Characterization in the Design of Mixed-Signal ICs ...................................................................................455

E. Charbon, R. Gharpurey, R.G. Meyer, and A. Sangiovanni-Vincentelli7B.3 A Video Driver System Designed Using a Top-Down, Constraint-Driven Methodology ..................................................................................463

I. Vassiliou, H. Chang, A. Demir, E. Charbon, P. Miliozzi, and A. Sangiovanni-Vincentelli

Session 7C: Partitioning and FloorplanModerators: Martin D.F. Wong, University of Texas, Austin, TX Frank M. Johannes, Technical University of Munich, Munich, Germany

7C.1 Hierarchical Partitioning .............................................................................................470 D. Behrens, K. Harbich, and E. Barke

7C.2 Hybrid Floorplanning Based on Partial Clustering and Module Restructuring .........478 T. Yamanouchi, K. Tamakashi, and T. Kambe

7C.3 Module Placement on BSG-Structure and IC Layout Applications.............................484 S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani

Session 7D: Delay Fault TestModerators: E.J. McCluskey, Stanford University, Stanford, CA Ray Mercer, Texas A&M University, College Station, TX

7D.1 Delay Fault Coverage: A Realistic Metric and an Estimation Technique for Distributed Path Delay Faults .............................................................494

M. Sivaraman and A.J. Strojwas7D.2 SIGMA: A Simulator for Segment Delay Faults..........................................................502

K. Heragu, J.H. Patel, and V.D. Agrawal7D.3 Zamlog: A Parallel Algorithm for Fault Simulation Based on Zambezi ......................509

M.B. Amin and B. Vinnakota

Session 8A: Embedded TutorialPresenter: Gordon W. Roberts, McGill University, Montreal, Quebec, Canada8A Metrics, Techniques and Recent Developments in Mixed-Signal Testing ..................514

G.W. Roberts

Session 8B: Embedded TutorialPresenters: Ken L. Shepard, IBM Corp., Yorktown Heights, NY Vinod Narayanan, IBM Corp., Yorktown Heights, NY

8B Noise in Deep Submicron Digital Design.....................................................................524 K.L. Shepard and V. Narayanan

Session 9A: Panel: Intranets and EDA: Impact, Application, and Technology .....534 Organizer: David Ku, Escalade, Santa Clara, CA Moderator: James Rowson, Cadence/Alta, Sunnyvale, CA Panel Members: Jean Brouwers, Sun Microsystems, Palo Alto, CA Giovanni De Micheli, Stanford University, Stanford, CA Jan Rabaey, University of California, Berkeley, CA

Session 10A: BDD Applications and TechniquesModerators: Albert Wang, Synopsys, Inc., Mountain View, CA Sujit Dey, C&C Research Labs., NEC USA, Inc., Princeton, NJ

10A.1 Digital Sensitivity: Predicting Signal Interaction Using Functional Analysis ...................................................................................................536

D.A. Kirkpatrick and A.L. Sangiovanni-Vincentelli10A.2 Efficient Solution of Systems of Boolean Equations...................................................542

S. Woods and G. Casinovi

10A.3 Partitioned ROBDDs - A Compact, Canonical and Efficiently Manipulable Representation for Boolean Functions ..................................................547

A. Narayan, J. Jain, M. Fujita, and A. Sangiovanni-Vincentelli

Session 10B: Advances in Transmission Line AnalysisModerators: Chandu Visweswariah, IBM Corp., Yorktown Heights, NY Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, PA

10B.1 Simulation and Sensitivity Analysis of Transmission Line Circuits by the Characteristics Method......................................................................556

J-F. Mao, J.M. Wang, and E.S. Kuh10B.2 A General Dispersive Multiconductor Transmission Line Model for Interconnect Simulation in SPICE........................................................................563

M. Celik and A.C. Cangellaris10B.3 Efficient Time-Domain Simulation of Frequency-Dependent Elements ...................569

S. Kapur, D.E. Long, and J. Roychowdhury

Session 10C: Power and Current ModelingModerators: Farid N. Najm, University of Illinois, Urbana, IL Jyuo-Min Shyu, Industrial Tech. Research Institute, Taiwan

10C.1 Stratified Random Sampling for Power Estimation...................................................576 C-S. Ding, C-T. Hsieh, Q. Wu, and M. Pedram

10C.2 Statistical Sampling and Regression Analysis for RT-Level Power Evaluation........................................................................................................583

C-T. Hsieh, Q. Wu, C-S. Ding, and M. Pedram10C.3 Expected Current Distributions for CMOS Circuits ..................................................589

D.J. Ciplickas and R.A. Rohrer

Session 10D: Mixed-Signal TestingModerators: Ranga Vemuri, University of Cincinnati, Cincinnati, OH Gordon Roberts, McGill University, Montreal, Quebec, Canada

10D.1 Metrology for Analog Module Testing Using Analog Testability Bus .......................594 C. Su, Y-T. Chen, S-J. Jou, and Y-T. Ting

10D.2 ABILBO: Analog BuILt-in Block Observer................................................................600 M. Lubaszewski, S. Mir, and L. Pulz

10D.3 Design of Robust Test Criteria in Analog Testing .....................................................604 W.M. Lindermeir

Session 11A: Logic SynthesisModerators: Narendra Shenoy, Synopsys, Inc., Mountain View, CA Carl Pixley, Motorola, Inc., Austin, TX

11A.1 Metamorphosis: State Assignment by Retiming and Re-Encoding ...........................614 B. Iyer and M. Ciesielski

11A.2 The Case for Retiming with Explicit Reset Circuitry ................................................618 V. Singhal, S. Malik, and R.K. Brayton

11A.3 Polarized Observability Don’t Cares ..........................................................................626 H. Arts, M. Berkelaar, and C.A.J. van Eijk

xiii

Session 11B: System Level Optimization and ValidationModerators: P.A. Subrahmanyam, AT&T Bell Labs., Holmdel, PA Masaharu Imai, Osaka University, Osaka, Japan

11B.1 Power Optimization in Disk-Based Real-Time Application Specific Systems.........................................................................................................634

I. Hong and M. Potkonjak11B.2 A Hierarchical Functional Structuring and Partitioning Approach for Multiple-FPGA Implementations..........................................................................638

W-J. Fang and A.C-H. Wu11B.3 Generation of BDDs from Hardware Algorithm Descriptions...................................644

S. Minato

Session 11C: Special Topics In Physical DesignModerators: Dwight Hill, Synopsys, Inc., Mountain View, CA Atushi Takahashi, Tokyo Institute of Technology, Tokyo, Japan

11C.1 Directional Bias and Non-Uniformity in FPGA Global Routing Architectures..............................................................................................................652

V. Betz and J. Rose11C.2 Width Minimization of Two-Dimensional CMOS Cells Using Integer Programming ................................................................................................660

A. Gupta and J.P. Hayes11C.3 Interchangeable Pin Routing with Application to Package Layout...........................668

M-F. Yu, J. Darnauer, and W.W-M. Dai

Session 11D: Fault DiagnosisModerators: Rabindra K. Roy, NEC Corp., Princeton, NJ Justin Harlow, Semiconductor Research Corp., NC

11D.1 A Coloring Approach to the Structural Diagnosis of Interconnects ..........................676 X.T. Chen and F. Lombardi

11D.2 Integrated Fault Diagnosis Targeting Reduced Simulation......................................681 V. Boppana and W.K. Fuchs

11D.3 An Efficient, Bus-Layout Based Method for Early Diagnosis of Bussed Driver Shorts in Printed Circuit Boards.......................................................685

K. Chakraborty and P. Mazumder

Session 12A: Embedded TutorialPresenters: W. Maly, H. Heineken, J. Khare, andP.K. Nag,

Carnegie Mellon University, Pittsburgh, PA12A Design for Manufacturability in Submicron Domain .................................................690

W. Maly, H. Heineken, J. Khare, and P.K. Nag

Session 12B: Embedded TutorialPresenter: L. P.P.P. van Ginneken, and N.V. Shenoy, Synopsys, Inc., CA

R.H.J.M. Otten, Delft University of Technology,The Netherlands

12B SPEED: New Paradigms in Design for Performance..................................................700 R.H.J.M. Otten, L.P.P.P. van Ginneken, and N.V. Shenoy

Author Index .......................................................................................................................703

FOREWORD

On behalf of the ICCAD-96 Executive and Technical Program Committees, I would like to welcome youto the 14th installment of the International Conference on Computer-Aided Design. We return again tothe San Jose Red Lion Hotel with its convenient, central location and cozy atmosphere. We have workedhard to hold down the cost of attending ICCAD-96 by maintaining a low nightly rate for hotel rooms.

The Technical Program for ICCAD-96 was put together under the direction of Ralph Otten. The TechnicalProgram Committee was organized as 13 subcommittees each with a focus in a specific technical area.Each subcommittee had several experts in the field evaluating about 25 technical papers. Thesubcommittee members represented a diverse range of opinions and included members from industry andacademia, and included significant international representation. Each volunteer on the committee devotedmany hours reviewing each paper and then attended the full-day committee meeting to present and defendtheir reviews and to assist in the difficult process of choosing a small subset of the papers for ICCAD-96.Overall, only 32% of the papers submitted to ICCAD-96 were accepted.

Within the technical track, we have included six 90-minute tutorials. Research experts in their respectivefields will introduce the basic concepts in technical areas which are at the forefront of CAD researchtoday: models of computation for specifying system behavior, noise issues in deep submicron designs,speed and delay optimizations in synthesis, accurate 3-D interconnect modeling, testing for mixed-signalICs, and DFM in the submicron domain.

We have also included two panels in the technical program, organized by Jacob White and David Ku. OnMonday night we explore the apparent renaissance of “in-house” corporate CAD in “Is Corporate CADBack?”. A cross section of CAD developers—corporate, vendor, and academic—will offer their differingopinions on why corporate CAD did not just “disappear” the way many pundits predicted. On Wednesdaymorning we visit the hot topic of network-centric CAD with a panel on “Intranets and EDA: Impact, Application,and Technology”. The panel looks at how evolving network technologies will affect the design of new CAD toolsand the delivery of next-generation CAD services.

Complementing the technical program is the 1996 Tutorial Program organized by Rob Aitken. The four full-daytutorials on Thursday, November 14, offer in-depth information on established areas of CAD where outstandingspeakers and educators outline their respective technical fields. This year the tutorial topics include: ICInterconnect Design Solutions, Circuit Tuning for High-Performance Custom Digital Design, Design and Test ofCore-Based Systems, and Verification of Electronic Systems. These tutorials have always been an important partof ICCAD and generate positive feedback from the tutorial attendees.

In an industry increasingly filled with million-gate chips, near-GHz clock rates, deep submicron geometries, andrapidly evolving design methodologies, ICCAD-96 offers a place for CAD developers and users to meet andexchange ideas about next-generation problems and solutions. We hope you find ICCAD-96 useful andenjoyable.

Rob A. Rutenbar Ralph H. J. M. OttenConference Chair Technical Program Chair

PROGRAM CHAIRRalph H.J.M. OttenDelft Univ. of TechnologyLab. for Circuits & Sys., Dept. EEMekelweg 4, 2628 CD DelftThe Netherlands(31) 15-2781600otten@et.tudelft.nl

PUBLICATIONS CHAIRHiroto YasuuraKyushu Univ.Dept. of Information Systems6-1, Kasuga KoenKasuga 816, Japan(81) 92-583-1339yasuura@is.kyushu-u.ac.jp

PAST CHAIRRichard RudellSynopsys, Inc.700 E. Middlefield Rd.Mountain View, CA 94043-4033 (415) 694-4337rudell@synopsys.com

PUBLICITY CHAIRMary BaileyRincon Research Corp.101 N. Wilmot, Ste. 310Tucson, AZ 85711(520) 745-0400mlb@rincon.com

TUTORIAL CHAIRRobert C. AitkenHewlett-Packard Co.Design Tech. Ctr., M/S-6UK1501 Page Mill Rd.Palo Alto, CA 94303-0889(415) 857-2146aitken@dtc.hp.com

PANEL CHAIRJacob WhiteMassachusetts Inst. of TechnologyDept. of EECS, Rm. 36-88050 Vassar St.Cambridge, MA 02139(617) 253-2543white@rle-vlsi.mit.edu

AV & LOCAL ARRANGEMENTSFINANCE CHAIRDavid KuEscalade Corp.1210 E. Arques Ave.Sunnyvale, CA 94086(408) 481-1317ku@escalade.com

ASIAN REPRESENTATIVEYoun-Long LinTsing Hua Univ.Dept. of CSHsin-Chu, Taiwan 30043 ROC(886) 35-731072ylin@cs.nthu.edu.tw

EUROPEANREPRESENTATIVEBernard CourtoisTIMA46 Ave. Felix VialletGrenoble Cedex 38031, France(33) 76-57-4615Bernard.Courtois@imag.fr

SIGDA REPRESENTATIVERobert A. WalkerKent State Univ.Dept. of Math and CSKent, OH 44242(216) 672-4004walker@mcs.kent.edu

IEEE CS/DATC REPRESENTATIVECharles W. RosenthalCWR-Engineering Consultants3080 SW Fairmont Blvd.Portland, OR 97201-1439(503) 245-8398charlier@cse.ogi.edu

CONFERENCE MANAGERKevin LepineMP Associates, Inc.5305 Spine Rd., Ste. ABoulder, CO 80301(303) 530-4562kevin@mpa-net.com

CONFERENCE COMMITTEECONFERENCE CHAIRRob A. RutenbarCarnegie Mellon Univ.Dept. of ECE5000 Forbes Ave.Pittsburgh, PA 15213(412) 268-3334rutenbar@ece.cmu.edu

Jacques BenkoskiEurEPICGieres, France

Michel BerkelaarEindhoven Univ. of Tech.Eindhoven, The Netherlands

Forrest BrewerUniv. of CaliforniaSanta Barbara, CA

Jay BrockmanUniv. of Notre DameNotre Dame, IN

Jerry BurchCadence Design Systems, Inc.Berkeley, CA

Philip C.H. ChanThe Hong Kong Univ. ofSci./Tech.Kowloon, Hong Kong

Chung Kuan ChengUniv. of CaliforniaSan Diego, CA

Jue-Hsien ChernTechnology Modeling Assoc., Inc.Palo Alto, CA

John CohnIBM Corp.Richmond, VT

Jason CongUniv. of CaliforniaLos Angeles, CA

Bernard ConqFrance Telecom CNET GrenobleMeylan, France

Sujit DeyC&C Res. Labs., NEC USA, Inc.Princeton, NJ

Nikil DuttUniv. of CaliforniaIrvine, CA

Bob FrancisXilinx, Inc.Toronto, Ontario, Canada

Tomoyuki FujitaNEC C&C Research Labs.Kawasaki, Japan

Georges GielenKatholieke Univ.Heverlee, Belgium

Michaela GuineyHewlett-PackardPalo Alto, CA

Rajesh K. GuptaUniv. of IllinoisUrbana, IL

Sandeep GuptaUniv. of Southern CaliforniaLos Angeles, CA

Dwight HillSynopsys, Inc.Mountain View, CA

Masaharu ImaiOsaka Univ.Osaka, Japan

Masaki ItoHitachi, Ltd.Tokyo, Japan

Rajeev JayaramanXilinx, Inc.San Jose, CA

Ahmed A. JerrayaTIMA/INPGGrenoble, France

Niraj K. JhaPrinceton Univ.Princeton, NJ

Frank M. JohannesTechnical Univ. of MunichMunich, Germany

Takashi KambeSHARP Co.Nara, Japan

Luciano LavagnoPolitecnico di TorinoTorino, Italy

David LewisUniv. of TorontoToronto, Ontario, Canada

Youn-Long LinTsing Hua Univ.Taiwan, ROC

David LingIBM Corp.Yorktown Heights, NY

Fadi MaamariLogicVisionSan Jose, CA

Don MacMillenSynopsys, Inc.Mountain View, CA

ICCAD-96 TECHNICAL PROGRAM COMMITTEE

Klaus Mueller-GlaserUniv. of KarlsruheKarlsruhe, Germany

Farid N. NajmUniv. of IllinoisUrbana, IL

Sani NassifIBM Corp.Austin, TX

Ryosuke OkudaMitsubishi Electric Corp.Hyogo, Japan

Kunle OlukotunStanford Univ.Stanford, CA

Marios PapaefthymiouYale Univ.New Haven, CT

Carl PixleyMotorolaAustin, TX

Irith PomeranzUniv. of IowaIowa City, IA

Dhiraj K. PradhanTexas A&M Univ.College Station, TX

Janusz RajskiMentor Graphics Corp.Wilsonville, OR

June-Kyung RhoLG Info. & Communication Ltd.Kyongki-Do, Korea

Charles W. RosenthalCWR-Engineering ConsultantsPortland, OR

Wolfgang RosenstielUniv. TuebingenTuebingen, Germany

Ellen M. SentovichEcole des Mines de ParisSophia-Antipolis, France

Takeshi ShimaToshiba Corp.Kawasaki, Japan

Jyuo-Min ShyuIndustrial Tech. Research Inst.Taiwan, ROC

Adit SinghAuburn Univ.Auburn, AL

Chau-Chin SuNational Central Univ.Taiwan, ROC

P.A. SubrahmanyamAT&T Bell Labs.Holmdel, NJ

Thomas G. SzymanskiAT&T Bell Labs./Lucent Tech.Murray Hill, NJ

Atushi TakahashiTokyo Inst. of TechnologyTokyo, Japan

Steve TjiangSynopsys, Inc.Mountain View, CA

Louise TrevillyanIBM Corp.Yorktown Heights, NY

Ren-Song TsayArcSys, Inc.Sunnyvale, CA

Jerzy TyszerMcGill Univ.Montreal, Quebec, Canada

Willem Van BokhovenEindhoven Univ. of Tech.Eindhoven, The Netherlands

Chandu VisweswariahIBM Corp.Yorktown Heights, NY

Albert WangSynopsys, Inc.Mountain View, CA

Jacob K. WhiteMassachusetts Inst. of Tech.Cambridge, MA

Martin D.F. WongUniv. of TexasAustin, TX

Hiroto YasuuraKyushu Univ.Fukuoka, Japan

Gary YeapMotorola, Inc.Tempe, AZ

Yervant ZorianAT&T Bell Labs./Lucent Tech.Princeton, NJ

ICCAD-96 TECHNICAL PROGRAM COMMITTEE

PANELIS CORPORATE CAD BACK?

Moderator: Jacob White - Massachusetts Institute of Technology, Cambridge, MA

Before the rapid growth of the CAD industry in the mid 1980’s, every integrated circuit manufacturermaintained a sizable corporate CAD group which developed tools like layout generators and editors,design rule checkers, simulators, synthesis tools and extractors. During the late 1980’s and early 1990’salmost all of these corporate CAD groups were reduced in size, in favor of purchasing tools from rapidlygrowing CAD companies. But now, these same manufacturers seem to be rebuilding their corporate CADgroups. Are these new groups reinventing wheels or providing customized capabilities which leverageexternally developed CAD tools? Is this regrowth a wise reaction to permanently unresponsive CADcompanies, or a temporary fix whose need will be eliminated by focussed tools from small companies andCAD service organizations? And what role will universities play? In this panel, corporate CAD and CADindustry leaders will present a variety of views of this rapidly evolving CAD environment.

Panel Members:

Michael Jackson- Motorola, Austin, TXResve Saleh- Simplex Solutions, San Jose, CAGadi Singer- Intel Corp., Santa Clara, CAJames Spoto- Cadence Design Systems, Inc., San Jose, CAPrasad Subrahmanyam- Bell Labs.-Lucent Tech., Holmdel, NJEllen Yoffa- IBM Corp., Yorktown Heights, NY

PANELINTRANETS AND EDA: IMPACT, APPLICATION, AND TECHNOLOGY

Organizer: David Ku- Escalade, Santa Clara, CAModerator: James Rowson- Cadence/Alta, Sunnyvale, CA

The emergence of intranets, using the standards and infrastructure of the Internet and the World WideWeb, is reshaping the way companies manage and share information and resources within theorganization. It has a huge impact on EDA users by enabling the effective sharing of design and toolresources that is fundamental to collaborative team design and fast time to market. This panel exploresthe technology behind intranets and its impact on how EDA tools are architected, built, and deployed inthe future. Following a short survey of the current and emerging technology for intranet-based client-server computing, a panel of technologists from EDA vendors, corporate CAD, and academia/researchwill discuss the impact, architecture, and technology behind EDA on intranets.

Panel Members:

Jean Brouwers- Sun Microsystems, Palo Alto, CAGiovanni De Micheli- Stanford Univ., Stanford, CAJan Rabaey- Univ. of California, Berkeley, CA

“This panel was co-organized byIEEE Design & Test of Computers Magazine”

TUTORIAL 1IC INTERCONNECT DESIGN SOLUTIONS

Speakers:

Aykut Dengi, Sematech Corporation, Austin, TX, is a Motorola assignee at Sematech. He is working oninterconnect modeling and signal integrity verification for digital IC’s.

Lawrence Pileggi, Carnegie Mellon University, Pittsburgh, PA, is associate professor of electrical andcomputer engineering at Carnegie Mellon University. He is best known for his work on moment-matchingtechniques (such as asymptotic waveform evaluation) for analyzing large interconnect circuit models.

John Cohn, IBM, Essex Junction, VT, is a senior engineer with IBM’s Electronic Design Automationgroup, where he is the lead architect for custom circuit tools. His work has included research inperformance driven layout for analog and digital VLSI.

Background: This tutorial is intended for CAD developers and integrated circuit designers at various skilllevels. A basic understanding of integrated circuits and circuit theory is assumed.

Description: Interconnect effects continue to have a dominant impact on the performance of integratedcircuits. This tutorial begins by describing the technology trends which brought about this dominance, alongwith predictions on where future technologies will take us. A broad spectrum of interconnect issues that mustbe dealt with during the design of integrated circuits will be covered, from front-end-design interconnectmetrics and models, to back-end verification and extraction capabilities.

Aykut Dengi will begin by describing the technology trends that have made the interconnect problem soprominent. In particular, he will discuss the impact of submicron VLSI scaling on the interconnectresistance and coupling capacitance. Then, recognizing the importance of accurate interconnect circuitmodels, he will give a breadth-first coverage of IC extraction algorithms, pointing out their inadequaciesfor future technologies. This will include a brief look at the role of on-chip inductance in the future.

Next, Larry Pileggi will describe how to generate and analyze interconnect circuit models from theextracted parameters. He will also describe the interconnect timing and signal integrity problems designerswill be faced with for deep submicron multi-layer metal designs. The latest advances in moment matching(AWE) and Pade’ approximations for RC(L) interconnect circuits will be described. Interfacing thesereduced circuit models to transistor-level simulators and gate-level timing analyzers will be covered indetail. In addition to analysis capabilities, the latest in front-end design metrics and models for ICinterconnect will be reviewed.

John Cohn will then describe how interconnect metrics can be used for a wide range of computer-aidedinterconnect and wiring design. He will cover signal nets, clock trees, and power grids, and describe howthe circuit parameters, models and metrics are used to cope with interconnect effects in a top-down designflow environment. He will also discuss some of the ongoing design automation work for such problems,and will conclude by describing aspects of interconnect design and analysis which are still open issues.

TUTORIAL 2CIRCUIT TUNING FOR

HIGH-PERFORMANCE CUSTOM DIGITAL DESIGN

Speakers:

Steven G. Duvall, Intel Corp., Santa Clara, CA, is a principal engineer at Intel and manages Intel’sstatistical design activity.

Chandu Visweswariah, IBM Corp., Yorktown Heights, NY, is a research staff member at IBM’s T.J.Watson Research Center. His research interests include circuit and timing simulation, device modelingand circuit optimization.

Sachin Sapatnekar, Iowa State University, Ames, IA, is an assistant professor in the ECE Dept. He haspublished widely in layout synthesis physical design, power, timing and simulation issues andoptimization algorithms.

Background: This tutorial is intended for IC designers and CAD developers interested in designoptimization techniques for high-performance circuits. Attendees should be familiar with the basics ofCMOS digital circuit design.

Description: Circuit tuning is an important step in high-performance digital circuit design, and istraditionally a manual, tedious and error-prone process. Recently, tools for automatic sizing of transistorsand interconnect have emerged in order to optimize any combination of path delay, rise/fall time, area,power or noise requirements. Further, tuning to guarantee robustness in the manufacturing step is crucialto enhancing the yield of these circuits. This tutorial will discuss various methods of automatic circuittuning, along with case studies of their application to real high-performance digital integrated circuits.

The tutorial begins with a brief introduction to optimization techniques, followed by a discussion of static-timing-based tuning methods. Several delay models will be discussed. TILOS and other sizingalgorithms, power optimization, wire optimization, simultaneous transistor/wire sizing and methods ofhandling dynamic logic will be addressed, including discussion of applications.

The second section of the tutorial will discuss dynamic-simulation-based tuning, which usually involvesSPICE-like simulation in the inner loop of the optimization. A quick literature survey will be followed bythe description of a practical circuit optimization tool. The circuits of a high-performance dynamic-logicmicroprocessor, which were tuned using this optimization program, will be presented as a case study.

Statistical tuning addresses the issue of manufacturing process variations by incorporating circuitvariability in the design process. The broad class of techniques developed for this purpose will besurveyed and discussed in the context of industrial experience with large microprocessor designs.

Throughout the tutorial, the impact of circuit tuning on design methodology will be discussed. Carefulspecification of design requirements and facilitation of design re-use are examples of impact on designmethodology.

TUTORIAL 3DESIGN AND TEST OF CORE-BASED SYSTEMS

Speakers:

Sujit Dey, C&C Research Laboratories, NEC USA, Princeton, NJ, has worked extensively in R&D ofCAD tools to support high level design and test methodologies for low-power and high-performancedesigns. He is currently involved in developing design aids for embedded systems.

Miodrag Potkonjak - Univ. of California, Los Angeles, is an assistant professor of computer science.His recent work emphasizes application and architectural-level synthesis, behavioral synthesis, codeoptimization, and debugging.

Yervant Zorian , Lucent Technologies, Bell Laboratories, Princeton, NJ, is a Distinguished Member ofTechnical Staff. He works in research and consulting in the areas of embedded core, IC, and MCM testmethods and Built-In Self-Test solutions.

Background: This tutorial is intended for designers, CAD tool developers, and researchers interested inthe specification, analysis, design, and test of heterogeneous embedded systems which use predesignedcores and off-the-shelf components.

Description: Increasing complexity, aggressive design requirements, and shorter product cycles requiretoday’s systems designers to make maximal use of predesigned cores and off-the-shelf components, andfocus more on system-level design exploration to aid product differentiation.

This tutorial addresses the design, validation, and test of embedded systems, with particular emphasis oncore-based systems, which allow reusability, customizability, and chip-level integration.

A wide range of available cores, from general-purpose processors and microcontrollers, to DSPs, PCI, anddigital video and communications, will be described. The need and design of co-processors and ASIPs willbe highlighted. Several system level design decisions will be addressed, such as the partitioning of theapplication tasks into software and custom hardware, and selecting the type and number of cores used. Thediscussion will include available methodologies and tools to aid in the system level exploration, includingsoftware and hardware timing and power estimation tools, and co-simulation tools.

For the parts of the application mapped to processor cores, compilation, code optimization, multi-tasking,and multi-processing will be addressed, plus examples of available software development and debuggingtools. Hardware synthesis of the user-defined logic (UDL), and integration of the cores with the UDL willbe addressed. The tutorial will also describe system validation methodologies, such as emulation,simulation using soft and hard models of the components, and co-simulation. Industrial examples will beused to illustrate the available cores and components, design methodologies and development tools, andapplications. Trends in core-based systems design and related ESDA tools will be discussed.

The tutorial will also cover the test related aspects of embedded systems with emphasis on testingembedded core-based designs, including requirements for testing, access, and standardization, as well asdebugging and diagnosing embedded units will be analyzed. The tutorial then will cover the state-of-the-art practices, such as BIST and scan for embedded cores and the porting of test data. Finally it will discussthe recent challenges and adopted strategies to implement an integrated test strategy from embedded coresto systems.

TUTORIAL 4VERIFICATION OF ELECTRONIC SYSTEMS

Speakers:

Jerry Burch - Cadence Berkeley Labs., Berkeley, CA

Rick McGeer - Cadence Berkeley Labs., Berkeley, CA

Ken McMillan - Cadence Berkeley Labs., Berkeley, CA

Alex Saldanha- Cadence Berkeley Labs., Berkeley, CA

Background: This tutorial describes how emerging verification technologies can be used in largedesigns. The focus of the tutorial will be on the strengths, weaknesses, and uses of each technology, asopposed to the mathematics and details of the technology. The presentation is intended for designers andfor design-side CAD professionals (those who design user-level environments for verificationtechnologies), and would likely not be of great interest to CAD technology developers.

Description: The organization and scope of the tutorial will be similar to the DAC ‘96 tutorial of thesame name. This tutorial presents a collection of design verification technologies that use cycle-basedmodels. These technologies are:

1) Highly optimized cycle-based simulation

2) Cycle-based timing analysis

3) Formal verification technologies (model checking combinational equivalence, etc.)

A cycle-based model defines the state of a circuit at the next clock event, as a function of the current stateand inputs. No information about intermediate signal transitions is computed. Cycle-based models havea number of advantages from the point of view of verification. First, in simulation there is no overheadof scheduling asynchronous events; operations may be efficiently scheduled in completely static manner.Second, a simulator needs only to compute the values of signals that are either latched or output from thesimulation. This allows very powerful optimization techniques to be used for simulation, much in themanner of circuit synthesis. This can result in order-of-magnitude speedups in simulation. It is also amajor advantage for formal verification techniques.

The tutorial will cover the construction of cycle-based models using the language SMV (roughlyequivalent to synthesizable Verilog), and the use of each verification technology to extract informationfrom the model. A small but representative design will be constructed using SMV, and each technologywill be employed to extract information about the design.

At the end of the day, participants should know:

1) How to construct a synthesizable, verifiable, cycle-accurate model of a design

2) How to use each of the presented technologies to extract information about the design

3) The strengths and weaknesses of each technology, and what each should be used for(and what it shouldn’t)

Miron Abramovici

Tobias Abthoff

Jay Adams

Saman Adham

Poonam Agrawal

Charles J. Alpert

Roger Ang

Kaoru Arakawa

Hideki Asai

Jacob Avidan

Adnan Aziz

Smita Bakshi

Clark Barrett

Roman Bazylevych

Peter Beeral

Luca Benini

Jacques Benkoski

Michel Berkelaar

Sudipta Bhawmik

Nguyen Ngoc Binh

Daniel Brand

Forrest Brewer

Oliver Bringmann

Jay Brockman

Tim Bucholz

Jerry Burch

Michael Burns

Rakesh Chadha

Tapan Chakraborty

Philip C.H. Chan

Chun-Yeh Chang

Chwen-Cher Chang

En-Shou Chang

Foong-Charn Chang

Ken Chang

Ming-Feng Chang

Shing-Chong Chang

Tsin-Yuan Chang

Yaowen Chang

Kevin Chao

Trinanjan Chatterjee

Benjamin Chen

Chih-Tung Chen

Chung-Ping Chen

D.S. Chen

De-Sheng Chen

H. Steven Chen

Jwu E. Chen

Pinhong Chen

Song Chen

Yung-Yuan Chen

Chung Kuan Cheng

David Cheng

Wei-Kai Cheng

Jue-Hsien Chern

Charles Chiang

Chen-Huan Chiang

Hyunwoo Cho

Ki-Seok Chung

John Cohn

Jason Cong

Bernard Conq

Jordi Cortadella

Andrew Crews

Paul Crocker

Zdzislaw Czarnul

Wayne Dai

Robert Damiano

Ali Dasdan

Hiroshi Date

An-Chang Deng

Sujit Dey

David Dill

Rainer Doemer

Richard Duerden

Christian Dufaza

Nikil Dutt

Masato Edahiro

Heinz-Josef Eikerling

Hans Eisenmann

Wolfgang Eisenmann

Aiman El-Maleh

Abe M. Elfadel

Nong Fan

Paul Fang

Jack Fishburn

Bob Francis

Elof Frank

Robert French

Takashi Fujii

Ryuichi Fujimoto

Tetsuya Fujimoto

Hisanori Fujisawa

Tomoyuki Fujita

Kunihiro Fujiyoshi

Dinesh Gaitonde

Reiner Genevriere

Joachim Gerlach

Georges Gielen

Eugene Goldberg

Eric H. Grosse

Peter Grun

Michaela Guiney

Rajesh K. Gupta

Sandeep Gupta

Kiyoharu Hamaguchi

Ikuo Harada

Wolfram Hardt

Lei He

Rachid Helaihel

Teruo Higashino

Dwight Hill

Richard Ho

Mitsuhiko Hokazono

Ulrich Holtman

Merit Hong

Hiromichi Honma

Shiang-Tang Huang

Xiaoli Huang

Jim Hwang

ICCAD-96 REVIEWERS

Seung-Ho Hwang

Ting-Ting Hwang

Masaharu Imai

Takahiro Inoue

Tetsuro Itakura

Masaki Ito

Tomonori Izumi

Rajeev Jayaraman

Ahmed A. Jerraya

Niraj K. Jha

Frank M. Johannes

Wen-Ben Jone

Jing-Yang Jou

Erica Hsiao-Ping Juan

Henry Jyu

Yoji Kajitani

A. Kalavade

Takashi Kambe

Mineo Kaneko

Joanna Kang

De-Yu Kao

Mark Kassab

Hideyuki Kawakita

Masayuki Kawamata

Jan Kellar

Andrew B. Khang

Hisakazu Kikuchi

Shinji Kimura

Tomohisa Kimura

Tsutomu Kimura

Michael Kishinevsky

Cheng-Kok Koh

Tetsushi Koide

David Kolson

Alex Kondratyev

Venkat Krishnaswamy

Florian Krohm

Shun-ichi Kubo

Prabhakar Kudva

Andreas Kuehlmann

Toshio Kumamoto

David Kung

Min Ter Kuo

Fadi Kurdahi

Tadahiro Kuroda

Luciano Lavagno

Chung-Len Lee

Kuen-Jong Lee

Jeremy Levitt

David Lewis

Jian Li

Ying-Meng Li

Wen-Toh Liao

John Lillis

Sung Lim

JC Lin

Youn-Long Lin

David Ling

Chun-Yeh Liu

Fan-Jou Liu

Huiqun Liu

Tony Ma

Fadi Maamari

Don MacMillen

Jean-Christophe Madre

Wai-Kei Mak

Margaret Marek-Sadowska

Robert L. Maziasz

Patrick McGuinness

Ron Miller

Sujoy Mitra

Takashi Mitsuhashi

Hiroshi Miyashita

Sundararajarao Mohan

Charles Monahan

Jose Monteiro

Cho Moon

Seijiro Moriyama

P. Morton

Klaus D. Mueller-Glaser

Nilanjan Murkherjee

Fidel Muradali

Hiroshi Murata

Sudip Nag

Tohru Nagamatsu

Akira Nagao

Farid N. Najm

Yoichiro Nakakuki

Shigetoshi Nakatake

Sani Nassif

Mahadevamurty Nemani

C. Nicol

Tetsuo Nishi

Kazuhisa Okada

Ryosuke Okuda

Makiko Okumura

Kunle Olukotun

Hidetoshi Onodera

Wenwei Pan

Preeti Panda

Rajendran Panda

Marios Papaefthymiou

Chaeryung Park

Jaehong Park

Ishwar Parulkar

Carl Pixley

Irith Pomeranz

Dhiraj K. Pradhan

Ruchir Puri

Stefano Quer

Ivan Radivojevic

Janusz Rajski

Srilata Raman

June-Kyung Rho

Bernhard Riess

Gordon Roberts

Charles W. Rosenthal

Jeroen Rutten

Toshiyuki Sadakane

Iwata Sakagami

ICCAD-96 REVIEWERS

Takayasu Sakurai

Harish Sarin

Ramesh Sathianathan

Jun Sato

Serap S. Savari

Endric Schubert

Andrew Seawright

Russ Segal

Arunabha Sen

Ellen M. Sentovich

Lu Sha

A. Sharma

Wen Zen Shen

Narendra Shenoy

AnJui Shey

Toshiyuki Shibuya

Takeshi Shima

Takashi Shimamoto

Arani Shina

Akichika Shiomi

Hiroshi Shirota

Masakazu Shoji

Jyuo-Min Shyu

Jui-Ching Shyur

Adit Singh

Kanwar Jit Singh

Vigyan Singhal

Gunter Stenz

Paul Stephan

Uli Stern

Leon Stok

Noel Strader

Chau-Chin Su

P. A. Subrahmanyam

Wern-Jieh Sun

Gitanjali Swamy

Thomas G. Szymanski

Shigetaka Takagi

Atushi Takahashi

Kazuhiro Takahashi

Toshihiko Takahashi

Yasuhiro Takashima

Yuichiro Takei

Yoshinori Takeuchi

Kazuo Tamakashi

Nagesh Tamarapalli

Mamoru Tanaka

Hiroshi Tanimoto

Masaya Tanno

Alexander Taubin

Juergen Teich

Masayuki Terai

Pieter Throbost

Steve Tjiang

Tony Todesco

Horia Toma

Tsuneo Tomita

Christoph Trautwein

Louise Trevillyan

Pieter Trouborst

Chris Tsai

Ren-Song Tsay

Ping-Sheng Tseng

Jerzy Tyszer

Akio Ushida

Koorosh Vakhshoori

Willem Van Bokhoven

Koen van Eijk

Peter Vanbekbergen

Benoit Veillete

Tiziano Villa

Chandu Visweswariah

Shin'ichi Wakabayashi

Albert Wang

Sying-Jyan Wang

Yifeng Wang

Kenji Watanabe

Takahiro Watanabe

Kenji Watanabe

Yosinori Watanabi

Christoph Weiler

Jen-Pin Weng

Jacob K. White

J. Williams

Martin D.F. Wong

Chen-Wen Wu

Tsung-Yi Wu

Yu-Liang Wu

Bernd Wurth

Hongyu Xie

Dongmin Xu

Jin Xu

Min Xu

Alexander Yakovlev

Akihiko Yamada

Masaaki Yamada

Takafumi Yamaji

Kiyotaka Yamamura

Takayuki Yamanouchi

Akira Yasuda

Hiroto Yasuura

Gary Yeap

C.S. Ying

Goichi Yokomizo

Chiyoshi Yoshioa

Michio Yotsuyanagi

Tak Young

Akira Yukawa

Peter Zepter

Hai Zhou

Jianwen Zhu

Qing Zhu

Victor Zia

Yervant Zorian

ICCAD-96 REVIEWERS

SESSION INDEX

Session 1A : TECHNOLOGY MAPPING Session 1B : INTERCONNECT CHARACTERIZATION AND ANALYSIS Session 1C : HIGH PERFORMANCE ROUTING SYNTHESIS Session 1D : SEQUENTIAL CIRCUIT TESTING Session 2A : FORMAL VERIFICATION I Session 2B : SYSTEM DESIGN: SYNTHESIS AND COMPILATION Session 2C : TIMING ANALYSIS Session 2D : SUPPORT FOR HIGH LEVEL DESIGN Session 3A : POWER AND PERFORMANCE IN HIGH LEVEL SYNTHESIS Session 3B : HIGH−PERFORMANCE CIRCUIT OPTIMIZATION Session 3C : CIRCUIT PARTITIONING Session 3D : ATPG Session 4A : EMBEDDED TUTORIAL: COMPARING MODELS OF COMPUTATION Session 4B : EMBEDDED TUTORIAL: ACCURATE INTERCONNECT MODELING : TOWARDSMULTI−MILLION TRANSISTOR CHIPS AS MICROWAVE CIRCUITS Session 5A : IMPLICATION−BASED LOGIC SYNTHESIS Session 5B : ADVANCED NUMERICAL SIMULATION TECHNIQUES Session 5C : ROBUST ROUTING Session 5D : BIST AND DFT Session 6A : FORMAL VERIFICATION II Session 6B : YIELD AND TECHNOLOGY MODELLING Session 6C : TOPICS IN POWER & TIMING ANALYSIS Session 6D : VERIFICATION AND FAULT TOLERANCE Session 7A : EXTENDING THE SCOPE OF HIGH LEVEL SYNTHESIS Session 7B : ANALOG CAD AND METHODOLOGY Session 7C : PARTITIONING AND FLOORPLAN Session 7D : DELAY FAULT TEST Session 8A : METRIES, TECHNIQUES AND RECENT DEVELOPMENTS IN MIXED−SIGNAL TESTING Session 8B : EMBEDDED TUTORIAL: NOISE IN DEEP SUBMICRON DIGITAL DESIGN Session 9A : PANEL: INTRANETS AND EDA: IMPACT, APPLICATION, AND TECHNOLOGY Session 10A : BDD APPLICATIONS AND TECHNIQUES Session 10B : ADVANCES IN TRANSMISSION LINE ANALYSIS Session 10C : POWER & CURRENT MODELING Session 10D : MIXED−SIGNAL TESTING Session 11A : LOGIC SYNTHESIS Session 11B : SYSTEM LEVEL OPTIMIZATION AND VALIDATION Session 11C : SPECIAL TOPICS IN PHYSICAL DESIGN Session 11D : FAULT DIAGNOSIS Session 12A : DESIGN FOR MANUFACTURABILITY IN SUBMICRON DOMAIN Session 12B : DRIVING ON THE LEFT HAND SIDE OF THE PERFORMANCE SPEED−WAY

709

Author Index

Achar, R. ..................................................20Agrawal, A. ............................................212Agrawal, V.D..........................................502Amin, M.B..............................................509Arts, H....................................................626Ashar, P. ................................................346Barke, E. ................................................470Behrens, D. ............................................470Berkelaar, M. .........................................626Berry, G. ................................................428Betz, V....................................................652Bjorksten, A. ..............................................2Boppana, V....................................... 63, 681Brand, D.................................................388Brayton, R.K. .........................................618Brewer, F. ..............................................395Brockman, J.B. ......................................142Bryant, R.E. ...........................................361Cabodi, G................................................354Camurati, P............................................354Cangellaris, A.C.....................................563Cao, W......................................................56Casinovi, G..................................... 450, 542Celik, M..................................................563Chaiyakul, V. .........................................154Chakraborty, K. .....................................685Chan, P.K...............................................201Chang, H................................................463Chang, S-C. ............................................262Chappell, B.A. ........................................119Charbon, E. ............................ 187, 455, 463Chatterjee, M. ..........................................88Chaudhuri, S..........................................436Chen, C-P.................................................38Chen, X.T. ..............................................676Chen, Y-A...............................................361Chen, Y-T...............................................594Cheng, K-T.............................................228Choi, K. ....................................................98Chung, K-S. ...........................................442Ciesielski, M...........................................614Ciplickas, D.J. ........................................589

Cong, J. ............................................ 44, 181Conn, A.R............................................... 174Corey, S.D................................................ 24Coulman, P.K. ....................................... 174Dai, W.W-M. ...........................316, 381, 668Darnauer, J. .......................................... 668Demir, A. ............................................... 463Deng, W. ................................................ 194Devadas, S. ............................................ 418Dey, S..................................................... 158Ding, C-S. ...................................... 576, 583Dutt, S. .................................................. 194Elfadel, I. ............................................... 288Fang, W-J. ............................................. 638Feldmann, P. ................................. 280, 295Felt, E. ................................................... 374Fleischer, B.M. ...................................... 119Fowler, J. ............................................... 450Freund, R.W. ......................................... 280Fuchs, W.K. ..................................... 63, 681Fujita, M. ............................................... 547Fujiyoshi, K. .......................................... 484Gajski, D.D. ........................................... 154Gharpurey, R. ........................................ 455Ghosh, A. ............................................... 418Ghosh, I. ................................................ 329Guardiani, C. ......................................... 374Gupta, A......................................... 346, 660Gupta, R.K............................................. 442Ha, H. .................................................... 395Hachtel, G................................................ 76Harbich, K. ............................................ 470Haring, R.A............................................ 174Hartanto, I. .............................................. 63Hayes, J.P...................................... 114, 660He, L. ..................................................... 181Heineken, H.T. .............................. 368, 690Heragu, K. ............................................. 502Hirose, F. ................................................. 82Ho, R.C................................................... 146Hong, I. .................................................. 634Hong, W. ................................................ 381

710

Horowitz, M.A........................................146Hsieh, C-T. ..................................... 576, 583Hsu, F.F. ................................................322Huang, J-D...............................................13Iwashita, H. .............................................82Iyer, B. ...................................................614Jain, J. ...................................................547Jang, J-Y. .................................................76Jha, N.K......................................... 158, 329Ji, H........................................................381Johnson, E.W. ........................................142Jou, J-Y. ........................................... 13, 400Jou, S-J. .................................................594Juan, H-P...............................................154Kahng, A.B...............................................30Kajitani, Y..............................................484Kambe, T................................................478Kamon, M. .............................................288Kapur, S. ................................................569Karri, R. .................................................406Kerstetter, P. .........................................450Keutzer, K..............................................418Khare, J. ................................................690Kiefer, G.................................................337Kim, K....................................................406Kirkpatrick, D.A. ...................................536Kondo, H. ...............................................228Kuh, E.S......................................... 302, 556Lavagno, L. ............................................212Lee, E.A..................................................234Lee, W. .....................................................76Lehmann, G. ..........................................134Lehther, D................................................50Leupers, R..............................................109Lin, J-Y. .................................................400Lindermeir, W.M. ..................................604Liu, C.L. .................................................442Lombardi, F. ..........................................676Long, D.E. ..............................................569Lubaszewski, M. ....................................600Mak, W-K...............................................205Malavasi, E. ...........................................187Malik, S.......................................... 346, 618Maly, W.......................................... 368, 690Mao, J-F. ................................................556

Marek-Sadowska, M...................... 262, 395Marques Silva, J.P................................. 220Marwedel, P........................................... 109Masuko, K................................................ 30Maurer, P.M. ......................................... 412Mazumder, P. ........................................ 685Mehra, R. ............................................... 166Meyer, R.G............................................. 455Miliozzi, P. ..................................... 187, 463Minato, S. .............................................. 644Mir, S. .................................................... 600Morrill, G.L............................................ 174Muddu, S. ................................................ 30Mudge, T................................................ 127Müller-Glaser, K.D................................ 134Murata, H. ............................................. 484Nag, P.K. ............................................... 690Nagoya, A. ............................................. 254Nakata, T................................................. 82Nakatake, S. .......................................... 484Nakhla, M................................................ 20Narayan, A. ........................................... 547Narayanan, V. ............................... 119, 524Okamoto, T. ............................................. 44Otten, R.H.J.M. ..................................... 700Papachristou, C.A.................................. 103Pardo, A. .................................................. 76Patel, J.H. .................................67, 322, 502Paul, D. .................................................... 88Pedram, M. .................................... 576, 583Potkonjak, M. ................................ 406, 634Pradhan, D.K..................................... 56, 88Pulz, L.................................................... 600Puri, R........................................................ 2Quayle, M. ............................................. 436Quer, S................................................... 354Rabaey, J. .............................................. 166Raghunathan, A. ........................... 158, 329Roberts, G.W.......................................... 514Rohrer, R.A............................................ 589Rose, J.................................................... 652Rosser, T.E................................................. 2Roychowdhury, J. .......................... 295, 569Rudnick, E.M................................... 67, 322Sakallah, K.A..........................114, 127, 220

711

Saldanha, A............................................212Saluja, K.K.................................................9Sangiovanni-Vincentelli, A.L........ 187, 212,Sangiovanni-Vincentelli, A. ... 234, 374, 455Sangiovanni-Vincentelli, A. ... 463, 547, 536Sapatnekar, S.S. ......................................50Sawada, H..............................................254Schilp, W.J. ............................................412Schlag, M.D.F. .......................................201Sentovich, E.M.......................................428Shen, W-Z. ....................................... 13, 400Shenoy, N.V. ..........................................700Shepard, K.L..........................................524Shin, Y. ....................................................98Silveira, L.M. .........................................288Singhal, V. .............................................618Sivaraman, M. .......................................494Smedes, T...............................................244Somenzi, F. ..............................................76Song, B. ..................................................381Strojwas, A.J. .........................................494Su, C.......................................................594Sun, W....................................................381Tamakashi, K.........................................478Ting, Y-T. ...............................................594Toma, H. ................................................428Van Campenhout, D. .............................127van der Meijs, N.P. ................................244van Eijk, C.A.J. ......................................626van Ginneken, L.P.P.P. ................. 262, 700Vassiliou, I. ............................................463

Vigeland, R. ........................................... 142Vinnakota, B.......................................... 509Visweswariah, C. ........................... 174, 388Vittal, A. ................................................ 395Vrudhula, S.B.K. ................................... 270Wang, D. ................................................ 302Wang, J.M.............................................. 556Wang, Q. ................................................ 270White, J.................................................. 288Wong, D.F. ................................38, 205, 310Woods, S................................................. 542Wu, A.C-H.............................................. 638Wu, Q............................................. 576, 583Wunder, B.............................................. 134Wunderlich, H-J. ................................... 337Xi, J.G. ................................................... 316Xiaoqing, W. .............................................. 9Xue, T. ................................................... 302Yalcin, H. ............................................... 114Yamanouchi, T....................................... 478Yamashita, S.......................................... 254Yang, A.T................................................. 24Young, C. ............................................... 450Yu, M-F.................................................. 668Zanella, S. .............................................. 374Zhang, Q-J. .............................................. 20Zhao, W.................................................. 103Zheng, G. ................................................. 20Zhou, H. ........................................... 38, 310Zhu, Z..................................................... 381Zien, J.Y................................................. 201

CONFERENCE CHAIR PROGRAM CHAIR PAST CHAIR TUTORIAL CHAIR PANEL CHAIRRalph H. J. M. Otten Hiroto Yasuura Rob A. Rutenbar Robert Aitken Jacob WhiteDelft Univ. of Technology Kyushu Univ. Carnegie Mellon Univ. Hewlett-Packard Co. Massachusetts Institute

1) SYNTHESIS

1.1 Combinational logic optimization (area, timing, power). FPGA optimization. Don’t care

methods. Technology mapping.

1.2 Sequential synthesis and optimization (e.g., state encoding, retiming) for area, timing,

and power. Asynchronous circuit design.

1.3 High level synthesis (scheduling, allocation, and binding). Datapath, control and

memory system synthesis and optimization. Estimation, use of libraries, synthesis

environments.

1.4 Analog circuit synthesis, optimization, and layout.

2) SIMULATION, VERIFICATION AND TESTING

2.1 Device modeling. Physical interconnect parameter extraction. TCAD, process and

device simulation.

2.2 Modeling and analysis techniques for timing and power at various levels of abstraction.

2.3 Circuit, interconnect and timing simulation. Circuit-level delay, timing and power

models. False path analysis. Transparent latch timing analysis and clock schedule optimization.

2.4 Switch, logic and high-level modeling and simulation. Functional Design Verification.

Formal verification techniques. High-level Design Validation.

2.5 New test strategies for digital circuits and analog circuits. Fault simulation.

2.6 Testability for digital circuits and analog circuits. BIST & DFT schemes. Partial and

boundary scan.

3) PLANNING, PLACEMENT AND ROUTING

3.1 Design planning. Synthesis for deep submicron technology. Interaction between logic

synthesis and layout.

3.2 Partitioning, placement and floorplanning techniques. Area estimation. Module

generation and leaf cell synthesis.

3.3 Routing for ICs and packages. Performance-driven placement and routing.

3.4 Complete layout systems (e.g., full chip, MCM). Symbolic design and compaction.

DRC, ERC, and layout verification.

4) SYSTEM DESIGN AND PRODUCT ENGINEERING

4.1 Specification, modeling and design of embedded systems. Hardware/software co-

design. Software synthesis, analysis and verification. Hardware/software co-testing and co-

validation.

4.2 Interface synthesis. System integration and testability. Performance evaluation.

Issues for real-time systems and DSP. ASIP synthesis.

4.3 Design metrics, concurrent engineering, requirements management, robust

engineering, design for manufacturing, iterative methodologies, planning and management, and

re-use. Frameworks and CAD on internet. Middleware: intertool communication, databases,

and data management. Hardware design languages and user interface.

4.4 Computer aided design for microsystems.

Authors should submit:

• 1 cover page including:

-Title of paper.-The category 1-4 and subcategory (e.g. 3.2) with keyword(s) in the

above list, which most closely matches the paper contents.-Complete name, return address, telephone number, fax number,

email address and affiliation of each author.-Clear identification of the corresponding author.-Papers will be reviewed anonymously. ONLY the cover page should

identify the authors and their affiliations.

• 8 copies of one page abstract

-Abstract, typed on separate page should state clearly and preciselywhat is new and point out the significant results. The IMPACT, or potentialimpact, of the contribution will play a major role in the evaluation.

• 8 copies of the completed paper

-Not to exceed 20 pages, double-spaced, figures, tables andreferences included.

O R• 8 copies of the 4-8 page proceedings format

-(double columned, 9pt or 10pt fonts) including figures, tables andreferences. (In the proceedings, four pages are free of charge and the maximumnumber of pages is 8).

• Papers exceeding these restrictions will be returned to the

authors.

- Previously published papers will not be considered;

this includes Workshop Proceedings.

- For further information email: icpubpap@dac.com

-Authors should clearly address the significance of their contribution as part of the

paper.

-Proposals for Panel Sessions and Tutorials are also invited.

AUTHOR’S SCHEDULE

Deadline for submissions: April 11, 1997 (Postmarked)

Notification of acceptance: July 7, 1997

Deadline for final version: August 8, 1997

Papers postmarked after April 11, will not be considered.

This deadline is firm and inflexible. No exceptions will be

made. Please plan accordingly!

Please direct all correspondence to:

ICCAD-97 Publications Department

MP Associates, Inc.5305 Spine Rd., Suite ABoulder, CO 80301Telephone: (303) 530-4562

ICCAD’S Home Page: http://www.iccad.com/

AREAS OF INTERESTOriginal technical papers on (but not limited to) the following topics are invited:

NOVEMBER 9-13, 1997

SAN JOSE, CA

CALL FOR PAPERSsponsored by: IEEE CIRCUITS AND SYSTEMS SOCIETY

THE IEEE COMPUTER SOCIETY DATC®

ASSOCIATION FOR COMPUTING MACHINERY/SIGDA

The 1997 INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN will be held November 9-

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THE INSTITUTE OF ELECTRICAL ANDELECTRONICS ENGINEERS, INC.

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Technical Committee on Design Automation®