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SIGDA Publications on CD-ROM:
ICCAD97IEEE/ACM International Conference on
Computer Aided Design
DoubleTree HotelSan Jose, CA
November 9-13, 1997
ICCAD ‘97 Proceedings © 1997 by IEEE. Al l rights reserved. No part of this book may be reproduced in any form, normay it be stored in a retrieval system or transmitted in any form without written permission of IEEE.
CDROM produced by ACM SIGDA CD-ROM Project.
ACM Order # 477976 ACM ISBN 0-89791-993-9
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ICCAD97:
Cover Page Front Matter Table of Contents Session Index Author Index
IEEE Circuits and Systems Society
IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN
A CONFERENCE FOR THE EE CAD PROFESSIONAL
I C C A D 97
NOVEMBER 9-13, 1997
DOUBLETREE HOTEL
SAN JOSE, CALIFORNIA
IEEE/ACM DIGEST OFTECHNICAL PAPERS
THE INSTITUTE OF ELECTRICALAND ELECTRONICS ENGINEERS, INC.ELECTRON DEVICES SOCIETY
ASSOCIATION FOR COMPUTING MACHINERYSpecial Interest Group on Design Automation
In cooperation with:
Sponsored by:
special interest group on
des ign au tomat ion
®
IEEE Computer Society
IEEE
1997IEEE/ACM International Conference
on Computer-Aided Design
November 9 – 13, 1997 San Jose, California
Digest of Technical Papers
Los Alamitos, CaliforniaWashington ● Brussels ● Tokyo
Copyright © 1997 by The Institute of Electrical and Electronics Engineers, Inc.All rights reserved
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The papers in this book comprise the proceedings of the meeting mentioned on the cover and title page.They reflect the authors’ opinions and, in the interests of timely dissemination, are published as presentedand without change. Their inclusion in this publication does not necessarily constitute endorsement by theeditors, the IEEE Computer Society, or the Institute of Electrical and Electronics Engineers, Inc.
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FOREWORD
On behalf of the organizing committees I would like to welcome you to the International Conference onComputer-Aided Design, being held once more in San Jose, in the same location as in recent years, but nowunder the name of the DoubleTree Hotel. This location, just off Highway 101, and with two internationalairports at less than half an hour’s distance, is easily reachable, and the accomodations for the technicalpresentations, panels and tutorials are conveniently together in the north wing so that you may easilycompose your personal daily program. Costs for attendance and hotels have been held down to the minimum.
The core of the conference is, of course, the technical program. A program committee of over sixty expertsfrom industry and academia around the world was organized under the direction of Hiroto Yasuura. To dofull justice to each submitted paper, the subcommittees were put together on the basis of the topicdistribution of incoming manuscripts. After evaluating the papers individually, the committee memberswere confronted with the opinions of the other subcommittee members, enabling the preparation of athorough review when all committee members met for a full day to establish the final selection and sessiondivision. In all, less than thirty percent of the submitted papers were accepted for inclusion in the final,high quality program.
At last year’s ICCAD, the embedded tutorials were extremely well received and attended. Hence, theExecutive Committee members again directed their efforts to carefully select a pair of ninety-minutepresentations for the end of each conference day. The purpose of these tutorials is to make the communityof tool developers aware of what is going on in the CAD world and what is urgently needed by today’sdesigners. Two of the tutorials will be devoted to areas that will keep gaining importance in this centuryand are still lacking adequate CAD support: simulation of circuits working at radio frequencies andmicroelectromechanical systems. Richard Newton will help you identify the challenges in research anddevelopment of distributed design systems, a new approach to collaboration in designing complexelectronic systems. Parallel to these, three areas, already recognized as of eminent importance for today’sdesign of high performance circuits, get their present forefront outlined: verification, interconnect design,and tuning for performance.
Ellen Sentovich has invited John Ousterhout to offer ICCAD attendees a special treat: a plenary Mondayevening event where its pioneer presents the status in scripting as a programming style quite different fromwhat is predominantly used in CAD today and shares his views on what to expect in the next century.
Of course, ICCAD-97 will close with a day of tutorials once more organized by Rob Aitken, in whichcomplete introductions to state-of-the-art CAD topics will be given by today’s expert developers andeducators. One tutorial targets timing analysis and optimization, which are already an integral part of thedesign process, but which become increasingly critical with the coming of deep-submicron. Given rapidadvances in our ability to integrate components on one chip, we offer a second tutorial that concentrateson design at higher levels of abstraction, and a third tutorial that focuses on complete systems on a chip.The final tutorial overviews custom in-house wireless design systems, complete with the available toolsand techniques for their hardware and software.
From the above you can see that we really are making efforts to make ICCAD the place where designerscan get an update with the latest results in design automation, developers can learn what designers needmost these days, and where the two groups can meet to exchange ideas, questions and answers. Thankyou for joining us at ICCAD-97.
Ralph H. J. M. Otten Hiroto YasuuraConference Chair Technical Program Chair
Table of Contents
Foreword ............................................................................................................................... xvConference Committee ...................................................................................................... xviTechnical Program Committee ....................................................................................... xviiReviewers ............................................................................................................................. xixTutorial 1: Timing Analysis and Optimization: From Devices to Systems............. xxiiTutorial 2: Design Technology for Building Wireless Systems................................ xxiiiTutorial 3: Modeling and Synthesis of Behavior, Control and Dataflow .............. xxivTutorial 4: Critical Technologies and Methodologies for Systems-On-Chips........ xxvKeynote Address ............................................................................................................... xxvi
Session 1A: Decision Diagram ApplicationsModerators: Shin-ichi Minato, Stanford University, Stanford, CA Jawahar Jain, Fujitsu Labs. of America, Inc., Santa Clara, CA1A.1: PHDD: An Efficient Graph Representation for Floating PointCircuit Verification.................................................................................................................... 2
Y.-A. Chen and R.E. Bryant1A.2: Functional Simulation Using Binary Decision Diagrams............................................... 8
C. Scholl, R. Drechsler, and B. Becker1A.3: Generalized Matching from Theory to Application ....................................................... 13
P. Vuillod, L. Benini, and G. De Micheli
Session 1B: Optimization and Synthesis for Reactive SystemsModerators: Rolf Ernst, Technical University Braunschweig, Braunschweig, Germany Charles Rosenthal, CWR-Engineering Consultants, Portland, OR1B.1: Decomposition of Timed Decision Tables and Its Use inPresynthesis Optimizations .................................................................................................... 22
J. Li and R.K. Gupta1B.2: A Predictive System Shutdown Method for Energy Saving of Event-Driven Computation................................................................................................................ 28
C.-H. Hwang and A.C.-H. Wu1B.3: Micro-Preemption Synthesis: An Enabling Mechanism for Multi-Task VLSI Systems ................................................................................................................. 33
K. Kim, R. Karri, and M.M. Potkonjak
Session 1C: Estimation of Power BoundsModerators: Farid N. Najm, University of Illinois, Urbana, IL Wen-Zen Shen, National Chiao Tung University, Hsinchu, Taiwan1C.1: Power Sensitivity — A New Method to Estimate Power Dissipation ConsideringUncertain Specifications of Primary Inputs ........................................................................... 40
Z. Chen, K. Roy, and T.-L. Chou
1C.2: Effects of Delay Models on Peak Power Estimation of VLSISequential Circuits.................................................................................................................. 45
M.S. Hsiao, E.M. Rudnick, and J.H. Patel1C.3: COSMOS: A Continuous Optimization Approach for Maximum PowerEstimation of CMOS Circuits.................................................................................................. 52
C.-Y. Wang and K. Roy
Session 1D: Block Krylov Methods for Interconnect ModelingModerators: Peter Feldmann, Bell Labs., Lucent Technologies, Murray Hill, NJ Jacob K. White, Massachusetts Institute of Technology, Cambridge, MA1D.1: PRIMA: Passive Reduced-Order Interconnect MacromodelingAlgorithm................................................................................................................................. 58
A. Odabasioglu, M. Celik, and L.T. Pileggi1D.2: A Block Rational Arnoldi Algorithm for Multipoint PassiveModel-Order Reduction of Multiport RLC Networks ............................................................. 66
I.M. Elfadel and D.D. Ling1D.3: Multipoint Padé Approximation Using a Rational Block LanczosAlgorithm................................................................................................................................. 72
T.V. Nguyen and J. Li
Session 2A: Multi-Level Synthesis and Covering ProblemModerators: Robert J. Francis, Xilinx, Inc., Toronto, Ontario, Canada Olivier Courdert, Synopsys, Inc., Mountain View, CA2A.1: The Disjunctive Decomposition of Logic Functions....................................................... 78
V. Bertacco and M. Damiani2A.2: Speeding Up Technology-Independent Timing Optimization byNetwork Partitioning .............................................................................................................. 83
R. Aggarwal, R. Murgai, and M. Fujita2A.3: Negative Thinking by Incremental Problem Solving: Applicationto Unate Covering ................................................................................................................... 91
E.I. Goldberg, L.P. Carloni, T. Villa,R.K. Brayton, and A.L. Sangiovanni-Vincentelli
Session 2B: Code Generation and Processor DesignModerators: P.A. Subrahmanyam, Stanford University, Stanford, CA Rolf Ernst, Technical University Braunschweig, Braunschweig, Germany2B.1: DSP Address Optimization Using a Minimum Cost CirculationTechnique .............................................................................................................................. 100
C. Gebotys2B.2: Application-Driven Synthesis of Core-Based Systems ................................................ 104
D. Kirovski, C. Lee, M.M. Potkonjak,and W. Mangione-Smith
2B.3: Power Optimization Using Divide-and-Conquer Techniques forMinimization of the Number of Operations.......................................................................... 108
I. Hong, M.M. Potkonjak, and R. Karri
Session 2C: High-Level Power Prediction and ReductionModerators: Chandu Visweswariah, IBM Corp., Yorktown Heights, NY Wen-Zen Shen, National Chiao Tung University, Hsinchu, Taiwan2C.1: High-Level Area and Power Estimation for VLSI Circuits ......................................... 114
M. Nemani and F.N. Najm2C.2: Optimizing Computations in a Transposed Direct Form Realizationof Floating-Point LTI-FIR Systems....................................................................................... 120
N. Sankarayya, K. Roy, and D. Bhattacharya2C.3: Achievable Bounds on Signal Transition Activity....................................................... 126
S. Ramprasad, N.R. Shanbhag, and I.N. Hajj
Session 2D: Noise Analysis and ModelingModerators: Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA Jue-Hsien Chern, Technology Modeling Associates, Inc., Sunnyvale, CA2D.1: Circuit Noise Evaluation by Padé Approximation BasedModel-Reduction Techniques ................................................................................................ 132
P. Feldmann and R.W. Freund2D.2: Global Harmony: Coupled Noise Analysis for Full-Chip RCInterconnect Networks.......................................................................................................... 139
K.L. Shepard, V. Narayanan, P.C. Elmendorf, and G. Zheng2D.3: Efficient Coupled Noise Estimation for On-Chip Interconnects ................................. 147
A. Devgan
Session 3A: High Level ValidationModerators: Christos Papachristou, Case Western Reserve University, Cleveland, OH Joachim Kunkel, Synopsys, Inc., Mountain View, CA3A.1: Efficient Circuit Partitioning to Extend Cycle SimulationBeyond Synchronous Circuits ............................................................................................... 154
C.J. DeVane3A.2: Verifying Correct Pipeline Implementation for Microprocessors................................ 162
J. Levitt and K. Olukotun3A.3: A Quantitative Approach to Functional Debugging.................................................... 170
D. Kirovski and M.M. Potkonjak
Session 3B: Timing AnalysisModerators: Chandu Visweswariah, IBM Corp., Yorktown Heights, NY Wen-Zen Shen, National Chiao Tung University, Hsinchu, Taiwan3B.1: Approximate Timing Analysis of Combinational Circuits under theXBDO Model.......................................................................................................................... 176
Y. Kukimoto, W. Gosti, A. Saldanha, and R.K. Brayton3B.2: Timing Analysis Based on Primitive Path Delay FaultIdentification ......................................................................................................................... 182
M. Sivaraman and A.J. Strojwas3B.3: Approximate Algorithms for Time Separation of Events ............................................ 190
S. Chakraborty and D.L. Dill
Session 4A: Embedded Tutorial: Microelectromechanical SystemsModerator: Bernard Courtois, TIMA Lab., Grenoble, France4A.1: Microelectromechanical Systems..................... ** Paper not available at time of publication
K.J. Gabriel
Session 4B: Embedded Tutorial: Optimization Techniques for High-PerformanceDigital CircuitsModerator: Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, PA4B.1: Optimization Techniques for High-Performance Digital Circuits .............................. 198
C. Visweswariah
Session 5A: Sequential Circuit OptimizationModerators: Marios Papaefthymiou, University of Michigan, Ann Arbor, MI Narendra V. Shenoy, Synopsys, Inc., Mountain View, CA5A.1: Sequential Optimization without State Space Exploration......................................... 208
A. Mehrotra, S. Qadeer, V. Singhal, R.K. Brayton, A. Aziz,and A.L. Sangiovanni-Vincentelli
5A.2: Minimum Area Retiming with Equivalent Initial States............................................ 216N. Maheshwari and S.S. Sapatnekar
5A.3: Decomposition and Technology Mapping of Speed-IndependentCircuits Using Boolean Relations ......................................................................................... 220
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno,E. Pastor, and A. Yakovlev
Session 5B: Advanced Scheduling TechniquesModerators: Miodrag M. Potkonjak, University of California, Los Angeles, CA David Ku, Escalade Corp., Santa Clara, CA5B.1: Scheduling and Binding Bounds for RT-Level Symbolic Execution ........................... 230
C. Monahan and F. Brewer5B.2: High-Level Scheduling Model and Control Synthesis for a BroadRange of Design Applications................................................................................................ 236
C.-T. Chen and K. Küçükçakar5B.3: Wavesched: A Novel Scheduling Technique for Control-FlowIntensive Behavioral Descriptions........................................................................................ 244
G. Lakshminarayana, K.S. Khouri, and N.K. Jha
Session 5C: Clock Design and OptimizationModerators: Masato Edahiro, C&C Research Labs., NEC Corp., Kawasaki, Japan Jason Cong, University of California, Los Angeles, CA5C.1: Optimal Wire and Transistor Sizing for Circuits with Non-TreeTopology................................................................................................................................. 252
L. Vandenberghe, S. Boyd, and A. El Gamal5C.2: Clock-Tree Routing Realizing a Clock-Schedule for Semi-Synchronous Circuits ............................................................................................................ 260
A. Takahashi, K. Inoue, and Y. Kajitani
5C.3: A Hierarchical Decomposition Methodology for Multistage ClockCircuits .................................................................................................................................. 266
G. Ellis, L.T. Pileggi, and R.A. Rutenbar
Session 5D: Circuit Simulation and OptimizationModerators: Ibrahim M. Elfadel, IBM Corp., Yorktown Heights, NY Wim van Bokhoven, Eindhoven University of Technology, Eindhoven, The Netherlands5D.1: A New High-Order Absolutely-Stable Explicit NumericalIntegration Algorithm for the Time-Domain Simulationof Nonlinear Circuits............................................................................................................. 276
R. Griffith and M. Nakhla5D.2: Circuit Optimization via Adjoint Lagrangians............................................................ 281
A.R. Conn, R.A. Haring,C. Visweswariah, and C.W. Wu
5D.3: State Transformation in Event Driven Explicit Simulation....................................... 289T.V. Nguyen and A. Devgan
Session 6A: New Ideas in EncodingModerators: Ellen M. Sentovich, Cadence Berkeley Labs., Berkeley, CA Pranav Ashar, C&C Research Labs., NEC USA, Inc., Princeton, NJ6A.1: A Fast and Robust Exact Algorithm for Face Embedding .......................................... 296
E.I. Goldberg, T. Villa, R.K. Brayton,and A.L. Sangiovanni-Vincentelli
6A.2: An Output Encoding Problem and a Solution Technique ........................................... 304S. Mitra, L.J. Avra, and E.J. McCluskey
6A.3: OPTIMIST: State Minimization for Optimal 2-Level LogicImplementation ..................................................................................................................... 308
R.M. Fuhrer and S.M. Nowick
Session 6B: Synthesis with Complex ComponentsModerators: Forrest D. Brewer, University of California, Santa Barbara, CA Kunle Olukotun, Stanford University, Stanford, CA6B.1: Resource Sharing in Hierarchical Synthesis............................................................... 318
O. Bringmann and W. Rosenstiel6B.2: Generalized Resource Sharing..................................................................................... 326
S. Raje and R.A. Bergamaschi6B.3: Exploiting Off-Chip Memory Access Modes in High-Level Synthesis ........................ 333
P.R. Panda, N.D. Dutt, and A. Nicolau
Session 6C: Partitioning Part IModerators: Naveed Sherwani, Intel Corp., Hillsboro, OR Chung-Kuan Cheng, University of California at San Diego, La Jolla, CA6C.1: Replication for Logic Bipartitioning ............................................................................ 342
M. Enos, S. Hauck, and M. Sarrafzadeh
6C.2: Partitioning Around Roadblocks: Tackling Constraints withIntermediate Relaxations...................................................................................................... 350
S. Dutt and H. Theny6C.3: Adaptive Methods for Netlist Partitioning .................................................................. 356
W.L. Buntine, L. Su, A.R. Newton, and A. Mayer
Session 6D: Analog Modeling and TestingModerators: Wim van Bokhoven, Eindhoven University of Technology, Eindhoven, The Netherlands Georges Gielen, Katholieke University Leuven, Leuven, Belgium6D.1: Symbolic Analysis of Large Analog Circuits with DeterminantDecision Diagrams ................................................................................................................ 366
C.-J.R. Shi and X. Tan6D.2: A Behavioral Signal Path Modeling Methodology for QualitativeInsight in and Efficient Sizing of CMOS Opamps ................................................................ 374
F. Leyn, W. Daems, G. Gielen, and W. Sansen6D.3: Test Generation for Comprehensive Testing of Linear AnalogCircuits Using Transient Response Sampling ...................................................................... 382
P.N. Variyam and A. Chatterjee
Session 7A: Sequential Circuit VerificationModerators: Carl P. Pixley, Motorola, Inc., Austin, TX Gianpiero Cabodi, Politecnico di Torino, Torino, Italy7A.1: Reachability Analysis Using Partitioned-ROBDDs..................................................... 388
A. Narayan, A.J. Isles, J. Jain, R.K. Brayton,and A.L. Sangiovanni-Vincentelli
7A.2: Record & Play: A Structural Fixed Point Iteration forSequential Circuit Verification ............................................................................................. 394
D. Stoffel and W. Kunz7A.3: Forward Model Checking Techniques Oriented to Buggy Designs ............................ 400
H. Iwashita and T. Nakata
Session 7B: BISTModerators: Janusz Rajski, Mentor Graphics Corp., Wilsonville, OR Ronald D. Blanton, Carnegie Mellon University, Pittsburgh, PA7B.1: BIST TPG for Faults in System Backplanes ............................................................... 406
C.-H. Chiang and S.K. Gupta7B.2: A Test Synthesis Technique Using Redundant Register Transfers............................ 414
C. Papachristou and M. Baklashov7B.3: Built-in Test Generation for Synchronous Sequential Circuits .................................. 421
I. Pomeranz and S.M. Reddy
Session 7C: Partitioning Part IIModerators: Charles J. Alpert, IBM Austin Research Lab., Austin, TX Atsushi Takahashi, Tokyo Institute of Technology, Tokyo, Japan7C.1: Hierarchical Partitioning for Field-Programmable Systems ...................................... 428
V.C. Chan and D. Lewis
7C.2: Hybrid Spectral/ Iterative Partitioning........................................................................ 436J.Y. Zien, P.K. Chan, and M. Schlag
7C.3: Large Scale Circuit Partitioning with Loose/Stable Net Removaland Signal Flow Based Clustering........................................................................................ 441
J. Cong, H.P. Li, S.K. Lim,T. Shibuya, and D. Xu
Session 7D: Efficient Techniques for Parasitics ExtractionModerators: David D. Ling, IBM Corp., Yorktown Heights, NY Sani R. Nassif, IBM Corp., Austin, TX7D.1: IES
3: A Fast Integral Equation Solver for Efficient
3-Dimensional Extraction ..................................................................................................... 448S. Kapur and D.E. Long
7D.2: FastPep: A Fast Parasitic Extraction Program for Complex Three-Dimensional Geometries ....................................................................................................... 456
M. Kamon, N. Marques, and J. White7D.3: Transform Domain Techniques for Efficient Extraction ofSubstrate Parasitics .............................................................................................................. 461
R. Gharpurey and S. Hosur
Session 8A: Embedded Tutorial: EDA and the NetworkModerator: David Ku, Escalade Corp., Santa Clara, CA8A.1: EDA and the Network.................................................................................................. 470
M.D. Spiller and A.R. Newton
Session 8B: Embedded Tutorial: Interconnect Design for Deep Submicron ICsModerator: Shuji Tsukiyama, Chuo University, Tokyo, Japan8B.1: Interconnect Design for Deep Submicron ICs ............................................................. 478
J. Cong, Z. Pan, L. He, C.-K. Koh, and K.-Y. Khoo
Session 9A: Power Estimation and ModelingModerators: Kaushik Roy, Purdue University, West Lafayette, IN Chandu Visweswariah, IBM Corp., Yorktown Heights, NY9A.1: Accurate Power Estimation for Large Sequential Circuits ......................................... 488
J.N. Kozhaya and F.N. Najm9A.2: Fast Power Estimation for Deterministic Input Streams ........................................... 494
L. Benini, G. De Micheli, E. Macii,M. Poncino, and R. Scarsi
9A.3: A Power Modeling and Characterization Method for MacrocellsUsing Structure Information ................................................................................................ 502
J.-Y. Lin, W.-Z. Shen, and J.-Y. Jou
Session 9B: Partitioning for HW/SW CodesignModerators: Allen C.-H. Wu, Tsing Hua University, Hsinchu, Taiwan Frank N. Vahid, University of California, Riverside, CA9B.1: Transformational Partitioning for Co-Design of MultiprocessorSystems.................................................................................................................................. 508
G.F. Marchioro, J.-M. Daveau, and A.A. Jerraya
9B.2: Hardware/Software Partitioning for Multi-Function Systems ................................... 516A. Kalavade and P.A. Subrahmanyam
9B.3: MOGAC: A Multiobjective Genetic Algorithm for the Co-Synthesisof Hardware-Software Embedded Systems........................................................................... 522
R.P. Dick and N.K. Jha
Session 9C: PlacementModerators: Dwight D. Hill, Synopsys, Inc., Mountain View, CA Malgorzata Marek-Sadowska, University of California, Santa Barbara, CA9C.1: NRG: Global and Detailed Placement ......................................................................... 532
M. Sarrafzadeh and M. Wang9C.2: Simulated Quenching: A New Placement Method for ModuleGeneration............................................................................................................................. 538
S. Sato9C.3: A Signature Based Approach to Regularity Extraction .............................................. 542
S.R. Arikati and R. Varadarajan
Session 9D: Fault Simulation and DiagnosisModerators: Robert Aitken, Hewlett-Packard Co., Palo Alto, CA Kwang-Ting Cheng, University of California, Santa Barbara, CA9D.1: Fault Simulation of Interconnect Opens in Digital CMOS Circuits ........................... 548
H. Konuk9D.2: GOLDENGATE: A Fast and Accurate Bridging Fault Simulator Undera Hybrid Logic/ IDDQ Testing Environment ........................................................................ 555
T. Chen and I.N. Hajj9D.3: A Deductive Technique for Diagnosis of Bridging Faults .......................................... 562
S. Venkataraman and W.K. Fuchs
Session 10A: Logic Synthesis for Low PowerModerators: Jordi Cortadella, University Politecnica de Catalunya, Barcelona, Spain Luciano Lavagno, Politecnico di Torino, Torino, Italy10A.1: Low Power Logic Synthesis for XOR Based Circuits ................................................ 570
U. Narayanan and C.L. Liu10A.2: An Exact Gate Decomposition Algorithm for Low-PowerTechnology Mapping ............................................................................................................. 575
H. Zhou and D.F. Wong10A.3: Trace Driven Logic Synthesis — Application to PowerMinimization ......................................................................................................................... 581
L.P. Carloni, P.C. McGeer, A. Saldanha,and A.L. Sangiovanni-Vincentelli
Session 10B: Analysis of Real Time SystemsModerators: Wayne Wolf, Princeton University, Princeton, NJ Ahmed A. Jerraya, TIMA-CMP Lab., Grenoble, France10B.1: Performance Analysis of a System of Communicating Processes ............................. 590
S. Dey and S. Bommu
10B.2: Embedded Program Timing Analysis Based on Path Clustering andArchitecture Classification.................................................................................................... 598
R. Ernst and W. Ye10B.3: Real Time Analysis and Priority Scheduler Generation forHardware-Software Systems with a Synthesized Run-Time System................................... 605
V.J. Mooney III and G. De Micheli
Session 10C: Interconnect OptimizationModerators: Wayne W.-M. Dai, University of California, Santa Cruz, CA John M. Cohn, IBM Corp., Richmond, VT10C.1: A New Approach to Simultaneous Buffer Insertion and Wire Sizing ....................... 614
C.C.N. Chu and D.F. Wong10C.2: Optimal Shape Function for a Bi-Directional Wire under ElmoreDelay Model........................................................................................................................... 622
Y. Gao and D.F. Wong10C.3: Global Interconnect Sizing and Spacing with Consideration ofCoupling Capacitance............................................................................................................ 628
J. Cong, L. He, C.-K. Koh, and Z. Pan
Session 10D: Implication and Test Generation TechniquesModerators: Pranav Ashar, C&C Research Labs., NEC USA, Inc., Princeton, NJ Jawahar Jain, Fujitsu Labs. of America, Inc., Santa Clara, CA10D.1: Test Generation for Primitive Path Delay Faults inCombinational Circuits ......................................................................................................... 636
R.C. Tekumalla and P.R. Menon10D.2: Fast Identification of Untestable Delay Faults UsingImplications........................................................................................................................... 642
K. Heragu, J.H. Patel, and V.D. Agrawal10D.3: A SAT-Based Implication Engine for Efficient ATPG,Equivalence Checking, and Optimization of Netlists ........................................................... 648
P. Tafertshofer, A. Ganz, and M. Henftling
Session 11A: Technology Driven SynthesisModerators: K.-C. Chen, Verplex Systems, Inc., Fremont, CA Shih-Chieh Chang, National Chung-Cheng University, Chaiayi, Taiwan11A.1: Library-Less Synthesis for Static CMOS Combinational Logic Circuits .................. 658
S. Gavrilov, A. Glebov, S. Pullela, S.C. Moore, A. Dharchoudhury,R. Panda, G. Vijayan, and D.T. Blaauw
11A.2: Logic Synthesis for Large Pass Transistor Circuits .................................................. 663P. Buch, A. Narayan, A.R. Newton, and A.L. Sangiovanni-Vincentelli
11A.3: An Exact Solution to Simultaneous Technology Mapping andLinear Placement Problem.................................................................................................... 671
J. Lou, A.H. Salek, and M. Pedram
Session 11B: System Specification and Product EngineeringModerators: Bernard Courtois, TIMA Lab., Grenoble, France Jerry R. Burch, Cadence Berkeley Labs., Berkeley, CA11B.1: An Efficient Statistical Analysis Methodology and Its Application toHigh-Density DRAMs............................................................................................................ 678
S.-H. Lee, C.-H. Choi, J.-T. Kong, W.-S. Lee, and J.-H. Yoo11B.2: Fast Field Solver Programs for Thermal and ElectrostaticAnalysis of Microsystem Elements ....................................................................................... 684
V. Székely and M. Rencz11B.3: Java as a Specification Language for Hardware-Software Systems ......................... 690
R. Helaihel and K. Olukotun
Session 11C: Performance-Driven RoutingModerators: D.F. Wong, University of Texas, Austin, TX Rajeev Jayaraman, Xilinx, Inc., San Jose, CA11C.1: Post-Route Optimization for Improved Yield Using a Rubber-Band Wiring Model ............................................................................................................... 700
J.Z. Su and W.W.-M. Dai11C.2: Delay Bounded Buffered Tree Construction for Timing DrivenFloorplanning ........................................................................................................................ 707
M. Kang, W.W.-M. Dai,T. Dillinger, and D. LaPotin
11C.3: Interconnect Layout Optimization Under Higher-Order RLC Model....................... 713J. Cong and C.-K. Koh
Session 11D: Test Theory and ApplicationsModerators: Fadi Maamari, LogicVision, Inc., San Jose, CA Sandeep K. Gupta, University of Southern California, Los Angeles, CA11D.1: Test and Diagnosis of Faulty Logic Blocks in FPGAs............................................... 722
S.-J. Wang and T.-M. Tsai11D.2: Partial Scan Delay Fault Testing of Asynchronous Circuits .................................... 728
M. Kishinevsky, A. Kondratyev, L. Lavagno,A. Saldanha, and A. Taubin
11D.3: Maximum Independent Sets on Transitive Graphs and TheirApplications in Testing and CAD.......................................................................................... 736
D. Kagaris and S. Tragoudas
Session 12A: Embedded Tutorial: Verifying Hardware in Its Software ContextModerator: Ellen M. Sentovich, Cadence Berkeley Labs., Berkeley, CA12A.1: Verifying Hardware in Its Software Context ............................................................ 742
R. Kurshan, V. Levin, M. Minea,D. Peled, and H. Yenigün
Session 12B: Embedded Tutorial: Simulation Methods for RF Integrated CircuitsModerator: Ralph H.J.M. Otten, Delft University of Technology, Delft, The Netherlands12B.1: Simulation Methods for RF Integrated Circuits........................................................ 752
K. Kundert
Author Index....................................................................................................................... 767
PROGRAM CHAIRHiroto YasuuraKyushu Univ.Dept. of CS & CE , Info Sci. Grad SchoolKasuga Koen, 6-1Kasuga, 816 Japan(81) [email protected]
FINANCE/PUBLICATIONS CHAIRDavid KuEscalade Corp.2475 Augustine Dr.Santa Clara, CA 95054(408) [email protected]
PAST CHAIRRob A. RutenbarCarnegie Mellon Univ.Dept. of ECE5000 Forbes Ave., Bldg. HH3107Pittsburgh, PA 15213(412) [email protected]
TUTORIAL CHAIRRobert C. AitkenHewlett-Packard Co.Design Tech. Ctr.1501 Page Mill Rd.Palo Alto, CA 94304-1126(415) [email protected]
PANEL CHAIRJacob WhiteMassachusetts Inst. of TechnologyDept. of EECS, Rm. 36-88050 Vassar St.Cambridge, MA 02139(617) [email protected]
PUBLICITY & AV CHAIREllen M. SentovichCadence Berkeley Labs.2001 Addison St., 3rd Fl.Berkeley, CA 94704-1103(510) [email protected]
EUROPEANREPRESENTATIVEBernard CourtoisTIMA Lab.46 Ave. Felix VialletGrenoble Cedex 38031, France(33) [email protected]
ASIAN REPRESENTATIVEShuji TsukiyamaChuo Univ.Dept. of Elect. & Elect. Engr.1-13-27 Kasuga, Bunkyo-kuTokyo, 112 Japan(81) [email protected]
SIGDA REPRESENTATIVERobert A. WalkerKent State Univ.Dept. of Math & CSKent, OH 44242(330) [email protected]
IEEE CS/DATCREPRESENTATIVECharles W. RosenthalCWR-Engineering Consultants3080 SW Fairmount Blvd.Portland, OR 97201-1439(503) [email protected]
CONFERENCE MANAGERKevin LepineMP Associates, Inc.5305 Spine Rd., Ste. ABoulder, CO 80301(303) [email protected]
CONFERENCE COMMITTEECONFERENCE CHAIRRalph H.J.M. OttenDelft Univ. of TechnologyLab. for Circuits & Systems, Dept. EEMekelweg 4, 2628 CD DelftThe Netherlands(31) [email protected]
Robert AitkenHewlett-Packard Co.Palo Alto, [email protected]
Pranav AsharC&C Res. Labs., NEC USA, Inc.Princeton, [email protected]
Ronald D. BlantonCarnegie Mellon Univ.Pittsburgh, [email protected]
Ivo BolsensIMECLeuven, [email protected]
Eric BrackenAnsoft Corp.Pittsburgh, [email protected]
Daniel BrandIBM Corp.Yorktown Heights, [email protected]
Forrest D. BrewerUniv. of CaliforniaSanta Barbara, [email protected]
Jerry R. BurchCadence Berkeley Labs.Berkeley, [email protected]
Gianpiero CabodiPolitecnico di TorinoTorino, [email protected]
Kuang-Chien ChenFujitsu Labs. of America, Inc.Santa Clara, [email protected]
Chung-Kuan ChengUniv. of California at San DiegoLa Jolla, [email protected]
Jue-Hsien ChernTechnology Modeling Assoc., Inc.Sunnyvale, [email protected]
John M. CohnIBM Corp.Richmond, [email protected]
Jordi CortadellaUniv. Politecnica de CatalunyaBarcelona, [email protected]
Bernard CourtoisTIMA Lab.Grenoble, [email protected]
Wayne W.-M. DaiUniv. of CaliforniaSanta Cruz, [email protected]
Masato EdahiroC&C Res. Labs., NEC Corp.Kawasaki, [email protected]
Ibrahim M. ElfadelIBM Corp.Yorktown Heights, [email protected]
Rolf ErnstTech. Univ. BraunschweigBraunschweig, [email protected]
Robert J. FrancisXilinx, Inc.Toronto, ON, [email protected]
Georges GielenKatholieke Univ. LeuvenLeuven, [email protected]
Rajesh K. GuptaUniv. of CaliforniaIrvine, [email protected]
Sandeep K. GuptaUniv. of Southern CaliforniaLos Angeles, [email protected]
Dwight D. HillSynopsys, Inc.Mountain View, [email protected]
Sasan ImanEscalade Corp.Santa Clara, [email protected]
Masaki ItoHitachi Ltd.Kanagawa-ken, [email protected]
Jawahar JainFujitsu Labs. of America, Inc.Santa Clara, [email protected]
Rajeev JayaramanXilinx, Inc.San Jose, [email protected]
Ahmed A. JerrayaTIMA-CMP Lab.Grenoble, [email protected]
Niraj K. JhaPrinceton Univ.Princeton, [email protected]
David KuEscalade Corp.Santa Clara, [email protected]
David D. LingIBM Corp.Yorktown Heights, [email protected]
Malgorzata Marek-SadowskaUniv. of CaliforniaSanta Barbara, [email protected]
ICCAD-97 TECHNICAL PROGRAM COMMITTEE
Shin-ichi MinatoStanford Univ.Stanford, [email protected]
Farid N. NajmUniv. of IllinoisUrbana, [email protected]
Sani R. NassifIBM Corp.Austin, [email protected]
Ryosuke OkudaMitsubishi Electric Corp.Hyogo, [email protected]
Kunle OlukotunStanford Univ.Stanford, [email protected]
Christos PapachristouCase Western Reserve Univ.Cleveland, [email protected]
Marios C. PapaefthymiouUniv. of MichiganAnn Arbor, [email protected]
Janak H. PatelUniv. of IllinoisUrbana, [email protected]
Carl P. PixleyMotorola, Inc.Austin, [email protected]
Miodrag M. PotkonjakUniv. of CaliforniaLos Angeles, [email protected]
Janusz RajskiMentor Graphics Corp.Wilsonville, [email protected]
Kaushik RoyPurdue Univ.West Lafayette, [email protected]
Ellen M. SentovichCadence Berkeley Labs.Berkeley, [email protected]
Wen-Zen ShenNational Chiao Tung Univ.Hsinchu, Taiwan [email protected]
Naveed SherwaniIntel Corp.Hillsboro, [email protected]
Takeshi ShimaToshiba Corp.Kawasaki, [email protected]
Jyuo-Min ShyuERSO/ITRIHsinchu, Taiwan [email protected]
L. Miguel SilveiraINESC/ISTLisboa, [email protected]
Chauchin SuNational Central Univ.Taiwan, [email protected]
P.A. SubrahmanyamStanford Univ.Stanford, [email protected]
Atsushi TakahashiTokyo Inst. of Tech.Tokyo, [email protected]
Kazuo TakiKobe Univ.Kobe, [email protected]
Jerzy TyszerPoznan Univ. of Tech.Poznan, [email protected]
Chandu VisweswariahIBM Corp.Yorktown Heights, [email protected]
Ted VucurevichCadence Design Systems, Inc.San Jose, [email protected]
D.F. WongUniv. of TexasAustin, [email protected]
Allen C.-H. WuTsing Hua Univ.Hsinchu, Taiwan [email protected]
Wim van BokhovenEindhoven Univ. of Tech.Eindhoven, The [email protected]
ICCAD-97 TECHNICAL PROGRAM COMMITTEE
TUTORIAL 1
TIMING ANALYSIS AND OPTIMIZATION: FROM DEVICES TO SYSTEMS
Speakers:
Anirudh Devgan, IBM Austin Research Lab., Austin, TX
Leon Stok, IBM Thomas J. Watson Research Ctr., Yorktown Heights, NY
Sandip Kundu, Intel Corp., Santa Clara, CA
Background: This tutorial is intended for researchers and practitioners of timing analysis andoptimization in both ASIC and custom design environments. Basic knowledge of timing analysis andcircuit theory would be useful.
Description: Timing analysis is an integral part of the design process at all levels of abstraction. Deepsub-micron design, including both custom design and ASIC design, rely heavily on timing analysis andoptimization to achieve required performance. This tutorial presents a comprehensive description oftiming analysis and optimization techniques. The tutorial is divided into three broad areas, with the firstone covering transistor and interconnect level analysis and optimization. Logic level analysis andoptimization and links to logic synthesis are described in the second part. Dependency of timing analysison logic functionality and vice versa is presented in the last part.
Higher operating frequencies, newer process technologies and advanced circuit families require timinganalysis and optimization to be done at the device level. The first part of the tutorial will present deviceand interconnect level techniques, including device and interconnect modeling, transistor level statictiming, dynamic timing simulation, interconnect model reduction, buffer insertion and sizing.
Static timing analysis has been an integral part of performance driven logic synthesis. In logic synthesisenvironment, static timing analysis needs to have incremental update capability. Description of logic level statictiming and optimization will include delay calculator language, logic restructuring, repowering and retiming.
Timing and functionality are interdependent. A topologically long path may not propagate a changingsignal, in which case it is called a false path. For the purpose of accurate timing analysis all such pathsmust be excluded from consideration. In the last part of the tutorial, the false path analysis problem isdescribed with discussion of two basic analysis techniques, one based on enumeration and examination ofpaths and the other based on threshold approach.
TUTORIAL 2
DESIGN TECHNOLOGY FORBUILDING WIRELESS SYSTEMS
Speakers:
Rajesh K. Gupta, Univ. of California, Irvine, CA
Mani B. Srivastava, Univ. of California, Los Angeles, CA
Background: This tutorial is targeted for practicing engineers interested in system and IC designtechniques for building wireless systems. CAD developers and researchers will develop an appreciationof the design tool requirements for wireless networked computing systems.
Description: The progress in IC technology is making chips that incorporate all the elements of acomplete wireless radio system on a chip a real possibility. Such an “antenna-to-network’’ chip wouldincorporate an RF front end, baseband digital signal processing, link layer coding functions for error,compression, and encryption, and medium access control and other network protocols. This requiresintegration of analog circuits, high performance custom signal processing datapaths and cores,customized logic, embedded processor, and complex software environments on the same chip. Thedesign, simulation, implementation, and testing techniques required for such chips are complex, as are themetrics to evaluate the performance. The current effort in standardization of pre-designed macromodules,often referred to as “core cells”, is expected to play a major role in making it possible for designers tobuild complete and customized wireless systems on a chip. However, the diversity of macromodulesrequired in such wireless systems on a chip represents a special challenge in almost all aspects ofIC/System design. In this tutorial we present the state of the art in designing such systems, focusing onboth the CAD problems that arise from such chips as well as on the tools and design techniques. Thepresentation is roughly divided into three parts: basics of wireless systems; VLSI design issues forwireless systems; design tools and techniques for hardware and software for wireless systems.
Rajesh Guptais an assistant professor in Information and Computer Science at UC Irvine. His interestsare in system-level design and CAD for embedded systems. Prior to his current position, he worked onCMOS, BiCMOS, ECL and high-speed GaAs chips while at Intel Corp.
Mani Srivastavais on the EE faculty at UCLA. His research activities include wireless and mobile ATM,low power wireless systems, adaptive wireless multimedia computing nodes, low power softwareprogrammable systems, and transformation-based DSP synthesis.
TUTORIAL 3
MODELING AND SYNTHESISOF BEHAVIOR, CONTROL AND DATAFLOW
Speakers:
Raul Camposano, Synopsys, Inc., Mountain View, CA
Andrew Seawright, Synopsys, Inc., Mountain View, CA
Joseph Buck, Synopsys, Inc., Mountain View, CA
Background: This tutorial is for digital circuit designers, EDA professionals and researchers interestedin the use of higher levels of abstraction in the design of digital systems. It covers a broad range of topicsgiving an overview of the techniques used in current “system level” tools.
Description: To tackle the exponential growth in the complexity of digital circuits, designers are movingto higher levels of abstraction in the design process. This tutorial aims to be an introduction to the stateof the art in modeling and synthesis above the RTL level. The tutorial will focus in three areas: 1) thedesign and synthesis of digital systems using behavioral synthesis techniques, 2) the modeling andsynthesis of complex controllers at using abstractions higher than FSMs and 3) the design and analysis ofDSP/Dataflow systems using various data flow models and methods.
Raul Camposano will introduce the concepts of behavioral synthesis applied to the implementation ofalgorithms. Principles of scheduling, allocation, and advanced arithmetic optimization techniques will becovered. The section ends with some typical applications and results for behavioral synthesis.
Andrew Seawright will present an overview of techniques for describing control at higher levels ofabstraction. The focus will be on methods for describing the “what” and not the “how” of the controlproblem while maintaining a cycle accurate representation. Methods for the synthesis of the underlyingFSMs will be covered using classical FSM synthesis techniques and more recent implicit techniques.
Joseph Buck will present an overview of the DSP design process and introduce several models of dataflow computation and their properties including Dynamic Data Flow, Synchronous Data Flow, andBoolean Data Flow models. System design flow, codesign, and the modeling of heterogenous systemswill be covered.
Raul Camposanois Vice President and General Manager of the Synopsys Design Tools Group. Prior tohis current position, he held different engineering positions, including Vice President of Engineering ofthe Synopsys Design Tools Group.
Andrew Seawrightis an R&D staff member of the Synopsys Design Tools Group. He is a principalarchitect of the Dali environment for the design of structured control logic for telecommunications andrelated application domains.
Joseph Buckis a member of the Synopsys Advanced Technology Group working in the areas of DSP andDataflow design technology. Prior to joining Synopsys he was a principal architect of the Ptolemy system.
TUTORIAL 4
CRITICAL TECHNOLOGIES ANDMETHODOLOGIES FOR SYSTEMS-ON-CHIPS
Speakers:
Wayne Dai, Univ. of California, Santa Cruz, CA
Howard Kalter , IBM Corp., Essex Junction, VT
Rob Roy, Intel Corp., Hillsboro, OR
Wayne Wolf, Princeton Univ., Princeton, NJ
Background: This tutorial is intended for designers, CAD tool developers, and researchers interested insystems-on-chips. It will examine the relationships between different design challenges to give the attendee aholistic view of the entire design process.
Description: This tutorial will present a survey of design challenges awaiting the industry in the systems-on-chips era. Systems-on-chips present new design challenges at every level of abstraction, ranging from theneed to drive 500 MHz clocks across 100 million transistor chips to the problem of designing a complexchip to meet an ever-shortening product window. This tutorial will present problems in four areas critical forsuccessfully designing systems-on-chips: Embedded RAM: various memory types; manufacturability,testability, diagnosability of embedded DRAM memory; technology and software tool requirements; chipsthat have used embedded memory; and a method of approach to the design problems. Low-power design,including circuit and system-level techniques. Low-power design is important not only for portable systemsbut also for any system where cooling and power supply costs are important. High-speed interconnect, whichwill be the dominant component of delay in many large systems-on-chips. Interconnection problems includemodeling of deep submicron interconnect and placement and routing algorithms which take into accountboth delay and crosstalk. Hardware/software co-design, which is one of the few ways in which large, high-functionality chips can be designed in the short intervals required by today’s markets. Co-design allowscustom multiprocessors to be designed which efficiently implement application-specific systems. Problemsinclude scheduling, allocation, processing element selection, and memory/communication synthesis.
Wayne Daiis an Associate Professor in the Computer Science and Engineering Department at UC SantaCruz. He received his Ph.D. from UC Berkeley. He has extensively studied placement and routing forVLSI and MCM systems.
Howard L. Kalteris with IBM Corporation in Essex Junction, Vermont. He has worked on memory chipdesign on both static and dynamic memory, memory systems, and alterable logic and memory devices.
Rob Roymanages a low-power design group at Intel Corporation in Hillsboro, Oregon. Before joining Intel,he was with the NEC C&C Research Lab. Roy has conducted research in low-power design and core-basedsystem design among other topics.
Wayne Wolfis an Associate Professor in the Department of Electrical Engineering at Princeton University.Before joining Princeton, he was with AT&T Bell Laboratories in Murray Hill, New Jersey. He hasstudied hardware/software co-design as well as many other areas of VLSI CAD.
Magdy Abadir
Rajat Aggarwal
Robert Aitken
Enamul Amyeen
James Anderson
Fabio Angelillis
Peter Arato
Guido Araujo
Hideki Asai
Pranav Ashar
Toru Awashima
Iris Bahar
Felice Balarin
Jeffrey Bell
Vaughn Betz
Ronald DeShawn Blanton
Ivo Bolsens
Vamsi Boppana
Eric Bracken
Daniel Brand
Forrest D. Brewer
Oliver Bringmann
Premal Buch
Jerry R. Burch
Gianpiero Cabodi
Juan Antonio Carbalo
Jordi Carrabina
Robert Carragher
Francky Catthoor
V. Chandramouli
Douglas Chang
Shih-Chieh Chang
Tsin-Yuan Chang
Yaowen Chang
Kai-Yuan Chao
Chung-Ping Chen
De-Sheng Chen
Jwu-E Chen
Kuang-Chien Chen
Yung-Yuan Chen
Zhanping Chen
Chung-Kuan Cheng
Wei-Kai Cheng
Jue-Hsien Chern
Chenhuan Chiang
Eli Chiprout
Mike Chou
Amit Chowdhary
Kevin Chung
Min-Feng Chung
Johan Cockx
John M. Cohn
Jordi Cortadella
Bernard Courtois
Walter Daems
Wayne W.-M. Dai
Giovanni De Micheli
Bart De Smedt
Stefan Donnay
Masato Edahiro
Aiman El-Maleh
Ibrahim M. Elfadel
Shinya Emoto
Rolf Ernst
Robert J. Francis
Hisanori Fujisawa
Masahiro Fujita
Tomoyuki Fujita
Kunihiro Fujiyoshi
Youxin Gao
Edelweis Garcez
Ricard Gavalda
Joachim Gerlach
Georges Gielen
Manish Goel
Eugene Goldberg
Arny Goldfein
Wilsin Gosti
Pei-Ning Guo
Aarti Gupta
Rajesh K. Gupta
Sandeep K. Gupta
Subodh Gupta
Gary D. Hachtel
Ibrahim Hajj
Jonathan Halter
Cordula Hansen
Ikuo Harada
Abu Hassan
Toshihiro Hattori
Gunter Haug
Lei He
Hans Hegt
Gerald Heim
Keerthi Heragu
Andre Hergenhan
Dwight D. Hill
Yuzo Hirai
Inki Hong
Michael Hsiao
Frank Hsu
Ing-Jer Huang
Mike Hutton
Jim Hwang
Tin-Tin Hwang
TingTing Hwang
Yean-You Hwang
Sasan Iman
Yasuaki Inoue
Shinya Ishihara
Nagisa Ishiura
ICCAD-97 REVIEWERS
Tsuyoshi Isshiki
Tetsuro Itakura
Kazuhito Ito
Masaki Ito
Tomonori Izumi
Jawahar Jain
Rajeev Jayaraman
Ahmed A. Jerraya
Niraj K. Jha
Mark Johnson
Wen-Ben Jone
Jing-Yang Jou
Shyh-Jye Jou
Yoji Kajitani
Mineo Kaneko
Deyu Kao
William Kao
Tanay Karnik
Masaru Katayama
Hideyuki Kawakita
Omar Kebichi
Sunil Khatri
Kei-Yong Khoo
Hyungwon Kim
Shinji Kimura
Tomohisa Kimura
Darko Kirovski
Michael Kishinevsky
Susumu Kobayashi
Gernot Koch
Alex Kondratyev
Raymond Kong
Joseph Kozhaya
Dilip Krishnaswamy
David Ku
Shun-ichi Kubo
Thommy Kuhn
Yuji Kukimoto
Arno Kunzmann
Mototaka Kuribayashi
Walter Lange
David Lapotin
Chung-Len Lee
Chunho Lee
Kenny Lee
Kuen-Jong Lee
Kyung T. Lee
Domine Leenaerts
Yau-Tsun Steven Li
Jiing-Yuan Lin
Poyang Lin
Youn-Long Lin
David D. Ling
Joe Linoff
Frank Liu
Per B. Ljung
Paulo Maciel
Malgorzata Marek-Sadowska
Hans-Georg Martin
Akira Matsugawa
Osamu Matsumoto
Robert L. Maziasz
Dinesh Mehta
Noel Menezes
Shin-ichi Minato
Sujoy Mitra
Hideki Mitsubayashi
Hiroshi Miyashita
Akihiko Miyazaki
Toshiaki Miyazaki
Yuichi Miyazawa
Sundararajarao Mohan
Takashi Morie
Dinos Moundanos
Rajarshi Mukherjee
Rajeev Murgai
Enric Musoll
Sudip Nag
Akira Nagao
Farid N. Najm
Koji Nakajima
Shigetoshi Nakatake
Amit Narayan
Francisco Nascimento
Sani R. Nassif
Mahadevamurty Nemani
Jeff Newquist
Tuyen Nguyen
Tetsuo Nishi
Shinya Nishikawa
Masahiro Numa
Emil Ochotta
Kimihiro Ogawa
Takuji Ogihara
Takumi Okamoto
Ryosuke Okuda
Makiko Okumura
Kunle Olukotun
Hidetoshi Onodera
Shoji Otaka
Steve Otto
Andras Pahi
David Z. Pan
Christos Papachristou
Marios C. Papaefthymiou
SeungJoon Park
Enric Pastor
Janak H. Patel
Massoud Pedram
Kris Pister
Carl P. Pixley
ICCAD-97 REVIEWERS
Miodrag M. Potkonjak
Gang Qu
Janusz Rajski
Rajeev Ranjan
Subodh Reddy
Marta Rencz
June-Kyung Rho
Lluis Ribas
Michael Riepe
Jordi Riera
Jing Roddy
Wolfgang Rosenstiel
Charles Rosenthal
Don Ross
Kaushik Roy
Dan Saab
Kazuyuki Saijo
Toshiyuki Saito
Takayasu Sakurai
William Salefski
N. Sankarayya
Andisheh Sarabi
Hisashi Sasaki
Mamoru Sasaki
Toshinori Sato
Gurjeet Saund
Hirosi Sawada
Prashant Sawkar
Ellen M. Sentovich
Maria J. Serna
Lu Sha
Debendra Das Sharma
Wen-Zen Shen
Naveed Sherwani
Yuji Shigehiro
Takeshi Shima
Jyuo-Min Shyu
L. Miguel Silveira
Jens Ulrik Skakkebaek
Rajan Sree
Bill Stiehl
Chauchin Su
Ming Su
P.A. Subrahmanyam
Ashok Sudarsanam
Yasuhiro Sugimoto
Vladimir Szekely
Shigetaka Takagi
Atsushi Takahara
Atsushi Takahashi
Wataru Takahashi
Hajime Takakubo
Yasuhiro Takashima
Hideki Takeuchi
Kazuo Taki
Seiichiro Tani
Hiroshi Tanimoto
Alexandre Taubin
Peter Thole
Rob Thompson
Jerzy Tyszer
Taku Uchino
Hiroshi Uno
Akio Ushida
Wim van Bokhoven
David Van Campenhout
Geert Van der Plas
Lieven VandenBerg
Jan Vandenbussche
Jan Vandersteen
Srikanth Venkatraman
Steven Vercauteren
Wim Verhaegen
Diederik Verkest
Frederik Vermeulen
Chandu Visweswariah
Ted Vucurevich
Shinichi Wakabayashi
Duncan M. Walker
Hank Walker
Chuanyu Wang
Li-Chung Wang
Sying-Jyan Wang
Takahiro Watanabe
Christoph Weiler
Karlheinz Weiss
Jacob K. White
Jesse Whittemore
Ralph Wittig
D.F. Wong
Allen C.-H. Wu
Chang Wu
Cheng-Wen Wu
Tsung-Yi Wu
Mary Xin
Jin Xu
Songjie Xu
Alexandre Yakovlev
Hakan Yalcin
Masaaki Yamada
Toshinori Yamada
Kiyotaka Yamamura
Shigeru Yamashita
Hannah Yang
Yibin Ye
Toshihiko Yokomaru
Goichi Yokomizo
Michio Yotsuyanagi
Jian-Kun Zhao
Kai Zhu
ICCAD-97 REVIEWERS
KEYNOTE ADDRESS
John K. OusterhoutDistinguished EngineerSun Microsystems, Inc.
Scripting languages such as Perl and Tcl represent a very different style of programming than systemprogramming languages such as C or Java. In this talk I will explain why scripting languages providemore rapid application development than system programming languages and why scripting languages arebecoming more and more important for applications of the future. I will also give a short history of Tcl(it was motivated by my work in ECAD in the early 1980’s), describe its current status, and speculateabout where Tcl is headed for the future, such as integration with Java.
John K. Ousterhout is a Distinguished Engineer at Sun Microsystems, Inc. His interests include scriptinglanguages, user interfaces, operating systems, and distributed systems. He is the creator of the Tclscripting language and the Tk toolkit. In the past, he led the development of the Sprite network operatingsystem and several widely-used programs for computer-aided design, including Magic and Crystal.Ousterhout is a Fellow of the ACM and has received many awards, including the ACM Grace MurrayHopper Award, the National Science Foundation Presidential Young Investigator Award, and the UCBDistinguished Teaching Award. He received a B.S. degree in Physics from Yale University in 1975 and aPh.D. in Computer Science from Carnegie Mellon University in 1980. From 1980 to 1994 he was aProfessor in the Department of Electrical Engineering and Computer Sciences at the University ofCalifornia at Berkeley.
Session Index
Session 1A: Decision Diagram ApplicationsSession 1B: Optimization and Synthesis for Reactive SystemsSession 1C: Estimation of Power BoundsSession 1D: Block Krylov Methods for Interconnect ModelingSession 2A: Multi-Level Synthesis and Covering ProblemSession 2B: Code Generation and Processor DesignSession 2C: High-Level Power Prediction and ReductionSession 2D: Noise Analysis and ModelingSession 3A: High Level ValidationSession 3B: Timing AnalysisSession 4A: Embedded Tutorial: Microelectromechanical SystemsSession 5A: Sequential Circuit OptimizationSession 5B: Advanced Scheduling TechniquesSession 5C: Clock Design and OptimizationSession 5D: Circuit Simulation and OptimizationSession 6A: New Ideas in EncodingSession 6B: Synthesis with Complex ComponentsSession 6C: Partitioning Part ISession 6D: Analog Modeling and TestingSession 7A: Sequential Circuit VerificationSession 7B: BISTSession 7C: Partitioning Part IISession 7D: Efficient Techniques for Parasitics ExtractionSession 8A: Embedded Tutorial: EDA and the NetworkSession 8B: Embedded Tutorial: Interconnect Design for Deep Submicron ICsSession 9A: Power Estimation and ModelingSession 9B: Partitioning for HW/SW CodesignSession 9C: PlacementSession 9D: Fault Simulation and DiagnosisSession 10A: Logic Synthesis for Low PowerSession 10B: Analysis of Real Time SystemsSession 10C: Interconnect OptimizationSession 10D: Implication and Test Generation TechniquesSession 11A: Technology Driven SynthesisSession 11B: System Specification and Product EngineeringSession 11C: Performance-Driven RoutingSession 11D: Test Theory and ApplicationsSession 12A: Embedded Tutorial: Verifying Hardware in Its Software ContextSession 12B: Embedded Tutorial: Simulation Methods for RF Integrated Circuits
Author Index
Aggarwal, R............................................. 83Agrawal, V.D..........................................642Arikati, S.R.............................................542Avra, L.J.................................................304Aziz, A. ...................................................208Baklashov, M..........................................414Becker, B. .................................................. 8Benini, L...........................................13, 494Bergamaschi, R.A...................................326Bertacco, V. ............................................. 78Bhattacharya, D.....................................120Blaauw, D.T. ..........................................658Bommu, S. ..............................................590Boyd, S. ..................................................252Brayton, R.K. ........... 91, 176, 208, 296, 388Brewer, F................................................230Bringmann, O. .......................................318Bryant, R.E. .............................................. 2Buch, P. ..................................................663Buntine, W.L..........................................356Carloni, L.P. .....................................91, 581Celik, M. .................................................. 58Chakraborty, S. ......................................190Chan, P.K. ..............................................436Chan, V.C. ..............................................428Chatterjee, A. .........................................382Chen, C.-T. .............................................236Chen, T. ..................................................555Chen, Y.-A. ................................................ 2Chen, Z. ................................................... 40Chiang, C.-H. .........................................406Choi, C.-H...............................................678Chou, T.-L. .............................................. 40Chu, C.C.N. ............................................614Cong, J............................ 441, 478, 628, 713Conn, A.R. ..............................................281Cortadella, J. ..........................................220Daems, W. ..............................................374Dai, W.W.-M...................................700, 707Damiani, M. ............................................ 78Daveau, J.-M. .........................................508De Micheli, G. .......................... 13, 494, 605DeVane, C.J............................................154
Devgan, A....................................... 147, 289Dey, S. ....................................................590Dharchoudhury, A. ................................658Dick, R.P. ...............................................522Dill, D.L. ................................................190Dillinger, T.............................................707Drechsler, R. ..............................................8Dutt, N.D. ..............................................333Dutt, S....................................................350El Gamal, A............................................252Elfadel, I.M. .............................................66Ellis, G. ..................................................266Elmendorf, P.C.......................................139Enos, M. .................................................342Ernst, R. .................................................598Feldmann, P...........................................132Freund, R.W...........................................132Fuchs, W.K.............................................562Fuhrer, R.M. ..........................................308Fujita, M. .................................................83Ganz, A...................................................648Gao, Y.....................................................622Gavrilov, S. ............................................658Gebotys, C. .............................................100Gharpurey, R. ........................................461Gielen, G. ...............................................374Glebov, A. ...............................................658Goldberg, E.I. ................................... 91, 296Gosti, W..................................................176Griffith, R...............................................276Gupta, R.K. ..............................................22Gupta, S.K. ............................................406Hajj, I.N. ........................................ 126, 555Haring, R.A. ...........................................281Hauck, S.................................................342He, L............................................... 478, 628Helaihel, R. ............................................690Henftling, M...........................................648Heragu, K...............................................642Hong, I. ..................................................108Hosur, S. ................................................461Hsiao, M.S................................................45Hwang, C.-H. ...........................................28
Inoue, K..................................................260Isles, A.J. ................................................388Iwashita, H.............................................400Jain, J.....................................................388Jerraya, A.A. ..........................................508Jha, N.K. ........................................244, 522Jou, J.-Y. ................................................502Kagaris, D. .............................................736Kajitani, Y. .............................................260Kalavade, A. ...........................................516Kamon, M...............................................456Kang, M..................................................707Kapur, S. ................................................448Karri, R. ...........................................33, 108Khoo, K.-Y. .............................................478Khouri, K.S. ...........................................244Kim, K. .................................................... 33Kirovski, D. ....................................104, 170Kishinevsky, M. .....................................220Kishinevsky, M. .....................................728Koh, C.-K................................ 478, 628, 713Kondratyev, A. ...............................220, 728Kong, J.-T...............................................678Konuk, H. ...............................................548Kozhaya, J.N. .........................................488Küçükçakar, K. ......................................236Kukimoto, Y. ..........................................176Kundert, K. ............................................752Kunz, W..................................................394Kurshan, R. ............................................742Lakshminarayana, G. ............................244LaPotin, D. .............................................707Lavagno, L......................................220, 728Lee, C. ....................................................104Lee, S.-H.................................................678Lee, W.-S. ...............................................678Levin, V. .................................................742Levitt, J. .................................................162Lewis, D..................................................428Leyn, F. ..................................................374Li, H.P. ...................................................441Li, J. ........................................................ 22Li, J. ........................................................ 72Lim, S.K. ................................................441Lin, J.-Y..................................................502Ling, D.D................................................. 66
Liu, C.L. .................................................570Long, D.E. ..............................................448Lou, J. ....................................................671Macii, E. .................................................494Maheshwari, N. .....................................216Mangione-Smith, W. ..............................104Marchioro, G.F.......................................508Marques, N. ...........................................456Mayer, A.................................................356McCluskey, E.J. .....................................304McGeer, P.C. ..........................................581Mehrotra, A............................................208Menon, P.R.............................................636Minea, M. ...............................................742Mitra, S. .................................................304Monahan, C............................................230Mooney III, V.J. .....................................605Moore, S.C..............................................658Murgai, R. ................................................83Najm, F.N....................................... 114, 488Nakata, T. ..............................................400Nakhla, M. .............................................276Narayan, A..................................... 388, 663Narayanan, U. .......................................570Narayanan, V.........................................139Nemani, M. ............................................114Newton, A.R. .......................... 356, 470, 663Nguyen, T.V. .................................... 72, 289Nicolau, A...............................................333Nowick, S.M. ..........................................308Odabasioglu, A. ........................................58Olukotun, K. .................................. 162, 690Pan, Z. ............................................ 478, 628Panda, P.R. ............................................333Panda, R.................................................658Papachristou, C......................................414Pastor, E.................................................220Patel, J.H. ........................................ 45, 642Pedram, M..............................................671Peled, D..................................................742Pileggi, L.T....................................... 58, 266Pomeranz, I. ...........................................421Poncino, M. ............................................494Potkonjak, M.M. .............. 33, 104, 108, 170Pullela, S. ...............................................658Qadeer, S................................................208
Raje, S. ...................................................326Ramprasad, S. ........................................126Reddy, S.M. ............................................421Rencz, M.................................................684Rosenstiel, W..........................................318Roy, K.........................................40, 52, 120Rudnick, E.M. ......................................... 45Rutenbar, R.A. .......................................266Saldanha, A. ........................... 176, 581, 728Salek, A.H. .............................................671Sangiovanni-Vincentelli, A.L. ..........91, 208Sangiovanni-Vincentelli, A.L. ........296, 388Sangiovanni-Vincentelli, A.L. ........581, 663Sankarayya, N. ......................................120Sansen, W...............................................374Sapatnekar, S.S......................................216Sarrafzadeh, M...............................342, 532Sato, S. ...................................................538Scarsi, R. ................................................494Schlag, M................................................436Scholl, C. ................................................... 8Shanbhag, N.R. ......................................126Shen, W.-Z..............................................502Shepard, K.L. .........................................139Shi, C.-J.R. .............................................366Shibuya, T. .............................................441Singhal, V...............................................208Sivaraman, M.........................................182Spiller, M.D. ...........................................470Stoffel, D.................................................394Strojwas, A.J. .........................................182Su, J.Z. ...................................................700Su, L. ......................................................356
Subrahmanyam, P.A..............................516Székely, V...............................................684Tafertshofer, P. ......................................648Takahashi, A. .........................................260Tan, X.....................................................366Taubin, A. ..............................................728Tekumalla, R.C. .....................................636Theny, H. ...............................................350Tragoudas, S. .........................................736Tsai, T.-M...............................................722Vandenberghe, L....................................252Varadarajan, R.......................................542Variyam, P.N. ........................................382Venkataraman, S. ..................................562Vijayan, G. .............................................658Villa, T.............................................. 91, 296Visweswariah, C. ........................... 198, 281Vuillod, P..................................................13Wang, C.-Y. ..............................................52Wang, M.................................................532Wang, S.-J. .............................................722White, J. .................................................456Wong, D.F. ............................. 575, 614, 622Wu, A.C.-H...............................................28Wu, C.W. ................................................281Xu, D. .....................................................441Yakovlev, A. ...........................................220Ye, W......................................................598Yenigün, H.............................................742Yoo, J.-H.................................................678Zheng, G.................................................139Zhou, H. .................................................575Zien, J.Y. ................................................436