sir c.r.reddy college of engineering eluru-534007 ... · digital signal processing lab manual (ec -...

Dept of Electronics and Communications Engg., 1

SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU-534007

Department of Electronics and Communications

DIGITAL SIGNAL PROCESSING Lab Manual (EC - 418) For IV / IV B.E (ECE), I - Semester

SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU-534007


Digital Signal Processing Lab

LIST OF EXPERIMENTS MAT LAB EXPERIMENTS:

1. GENERATION OF DISCRETE –TIME SIGNALS

2. CONVOLUTION OF DISCRETE – TIME SIGNALS

3. FREQUENCY RESPONSE OF DISCRETE TIME SYSTEMS

4. DISCRETE TIME FOURIER TRANSFORM

5. COMPUTATION OF DFT

6. DESIGN OF IIR DIGITAL FILTER

7. DESIGN OF FIR DIGITAL FILTER

VHDL EXPERMENTS : 1. SIMULATION OF DECODER, ENCODER, MULTIPLEXER AND

DEMULTIPLEXER

2. SIMULATION OF PARALLEL ADDER AND BCD ADDER

3. SIMULATION OF BCD TO SEVEN SEGMENT DECODER AND B-G

& G-B CODE CONVERTERS

4. SIMULATION OF FLIP-FLOPS

5. SIMULATION OF SYNCHRONOUS UP/DOWN AND BCD

COUNTERS

6. SIMULATION OF SHIFT REGISTER AND BARREL SHIFTER

REGISTER

7. FSM IMPLEMENTATION OF GRAY CODE COUNTER AND

SEQUENCE DETECTOR


1. GENERATION OF UNIT IMPULSE,UNIT

STEP , UNIT RAMP, REAL EXPONENTIAL AND SINUSOIDAL

SEQUENCES


GENERATION OF DISCRETE-TIME SIGNALS

AIM: Write a MATLAB program for the generation of unit impulse, unit step, ramp, exponential and Sinusoidal sequences. PROGRAM:

%program for the generation of unit impulse sequence [δ (n)] K=input ('enter the length of sequence of K :'); n= - K: 1: K; x= [zeros (1, K), ones (1, 1), zeros (1, K)]; subplot (5, 1, 1); stem (n, x); xlabel('time index'); ylabel ('s(n)'); title ('unit impulse'); %program for the generation of unit step sequence [u (n)] L=input ('enter length of sequence of L :'); n= - L: 1: L; x= [zeros (1, L), ones (1, L+1)]; subplot (5,1,2); stem (n,x); xlabel('time index'); ylabel('u(n)'); title ('unit step'); %program for the generation of exponential sequence x (n) =c (a) n M=input ('enter sequence length of M :'); n=0: M; B=input ('enter value of B :'); d=B; C=input ('enter a value of C :'); a=C; x=d*(a. ^n); subplot (5,1,3); stem (n,x); xlabel('time index'); ylabel('e(n)');


title ('exponential'); %program for the generation of sinusoidal sequence N=input ('enter the length of N :'); n=0: N; x=sin (2*pi/10*n); subplot (5,1,4); stem (n,x); xlabel('time index'); ylabel('r(n)'); title ('sinusoidal'); %program for the generation of ramp sequence O=input ('enter sequence length of O:'); l=0: O; x=l; subplot (5,1,5); stem (l,x); xlabel('time index'); ylabel('z(n)'); title ('ramp function');

RESULT: Given sequences are generated and plotted using MATLAB.

VIVA QUESTIONS: 1. What is the use of stem command? 2. What is the use of xlabel command? 3. What is the use of ylabel command? 4. What is the use of subplot command? 5. What is the use of title command?


2. LINEAR CONVOLUTION OF SEQUENCES


LINEAR CONVOLUTION OF SEQUENCES

AIM: Write a MATLAB program to find the linear convolution of two sequences x (n) and h (n) PROGRAM: %program for the generation of first sequence [x (n)] N=input ('enter length of the first sequence :'); n=-N: 1: N; x=input ('enter the first sequence :'); subplot (3,1,1); stem (n,x); xlabel('time index'); ylabel('x(n)'); title ('1stinputsequence'); %program for the generation of second sequence [h (n)] M=input ('enter length of the second sequence :'); k=-M: 1: M; h=input ('enter the second sequence :'); subplot (3,1,2); stem (k,h); xlabel('time index'); ylabel('h(k)'); title ('2ndinputsequence'); %program for the generation of convolved sequence [y(n)=x(n)*h(n)] p= (-N-M):1 :( M+N); y=conv(x, h); subplot (3,1,3); stem (p,y); xlabel('time index'); ylabel('y(p)'); title ('convolution'); RESULT: Linear convolution of two sequences x (n) and h (n) are determined using MATLAB.


VIVA QUESTIONS: 1. What is the use of input command? 2. What is the use of length command? 3. What is the use of ‘conv’ function? 4. What are the uses of MATLAB? 5. What are the different toolboxes in MATLAB?


3. FREQUENCY RESPONSE OF

DISCRETE-TIME SYSTEMS


FREQUENCY RESPONSE OF DISCRETE TIME SYSTEMS

AIM:

Write MATLAB program to plot the frequency response of systems. PROGRAM: 1. To plot the frequency response of the first order system y (n)-0.8y (n-1) =x (n) Clear all;

b= [1];

a= [1, -0.8];

w = - (2*pi): 0.001 :( 2*pi);

[h]=freqz (b, a, w);

subplot (2,1,1);

plot (w/pi,abs(h));

title ('frequency response in pi');

xlabel('normalised frequency');

ylabel('magnitude response');

subplot (2,1,2);

plot (w/pi,angle(h));

xlabel ('normalised frequency');

ylabel ('phase response');

RESULT: Frequency response of discrete time systems are determined and plotted using MATLAB. VIVA QUESTIONS: 1. What is the use of ‘clear all’ command? 2. What is the use of ‘freqz’ function? 3. What is the use of ‘abs’ function? 4. What is the use of ‘angle’ function? 5. What is the use of ‘grid’ command?


4. DISCRETE - TIME FOURIER TRANSFORM


DISCRETE - TIME FOURIER TRANSFORM

AIM: Write a MATLAB program to find the DTFT of the given sequence x (n) = (-0.9) n , For -10<=n<=10

PROGRAM:

n=-10:10;

x= (-0.9). ^n;

k=-200:200;

w= (pi/100)*k;

x=x*(exp (-j*(pi/100)*(n'*k)));

magx =abs(x);

angx =angle(x);

subplot (2,1,1);

plot (w/pi,magx);grid;

xlabel ('frequency in pi');

ylabel('modx');

title ('magnitude part');

subplot (2,1,2);

plot (w/pi,angx/pi);grid;

xlabel ('frequency in pi');

ylabel ('phase part');

RESULT: DTFT of the given sequence is determined and plotted using MATLAB. VIVA QUESTIONS: 1. What is the use of ‘freqspace’ function? 2. What is the use of ‘impz’ function? 3. What is the use of ‘phasez’ function? 4. What is the use of ‘stepz’ function? 5. What is the use of ‘phasedelay’function?


5. COMPUTATION OF DFT


COMPUTATION OF DFT

AIM: Write a MATLAB program to compute the DFT of the given sequence and plot the magnitude and phase response.

PROGRAM:

%DFT using FFT

Clear all;

N=input ('enter length of FFT :');

k=0: N-1;

x=input ('enter length of sequence :');

XK=fft(x, N);

magxk=abs(XK);

angxk=angle(XK);

subplot (2,1,1);

stem (k,magxk);

xlabel ('k');

ylabel ('real part of XK');

title ('magnitude part');

subplot (2,1,2);

stem (k,angxk);

xlabel ('k');

ylabel ('imaginary part of XK');

title ('phase part');

RESULT: DFT of the given sequence is determined and plotted using MATLAB.


VIVA QUESTIONS: 1. What is the use of ‘dftmtx’ function? 2. What is the use of ‘dct’ function? 3. What is the use of ‘fft’ function? 4. What is the use of ‘fft2’ function? 5. What is the use of ‘fftshift’function?


6. DESIGN OF IIR DIGITAL FILTERS


DESIGN OF BUTTERWORTH LOW PASS FILTER AIM: Write a MATLAB program to design a Butterworth low pass digital filter for the given specifications %To design a Butterworth low pass filter for the given specifications clear all;

alphap=4; % Pass band attenuation in dB

alphas=30; % Stop band attenuation in dB

fp=400; % pass band frequency in Hz

fs=800; % stop band frequency in Hz

F=2000; % Sampling frequency in Hz

omp=2*fp/F; oms=2*fs/F;

%To find cutoff frequency and order of the filter

[n,wn]=buttord(omp,oms,alphap,alphas)

% system function of the filter

[b,a]=butter (n, wn)

w=0:.01:pi;

[h,om]=freqz (b,a,w,'whole');

m=20*log10(abs(h));

an=angle(h);

subplot(2,1,1);plot(om/pi,m);grid;

ylabel('Gain in dB');

xlabel('Normalised frequency');

title('magnitude response');

subplot(2,1,2);plot (om/pi,an);grid

ylabel('Phase in radians');


title('phase response');


RESULT: Butterworth low pass digital filter is designed with the given specifications using MATLAB. VIVA QUESTION:

1. What is the use of ‘buttord’ function? 2. What is the use of ‘butter’ function? 3. What is the use of ‘freqz’ function? 4. What is the use of ‘residuez’ function? 5. What is the use of ‘ zplane’ function?


DESIGN OF BUTTERWORTH HIGH PASS FILTER

AIM: Write a MATLAB program to design a Butterworth High pass digital filter for the given specifications

%To design a Butterworth high pass filter for the given specifications

clear all;

alphap=4; %Pass band attenuation in dB

alphas=30; %Stop band attenuation in dB

fs=400; %pass band frequency in Hz

fp=800; %stop band frequency in Hz

F=2000; %Sampling frequency in Hz

omp=2*fp/F; oms=2*fs/F;

%To find cutoff frequency and order of the filter

[n,wn]=buttord(omp,oms,alphap,alphas)


[b,a]=butter(n,wn,'high')

w=0:.01:pi;

[h,om]=freqz(b,a,w);

m=20*log10(abs(h));

an=angle(h);

subplot(2,1,1);plot(om/pi,m);grid;



subplot(2,1,2);plot(om/pi,an);grid;




RESULT: Butterworth High pass digital filter is designed with the given specifications using MATLAB. VIVA QUESTIONS:

1.What is the use of ‘real’ function? 2.What is the use of ‘freqs’ function? 3.What is the use of ‘poly’ function? 4.What is the use of ‘roots’ function? 5.What is the use of ‘ ceil’ function?


DESIGN OF BUTTERWORTH BAND PASS FILTER AIM: Write a MATLAB program to design a Butterworth Band pass digital filter for the given specifications %To design a Butterworth Bandpass filter for the given specifications

clear all;

alphap=2; %Passband attenuation in dB

alphas=20; %Stopband attenuation in dB

wp=[.2*pi,.4*pi]; %passband frequency in radians

ws=[.1*pi,.5*pi]; %stopband frequency in radians

%To find cutoff freency and order of the filter

[n,wn]=buttord(wp/pi,ws/pi,alphap,alphas)


[b,a]=butter(n,wn)

w=0:.01:pi;

[h,ph]=freqz(b,a,w);

m=20*log(abs(h));

an=angle(h);

subplot(2,1,1);plot(ph/pi,m);grid;



subplot(2,1,2);plot (ph/pi,an);grid


xlabel('Normalised freuency');

RESULT: Butterworth Band pass digital filter is designed with the given specifications using MATLAB.


VIVA QUESTION:

1.What is the use of ‘fliplr’ function? 2.What is the use of ‘dfs’ function? 3.What is the use of ‘dir2cas’ function? 4.What is the use of ‘cas2dir’ function? 5.What is the use of ‘dir2par’ function?


DESIGN OF CHEBYSHEV LOW PASS FILTER

AIM: Write a MATLAB program to design a Chebyshev low pass digital filter for the given specifications %To design a chebyshev type I lowpass filter for the given specifications

clear all;



wp=.2*pi; %passband frequency in radians

ws=.3*pi; %stopband frequency in radians


[n,wn]=cheb1ord(wp/pi,ws/pi,alphap,alphas)


[b,a]=cheby1(n,alphap,wn)

w=0:.01:pi;


m=20*log(abs(h));

an=angle(h);


ylabel('Gain in dB');xlabel('Normalised frequency');

subplot(2,1,2);plot(ph/pi,an);grid

ylabel('Phase in radians');xlabel('Normalised freuency');

RESULT: chebyshev low pass digital filter is designed with the given specifications using MATLAB.


VIVA QUESTION:

1.What is the use of ‘cheb1ord’ function? 2.What is the use of ‘cheby1’ function? 3.What is the use of ‘cheby2’ function? 4.What is the use of ‘cheb2ord’ function? 5.What is the use of ‘chebiap’ function?


DESIGN OF CHEBYSHEV BAND PASS FILTER AIM: Write a MATLAB program to design a Chebyshev Band pass digital filter for the given specifications %To design a chebyshev type I band pass filter for the given

specifications

clear all;



wp=[.2*pi,.4*pi]; %passband frequency in radians

ws=[.1*pi,.5*pi]; %stopband frequency in radians


[n,wn]=buttord(wp/pi,ws/pi,alphap,alphas)


[b,a]=cheby1(n,alphap,wn)

w=0:.01:pi;


m=20*log10(abs(h));

an=angle(h);


ylabel('Gain in dB');xlabel('Normalised frequency');

subplot(2,1,2);plot(ph/pi,an);grid;

ylabel('Phase in radians');xlabel('Normalised freuency');

RESULT: chebyshev band pass digital filter is designed with the given specifications using MATLAB.


VIVA QUESTIONS:

1.What is the use of ‘cheby1(n,Rp,wn,’bandpass’)’ function? 2.What is the use of ‘cheby1(n,Rp,wn,’high’)’’ function? 3.What is the use of ‘cheby2ord’ function? 4.What is the use of ‘cheby2’ function? 5.What is the use of ‘ellipord’ function?


7. DESIGN OF FIR DIGITAL FILTERS


DESIGN OF LOW PASS FIR FILTER

AIM: Write a MATLAB program to design a Low pass FIR filter using Rectangular and Hamming windows.

%To design a 25-tap lowpass filter with cutoff frequency of 0.5pi radians using

% rectangular and Hamming windows and plot their frequency response

clear all;

wc=.5*pi;

N=25;alpha=(N-1)/2;eps=.001;

n=0:1:N-1;

hd=sin(wc*(n-alpha+eps))./(pi*(n-alpha+eps));

wr=boxcar(N);%Rectangular window sequence

hn=hd.*wr';%Filter coeffcients

w=0:.01:pi;

h=freqz(hn,1,w);

plot(w/pi,abs(h));

hold on

wh=hamming(N);%Hamming window sequence

hn=hd.*wh';%filter coefficients

w=0:.01:pi;

h=freqz(hn,1,w);

plot(w/pi,abs(h),'-.');grid;

xlabel('normalised frequency\omega/\pi');

ylabel('Magnitude');hold off

RESULT:

Low pass FIR filter is designed using Rectangular and Hamming windows in MATLAB.


VIVA QUESTIONS:

1.What is the use of ‘boxcar’ function? 2.What is the use of ‘hamming’ function? 3.What is the use of ‘hanning’ function? 4.What is the use of ‘fir1’ function? 5.What is the use of ‘fir2’ function?


DESIGN OF BAND PASS FIR FILTER

AIM: Write a MATLAB program to design a Band pass FIR filter using Rectangular and Hamming windows. %To design a 25-tap bandpass filter with cutoff frequency

%.25pi and .75pi radians using rectanglur and Hamming windows

% and plot their frequency reponse

clear all;

wc1=.25*pi;wc2=.75*pi;% Cutoff frequencies

N=25;a=(N-1)/2;

eps=.001;%To avoid indeterminate form

n=0:1:N-1;

hd=(sin(wc2*(n--a+eps))-sin(wc1*(n-a+eps)))./(pi*(n-a+eps));

wr=boxcar(N);%Rectangular window sequence

hn=hd.*wr';%Filter coeffcients

w=0:.01:pi;

h=freqz(hn,1,w);

plot(w/pi,abs(h));

hold on

wh=hamming(N);%Hamming window sequence

hn=hd.*wh';%filter coefficients

w=0:.01:pi;

h=freqz(hn,1,w);

plot(w/pi,abs(h),'-.');grid;

xlabel('normalised frequency\omega/\pi');

ylabel('Magnitude');hold off

RESULT: Band pass FIR filter is designed using Rectangular and Hamming windows in MATLAB.


VIVA QUESTIONS:

1.What is the use of ‘hold on’ function? 2.What is the use of ‘hold off’ function? 3.What is the use of ‘wvtool’ function? 4.What is the use of ‘rectwin’ function? 5.What is the use of ‘triang’ function?


1. SIMULATION OF DECODER,ENCODER,

MULTIPLEXER AND DEMULTIPLEXER


SIMULATION OF DECODER AIM: Write VHDL source code to simulate DECODER PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder4 is Port ( a : in std_logic_vector(1 downto 0); d : out std_logic_vector(3 downto 0)); end decoder4; architecture decoder4 of decoder4 is begin process (a) begin case a is when "00" => d<="0001"; when "01" => d<="0010"; when "10" => d<="0100"; when "11" => d<="1000"; when others => d<="ZZZZ"; end case; end process; end decoder4; RESULT: DECODER is simulated using VHDL source code.


SIMULATION OF ENCODER

AIM: Write VHDL source code to simulate ENCODER PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder4 is Port ( d : in std_logic_vector(3 downto 0); a : out std_logic_vector(1 downto 0)); end encoder4; architecture encoder4 of encoder4 is begin a <= "00" when d="0001" else "01" when d="0010" else "10" when d="0100" else "11" when d="1000" else “ZZ”; end encoder4; RESULT: ENCODER is simulated using VHDL source code.


SIMULATION OF MULTIPLEXER

AIM: Write VHDL source code to simulate MULTIPLEXER PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux4 is Port (i: in std_logic_vector (3 downto 0); a, b: in std_logic; y : out std_logic); end mux4; architecture Behavioral of mux4 is signal s: std_logic_vector(1 downto 0); begin s<= a & b; with s select y <= i(0) when "00", i(1) when "01", i(2) when "10", i(3) when "11", ‘X’ when others; end Behavioral; RESULT: Multiplexer is simulated using VHDL source code.


SIMULATION OF DEMULTIPLEXER

AIM : Write VHDL source code to simulate DEMULTIPLEXER PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux4 is Port (e,a,b : in std_logic; y : out std_logic_vector(3 downto 0)); end demux4; architecture demux4 of demux4 is begin process (e,a,b) begin if e='1' then if a='0' and b='0' then y<= "0001"; elsif a='0' and b='1' then y<= "0010"; elsif a='1' and b='0' then y<= "0100"; elsif a='1' and b='1' then y<= "1000"; end if; else y <="0000"; end if; end process; end demux4; RESULT: Demultiplexer is simulated using VHDL source code.


VIVA QUESTIONS: 1. What is VHDL? 2. What are the advantages of VHDL? 3. What are the applications of VHDL? 4. What is an Entity? 5. What are ports? 6. What is an Architecture body? 7. What are the differences between signal assignment and variable assignment statements? 8. What are the differences between inertial delay and transport delay? 9. What is the sensitivity list of process statement? 10. What is the difference between ‘std_logic” and ‘bit ‘type? 11. What are the different types of identifiers used in VHDL? Give examples?


2. SIMULATION OF

PARALLEL ADDER AND BCD ADDER


SIMULATION OF PARALLEL ADDER

AIM: Write VHDL source code to simulate PARALLEL ADDER PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity PAFOR is Port (a: in std_logic_vector (3 downto 0); b : in std_logic_vector(3 downto 0); cin: in std_logic; sm : out std_logic_vector (3 downto 0); cout: out std_logic); end PAFOR; architecture Behavioral of PAFOR is component FA is port (a, b, cin: in std_logic; sum, carry: out std_logic); end component; signal cy: std_logic_vector (4 downto 0); begin cy (0) <= cin; g: for k in 3 downto 0 generate g1:FA port map(a(k), b(k), cy(k), sm(k), cy(k+1)); end generate g; cout<=cy (4); end Behavioral; RESULT: PARALLELADDER is simulated using VHDL source code.


SIMULATION OF BCD ADDER

AIM: Write VHDL source code to simulate BCD ADDER. PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd_add is Port ( a,b : in std_logic_vector(3 downto 0); Cin : in std_logic; sum: out std_logic_vector(3 downto 0); cout :out std_logic); end bcd_add; architecture bcd_add of bcd_add is signal t ,t1:std_logic_vector(4 downto 0); begin t<= ‘0’ & a + b + cin; t 1<= t + “0110” when t > “01001” else t; sum <= t1(3 downto 0); cout <= t1(4); end bcd_add; RESULT: BCD ADDER is simulated using VHDL source code. VIVA QUESTIONS: 1. What are different data objects in VHDL? 2. What are different data types in VHDL? 3. What are the different logical operators in VHDL? 4. What are the different relational operators in VHDL? 5. What are the different shift operators in VHDL? 6. What are the different Adding operators in VHDL? 7. What is the use of IF statement? Give syntax for IF statement? 8. What is the use of CASE statement? Give syntax for CASE statement? 9. What is the use of LOOP statement? Give syntax for LOOP statement? 10. What is the use of ASSERT statement? Give syntax for ASSERT statement? 11. What is the use of WAIT statement? Give syntax for WAIT statement?


3. SIMULATION OF BCD TO SEVEN

SEGEMENT DECODER AND B-G & G-B

CODE CONVERTERS


SIMULATION OF BCD TO SEVEN SEGMENT DECODER

AIM: write VHDL source code to simulate BCD to SEVEN SEGMENT DECODER PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd_7seg is Port ( a, b, c, d : in std_logic; x : out std_logic_vector(6 downto 0)); end bcd_7seg; architecture bcd_7seg of bcd_7seg is begin process (a, b, c, d) variable s: std_logic_vector(3 downto 0); begin s := a& b& c& d; if (s="0000") then x<= "1111110"; elsif (s="0001") then x<= "0110000"; elsif (s="0010") then x<= "1101101"; elsif (s="0011") then x<= "1111001"; elsif (s="0100") then x<= "0110011"; elsif (s="0101") then x<= "1011011"; elsif (s<="0110") then x<= "1011111"; elsif (s="0111") then x<= "1110000"; elsif (s="1000") then x<= "1111111";


elsif (s="1001") then x<= "1110011"; else x<= "ZZZZZZZ"; end if; end process; end bcd_7seg; RESULT: BCD to SEVEN SEGMENT DECODER is simulated using VHDL source code.


SIMULATION OF BINARY TO GRAY CODE CONVERTER

AIM: Write VHDL source code to simulate BINARY TO GRAY CODE PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binarytogrey is Port (b: in std_logic_vector (3 downto 0) ; g: out std_logic_vector (3 downto 0)); end binarytogrey; architecture Behavioral of binarytogrey is begin g (3) <= b(3); g (2) <= b (3) xor b (2); g (1) <= b (2) xor b (1); g (0) <= b (1) xor b(0); end Behavioral; RESULT: BINARY TO GRAYCODE CONVERTER is simulated using VHDL source code.


SIMULATION OF GRAY TO BINARY CODE CONVERTER

AIM: Write VHDL source code to simulate GRAY TO BINARY CODE PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity greytobinary is Port (g: in std_logic_vector (3 downto 0) ; b: out std_logic_vector (3 downto 0)); end greytobinary; architecture dataflow of greytobinary is begin b (3) <=g (3); b (2) <=g (3) xor g(2); b (1) <=(g (3) xor g (2)) xor g (1); b (0) <=(g (3) xor g (2)) xor (g (1) xor g (0)); end dataflow; RESULT: GRAY TO BINARY CODE CONVERTER is simulated using VHDL source code.

VIVA QUESTIONS: 1. What is the use of NULL statement? 2. What is the difference between EXIT and NEXT statements? 3. What is the use of REPORT statement? 4. Give syntax for component declaration? 5. Where should we declare components in an Architecture body? 6. What are actuals and formals? 7. What is component instantiation? Give syntax for Component instantiation statement? 8. What is the use of Configuration statement? 9. What is a Package? 10. What is component in VHDL?


4. SIMULATION OF FLIP FLOPS


SIMULATION OF SR FLIP-FLOP AIM : Write VHDL source code to simulate SIMULATION OF SR FLIP-FLOP.

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sr_ff is Port ( s,r,p,c,clk : in std_logic; q: out std_logic; nq: out std_logic );

end sr_ff;

architecture Behavioral of sr_ff is begin process(s,r,p,c,clk) variable tq: std_logic : ='0'; begin if p='0' and c=’1’ then tq :='1'; elsif c='0' and p=’1’ then tq := '0'; elsif p='1' and c='1' then if clk ='0' and clk'event then if(s='0' and r='0') then

tq: = tq; elsif(s='0' and r='1') then tq: ='0'; elsif(s='1' and r='0') then tq: ='1'; elsif(s='1' and r='1') then tq: =’X’; end if;

end if; else null; end if; q<=tq; nq<=not tq; end process; end Behavioral; RESULT: SR FLIP-FLOP is simulated using VHDL source code.


SIMULATION OF JK FLIP FLOP

AIM: Write VHDL source code to simulate JK FLIP-FLOP PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity JKFF is Port (j, k, p, c, clk : in std_logic; q: out std_logic; nq: out std_logic ); end JKFF; architecture Behavioral of JKFF is begin process(p, c, clk, j, k) variable tq:std_logic:='0'; begin if p='1' and c='0' then tq:= '0'; elsif p='0' and c='1' then tq:= '1'; elsif p='1' and c='1' then

if(clk'event and clk='0') then if(j='0' and k='0') then tq: =tq; elsif(j='0' and k='1') then tq: ='0'; elsif(j='1' and k='0') then tq: ='1'; elsif(j='1' and k='1') then tq: =not tq; end if;

end if; q<=tq; nq<=not tq; end process; end Behavioral; RESULT: JK FLIP- FLOP is simulated using VHDL source code.


SIMULATION OF D FLIP-FLOP

AIM : Write VHDL source code to simulate D FLIP-FLOP. PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity d_ff is Port ( d, p, c, clk : in std_logic; q : out std_logic; nq : out std_logic); end d_ff; architecture d_ff of d_ff is begin process (p, d, c, clk) variable tq: std_logic : ='0'; begin if p='1' and c='0' then tq:= '0'; elsif p='0' and c='1' then tq:= '1'; elsif p='1' and c='1' then if clk ='0' and clk'event then tq:= d; end if; else null;

end if; q<=tq; nq<=not tq;

end process; end d_ff; RESULT: D FLIP-FLOP is simulated using VHDL source code.


SIMULATION OF T FLIP-FLOP

AIM: Write VHDL source code to simulate JK Flip-Flop PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity t_ff is Port ( t, p, c, clk : in std_logic; q: out std_logic; nq :out std_logic); end t_ff; architecture Behavioral of t_ff is begin process (t, p, c, clk) variable s1: std_logic : ='0'; begin if p='1' and c='0' then s1:= '0'; elsif p='0' and c='1' then s1:= '1'; elsif p='1' and c='1' then if clk ='0' and clk'event then if(t='0') then

s1:=s1; elsif(t='1') then s1:=not s1; end if;

end if; else null; end if; q<=s1; nq<=not s1; end process; end Behavioral; RESULT: T Flip-Flop is simulated using VHDL Source code.


VIVA QUESTIONS: 1. Give the syntax for WAIT ON STATEMENT? 2. Give the syntax for WAIT UNTIL STATEMENT? 3. Give the syntax for WAIT FOR STATEMENT? 4. Where should we declare variables in the Process statement? 5. What is the use of Generate statement?


5. SIMULATION OF SYNCHRONOUS UP/DOWN

AND BCD COUNTERS


SIMULATION OF SYNCHRONOUS UP/DOWN COUNTER

AIM: Write VHDL source code to simulate Synchronous up/down counter

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity updnsyn is Port (clk,m : in std_logic; q : out std_logic_vector(2 downto 0); nq : out std_logic_vector(2 downto 0)); end updn_syn; architecture updn_syn of updn_syn is begin process(m,clk) variable tq: std_logic_vector(2 downto 0):=”000”; begin if clk ='0' and clk'event then if m=’0’ then tq:= tq + 1; elsif m= ‘1’ then tq := tq – 1; endif; end if; q<= tq; nq<= not tq; end process; end updn_syn;

RESULT: Synchronous up/down counter is simulated using VHDL Source code.


SIMULATION OF SYNCHRONOUS BCD COUNTER AIM : Write VHDL source code to simulate SYNCHRONOUS BCD COUNTER. PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd_syn is Port ( clk : in std_logic; q : out std_logic_vector(3 downto 0); nq : out std_logic_vector(3 downto 0)); end bcd_syn; architecture bcd_syn of bcd_syn is begin process(clk) variable tq: std_logic_vector(2 downto 0):=”0000”; begin if clk ='0' and clk'event then if tq < “1010” then tq:= tq + 1; else tq := “0000”; endif; end if; q<= tq; nq<= not tq; end process; end bcd_syn;

RESULT: SYNCHRONOUS BCD COUNTER is simulated using VHDL source code. VIVA QUESTIONS: 1.What are the differences between signals and variables? 2.How do you declare a constant in VHDL? 3.Simulate the function f=∑(1,3,5,7) in dataflow model 4.Simulate the function f=∑(1,3,5,7) in behavioral model 5.Simulate the function f=∑(1,3,5,7) in structural model


6. SIMULATION OF SHIFT REGISTERS


SIMULATION OF BIDIRECTIONAL SHIFT REGISTER AIM: Write VHDL source code to simulate BIDIRECTIONAL SHIFT REGISTER PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity shrg is Port ( x, m, clk : in std_logic; q : out std_logic_vector(3 downto 0); nq : out std_logic_vector(3 downto 0)); end shrg; architecture br_design of shrg is begin process variable tq : std_logic_vector(3 downto 0):=”0000”; begin if clk=’0’ and clk’event then if m=’1’ then tq(3):= x; tq(2):= tq(3); tq(1):= tq(2); tq(0):= tq(1); else tq(0):= x; tq(1):= tq(0); tq(2):= tq(1); tq(3):= tq(2); end if; end if; q<= tq; nq<= not tq; end process; end br_design; RESULT: BIDIRECTIONAL SHIFT REGISTER is simulated using VHDL source code.


SIMULATION OF BARREL SHIFTER AIM: Write VHDL source code to simulate BARREL SHIFT REGISTER PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity brlshr is generic(n:positive:=8); Port ( data : in std_logic_vector(n-1 downto 0); s : in integer range 0 to n-1; Barr_out : out std_logic_vector(n-1 downto 0) ); end brlshr; architecture Behavioral of brlshr is begin process(data,s) variable temp:std_logic_vector(n-1 downto 0); begin temp:= data; for i in 1 to s loop temp:=temp(n-2 downto 0) & temp( n-1); end loop; barr_out<= temp; end process; end Behavioral;

RESULT: BARREL SHIFT REGISTER is simulated using VHDL source code. VIVA QUESTIONS: 1. Give the syntax for GENERATE statement. 2. RTL stands for? 3. what are the differences among IN, OUT and INOUT types 4. Give syntax for ‘with select’ statement. 5. Give syntax for ‘when else’ statement.


7. FSM IMPLEMENTATION OF GRAY CODE

COUNTER AND SEQUENCE DETECTOR


SIMULATION OF FSM GRAY CODE COUNTER

AIM : Write VHDL source code to simulate FSM GRAY CODE COUNTER PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsmgray is Port ( ck : in std_logic; q : out std_logic_vector(2 downto 0):=”000”); end fsmgray; architecture Behavioral of fsmgray is type state_type is (s0,s1,s2,s3,s4,s5,s6,s7); signal state :state_type; begin process(ck) begin if ck='0' and ck'event then case state is when s0 => state<= s1; q<= "001"; when s1 => state<= s2; q<= "011"; when s2 => state<= s3; q<="010";

when s3 => state<= s4; q<= "110"; when s4 => state<= s5; q<= "111"; when s5 => state<= s6; q<= "101"; when s6 => state<= s7; q<= "100"; when s7 => state<= s0; q<= "000"; end case; end if; end process; end Behavioral;

RESULT: FSM GRAY CODE COUNTER is simulated using VHDL source code.


SIMULATION OF FSM SEQUENCE DETECTOR


AIM : Write VHDL source code to simulate FSM SEQUENCE DETECTOR PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsmdet is Port ( x,ck,resetn : in std_logic; q : out std_logic); end fsmdet; architecture Behavioral of fsmdet is type state_type is (A,B,C); signal y:state_type; begin process(ck,resetn,x) begin if resetn= '0' then y<= A; elsif ck= '0' and ck'event then case y is when A => if x='0' then y<= A; else y<=B; end if ; when B => if x='0' then y<= A; else y<= C; end if ; when C => if x='0' then y<= A; else y<= C; end if ; end case; end if; end process; q<= ‘1’ when y= C and x=’1’ else ‘0’; end behavioral;

RESULT: FSM SEQUENCE DETECTOR is simulated using VHDL source code.

sir c.r.reddy college of engineering eluru-534007 ... · digital signal processing lab manual (ec -...

Documents