Small Budget, Project Based, VLSI Design Teaching Method

A. Pavasović, J. Popović

Abstract – An introductory VLSI university-level course

encompassing all levels of IC design is described. The course is strongly project based, and is achievable even on universities with very limited resources. We describe where and how to get the needed software tools, and how to manage the projects from year to year. A detailed description of one of the projects is also given.

I. INTRODUCTION

There are many nicely planned and carried out project based courses on universities with large resources, mostly in USA, EU, Australia and Canada. On the other hand, the majority of world's universities have to deal with the problem of lack of resources, both for computer and lab equipment which is inadequate in quantity and quality, and for financing the work of their professors and teaching assistants. As a result, practically all the courses on those universities are either purely theoretical, or with very small projects, not giving the engineering student any applied experience before graduation.

The work described here is a part of our effort to restructure the entire electrical engineering curriculum so that it allows the integration of our faculty into the European family of higher education (Bologna declaration). We aim to develop undergraduate and graduate programs for electronic engineers by adapting the content, structure and methodologies, which will give students the possibility of getting the diploma in less time, while gaining more practical knowledge.

The work described deals with restructuring of an introductory VLSI course, and is a “pilot” work in our quest to introduce new teaching methodologies, with heavy emphasis on practical training of the students, and obligatory projects in all advanced courses.

II. BACKGROUND

There is a myriad of problems facing the faculties and faculty staff at the universities in Serbia, most of them shared by the majority of world universities. These problems restrict the ways in which a design course can be taught. We will mention some of them here, together with

some thoughts on how to solve them or go around them: 1. The lack of equipment (lab equipment, computers and

software), and the lack of space. With the continuous lack of money facing most faculties, this problem is getting worse instead of better in both hardware and software. The hardware problem intensifies since the existing equipment is getting outdated or broken without any means to replace it. By leaving the unlawfull software use era, many universities are left practicaly without any software. Thus, any design course at faculties such as ours has to be restricted to PCs (solving both the space problem by enabling students to work at home, and the problem of inability of universities to acquire expensive work-stations), and the design software packages have to be free or inexpensively obtained for university purposes.

2. Overload of professors, and even more, teaching assistants. This overload is due to a large number of teaching hours per week per teacher and to a very large student/teacher ratio. Additionally, the teaching staff is very poorly paid, so that most have to take additional jobs and so have even less time to develop new teaching materials. Thus, the courses have to be implemented in such a way that the load presented to the teaching assistants and teachers is minimized.

3. Students are not required to come to lectures, can take exams at any time, even years after they took the course, and are concentrated only on passing exams (getting their diploma), and not on how much they learn in the process. Thus, there should be no repetition of projects in order to ensure that each student does his/her own work. Since restrictive policies are to be avoided, positive motivation should be employed in order to make the whole class do the projects at the same time.

4. The procedure for changing anything in the curriculum is complicated, while there are very few or no elective courses in the existing curriculum. Same as for the previous points, this is something everybody in the academia should work toward changing. In the meantime, the only solution we found is working within the already approved courses.

III. VLSI COURSE IMPLEMENTATION

There are two VLSI design courses in our curriculum, one was based on high, the other on low level design. We restructured the courses such that the first one

A. Pavasovic, and J. Popovic are with the Department ofElectronics, Faculty of Electrical Engineering, University ofBelgrade, Bulevar kralja Aleksandra 73, 11000 Belgrade,Serbia & Montenegro, E-mail: apavasovic@etf.bg.ac.yu

encompasses all levels of VLSI design, giving students the sense and experience through project work of the complete IC design flow, and enabling them to do complex design projects independently in the second course.

A. Scope of the course

We decided to enable students to go through the whole IC design cycle, from architecture level to the mask level, with the exception of silicon compiling and testing fabricated ICs.

First, why the exclusions? Although the students could learn a lot by compiling their projects and comparing the results with their full-custom implementations, we decided to skip this step because we could not find any silicon compiling software that was at the same time good enough and free. Additionally, it is planned that the students will do more VHDL programming in the course based on FPGAs, and there they will go all way through the synthesis and testing.

The testing was omitted since fabricating ICs is above the means of our university, as well as obtaining the equipment necessary for testing. Additionally, there is no time to fit the design, fabrication and testing into one semester course.

Another question to be argued is why include mask level design in an introductory course. Many professors claim that mask level design is only for those few students interested in microelectronics, and that most VLSI courses, especially introductory ones, should be based solely on high-level design. Contrary to that opinion, it is our belief that it is difficult today, and will be practically impossible in the future to design systems without understanding the transistor and interconnect level. The digital design is becoming progressively more difficult, and digital engineers are less well equipped to face the problems encountered in high speed design than they were 30 years ago, since most of them have very little knowledge of analog electronics and magnetics, resulting in failing of many high-speed design projects [1]. By including mask level design and SPICE simulation of obtained cells, as well as IRSIM simulation of the whole project, the students are given the opportunity at least to see the difference between the intended and real circuit operation.

B. Organization of the course

The students work in groups of two, thus making the project progress faster, and also getting them used to team work. Team work is almost nonexistent in education systems such as ours, and we think it is very important.

The work on the project starts with the stage of literature search, mostly through the web1. In this faze, the students are guided by the course teacher. The choice of

1 A byproduct of this step is that we introduce the student to IEEE publications.

architecture follows, and after that the groups do the high level design of their project using VHDL. Since the projects are relatively large and would require more time to complete than the available time in the curriculum, the students write just a portion of VHDL code. They are supplied with the rest of the code (see subsection C), so that they can simulate the whole system, not just the small part they designed2.

After finishing the high-level design and simulation of the system, the students go to low-level design of the part of the system they already wrote the description for in VHDL. The layout is done in Magic, simulations of designed cells in Spice, and simulations of the whole design in IRSIM.

In order to ensure that students not only learn how to design, but also learn how to present their work, each group has to write a formal report/documentation on their project, as well as prepare and give a short presentation of their project. A lot of emphasis is placed on this part of the project, since the authors feel that our engineering students are not prepared at all for this part of their future engineering jobs.

C. Preparation and Organization of the Projects

The introduction of this methodology was started in the 2002/3 school year, by adapting a project “Huffman decoder” [2], developed during several years and Stanford, USA (see Acknowledgements). The only adaptation of the project to our syllabus was using VHDL instead of Verilog for high level design and verification.

The plan is that, for the following years, the best students of each class prepare the project for the next year, guided by the teacher of the course. In that way we solved the problem of excessive teachers’ time needed for preparation of big student projects. Several students can be found in each class who are enthusiastic enough to do more work than required for passing the course, at the same time obviously learning much more, not only in the course subject, but also in organizing, preparing teaching materials, and teaching itself. Since these students are usually the top students of their class, many of them will end up in academia, and this is a good way to begin preparing them for that carrier (a useful byproduct of the proposed idea).

Depending on the size of the project, we form a group of two to four students for the project preparation. This group then goes through the whole project, thus testing the difficulty of the project, time needed for completion, and preparing the instructions for the project implementation. After the successful simulation both on high and on circuit level, the decision is made on which

2 Obviously, in order for this to work for some projects, the literature search described previously is guided so that they come up with the architecture we have already chosen in advance

part of the project will the next year’s class design in detail. That part is taken out both from VHDL and Magic designs. Test vectors are prepared for testing the projects after their submission. Finally, detailed project instruction sheets are written by the student group.

During the next year’s semester, the students of this group help and guide the other students through the realization of their projects, including software installation. Usually they are symbolically paid for such work.

In order for our idea to work, we had to solve an additional locally specific problem: how to force the students to do their projects on time, i.e. during the semester when the lectures are held (otherwise, there would be no way of helping them through the project, and the whole idea would fall on the fact that one or two groups would do the project as intended, and the rest will just use their results). We succeeded in doing it by having the first exam after the semester much easier than the exams during the rest of the year, and having a fixed deadline for the submission of project reports at the beginning of the next semester3.

D. Tools

One version of VHDL (BlueHDL) can be downloaded from [3]. BlueHDL VHDL is a complete VHDL simulation tool suite including a VHDL compiler and a simulation engine. Also free for downloading is Electric [4]. Electric has a built-in gate-level simulator called ALS (the Asynchronous Logic Simulator) that can simulate VHDL descriptions (it can also simulate schematics and IC layout).

Magic is a well-known VLSI layout system developed at the University of California, Berkley in the eighties and used intensively in VLSI courses at United States universities in the last twenty years. It was made available to universities outside the United States in the nineties. Only in the last several years non-Unix versions become available, through a big effort from enthusiasts from Johns Hopkins, Stanford, Cornell, and Caltech, making Magic accessible to universities in countries which can not afford expensive workstations for teaching. Both Linux and Windows versions of Magic can be downloaded freely [5]. Our students usually use Windows versions. In that case, an X server (X Window System display server) must be installed in order for Magic to work. X server can be downloaded from [6] and is installed easily. Our experience with Magic under Windows is good, once the installation problems are surpassed. The biggest problems our students encountered is configuring the necessary ‘magic.bat’ file in order for the system to work (the contents of this file are very dependant on the PC operating system), and setting the colors in Magic. Since Magic has a

3 The students that do not hand in their reports by that deadline, loose the right to hand it in at all, and have to wait for the next round of projects.

very good tutorial and reference manuals, once it is installed, the students usually do not have any problems using it. The technology files for the processes supported by MOSIS can be found on [7].

The performance check of designed circuits is done by both analog and switch simulators. Spice is used for simulating basic cells. The functionality of the whole design, as well as timing and dissipation characteristics, is done using IRSIM. IRSIM is a switch-level simulator distributed freely along with Magic, and installed at the same time as Magic. In order to use IRSIM, parametric files (*.prm) for the specific process are needed. Parametric files are text files, and, in the unlikely event that the file for the used technology cannot be found on the web, they can be easily generated using the technology data found on the manufacturer’s website.

IRSIM is simple to use and can be invoked directly from Magic with the command ‘:rsim TechName.prm PrName.sim’. After this command, the switching back to Magic is done by typing a period, and back to IRSIM by command ‘:rsim’. Before starting IRSIM, the designed cells in Magic have to be converted to the proper format, i.e. their parameters extracted, which is done with the ‘:extract all’ command (which extracts the parameters of the whole hierarchy bellow the edited cell), and then converting these extracted parameters into IRSIM format by using the command ‘:ext2sim –L –R –c 20 PrName.ext’. Although the simulation can be performed by typing the IRSIM commands directly, it is strongly suggested that students prepare the simulation command sequence in advance in a *.cmd file.

E. Description of one of the Projects

Figure 1. Block diagram of an 8-bit adder (32-bit adder is essentially the same)

Here we will describe the next semester project: the implementation of an arithmetic logic unit. This project was chosen since ALU represents an essential part of any microprocessor, and the students have extensive knowledge of its operation. The complete project was prepared by the

best students of this year's VLSI design class. After the project was finished and tested, we decided to limit the project for the next semester’s course to the most critical part of the ALU: the adder. The adder part was removed from both VHDL and layout design, and the rest of the design will be given to the students.

The design of a 32-bit adder will be in a 250 nm CMOS technology (TSMC25, λ = 150 nm, see [8]), and the students will either design for maximum speed, minimum dissipation or a justified compromise of the two. It is suggested to the students to choose, by searching the open literature, for the best adder realization. An illustrative example is given to them in the form of one

implementation (Figure 1) of a Carry Lookahead Adder [9]. 32-bit adder has 32 C blocks and (16+8+4+2+1+1) D blocks, the last D block being somewhat different than the rest, since it has no output signals.

The organization of the adder is hierarchical. Although many today’s adders don’t use standard CMOS logic for implementation of the logic functions, it was decided to allow students to design the adder using standard CMOS logic, in order to make the IRSIM simulations easier. If realized in this way, the area of the adder is approximately 0.1 mm2, with around 2400 transistors. Sample cell and adder layouts are shown on Figure 2.

a. b.

Figure 2. a. “C” cell layout (two cells), b. 32-bit adder layout [10]

IV. CONCLUSION

The proposed changes of the VLSI design course were warmly welcomed by the students, as they realized that it gives them a better quality of education, with much greater practical experience through project work. Especially satisfied were the students who continued with the advanced VLSI course, since they are now able to do very complicated projects in that course. Our efforts were also recognized by the European Commition, which approved our TEMPUS project proposal [11] based on the idea presented in this paper, and which will enable a much wider implementation of our curriculum change ideas.

ACKNOWLEDGEMENTS

The authors would like to thank Prof. Paul Horowitz from Stanford for giving us permission to use their project “Huffman decoder”, and Vladimir Stojanovic, also from Stanford, for his help in implementing that project at ETF.

REFERENCES

[1] H. Johnson, “Why Johnny Can’t Design a High-Speed Digital System”, DesignCon, Santa Clara, CA, 2003

[2] P. Horowitz, “EE271: Intro to VLSI Design Project Instructions”, Stanford Un., Autumn Quarter 01/02.

[3] http://www.bluepc.com/download.html#vhdlwin [4] http://www.staticfreesoft.com/manual/index.html [5] http://vlsi.cornell.edu/magic/ [6] http://www.cygwin.com/xfree/ [7] http://bach.ece.jhu.edu/~tim/programs/magic/tech.html [8] http://www.mosis.org/products/fab/vendors/ [9] F.-C. Cheng, S.H. Unger, M. Theobald, and W.-C. Cho.

”Delay-Insensitive Carry-Lookahead Adders”, International Conf. on VLSI Design, January 1997.

[10] P. Marković, L. Karbunar, P. Stevanović, P. Protić, “VLSI Design Final project report”, Un. of Belgrade, Faculty of Electrical Engineering, 2003. (in Serbian)

[11] Tempus CARDS Joint European Project JEP 17028, http://www.tempusscg.net/year2002.htm