Appendix A - 1

APPENDIX A SMD AND MULTI-LAYERED PAD Creating SMD Pad and Multi-Layered Pad are generally the same as the pads that you create in Lab 3 with only a slight difference in layer assignment. Multi-Layered Pad 1 Invoke the Library Manager and open the Melody.lmc Library. 2 Click on the Padstack Editor. 3 In the Pads Tab, create a 4 Web Round Thermal as follows.

4 The Thermal Pad is used for Relief Connection in a Plane. 5 When creating a Thermal Pad you should determine the size of your WebClear (Air-Gap) first,

usually 10 th (mils) would have been sufficed.

Appendix A - 2

6 The width of the Relief Connection should be also wide enough to carry the Current draw by the circuit, without compensating heat losses during soldering.

7 The Hole to be used for this Padstack should be smaller than the inner section of the Pad, without

touching the Air-Gap. 8 This will ensure proper plating on the Through Hole Pads and Vias. 9 Create a Round 50 Pad, which will be used for Mount side, Internal and Opposite side. 10 Another Round 65 Pad, for the Solder Mask and the Anti-Pad on the Planes. 11 Return to Padstack Tab, and create a new Padstack M R50 X H32. 12 Assign the Pads as below and use Rnd 32+/- Tol 3 for the Hole.

13 Use the preview window to see the relationship between the Layers and the Hole.

Appendix A - 3

SMD Pads 14 Create two Rectangle Pads Rectangle 60x50 and Rectangle 70x60 in the Pads Tab.

15 Select Type as Pin – SMD, and assign the Pads as below.

16 SMD Component does not have leaded pins, therefore the Hole, Internal Layers, Plane Clearance

and Thermal are ignore. 17 The Solder Paste Mask uses the same Pad size as the Top and Bottom Mount. 18 Save the file and Exit.

Appendix A - 4

APPENDIX B MELODY GENERATOR FOOTPRINT DATA Following the creation of the Cell Database in Lab 4 create the rest of the cells as listed below. Melody Generator Footprint 1 Create the cell DPST_SW with this Wizard, by assigning the data as below.

DPST_SW 2 When you have placed it on the Cell Editor, click the Draw Mode Button to add a Text

property to the Cell.

Appendix A - 5

3 Change the Line Width of the Silkscreen to 10. 4 Similarly generate a cell for the Transistor Footprint TR09 with Text C, B and E to Pins 1, 2 and 3

respectively.

TR09 5 For the Connector CONN, add a 5V Text for Pin 1 and GND for Pin 2. CONN

Appendix A - 6

6 The Resistor Package uses the Through Discrete Wizard, and the name of the Footprint RES04

indicates a 0.4 inch Pitch.

RES04 7 For the Radial Package of the Electrolytic Capacitor, remove the tick for the Silkscreen Outline

when entering the specification. RAD02-03

Appendix A - 7

8 Draw the Silkscreen with the Add Circle Button with a diameter of 300 mils. 9 Draw a Cross beside Pin 1 to indicate the Positive Polarity of the Pin.

10 The Name of the Footprint RAD02-03 constitutes the Type RAD as Radial, Pitch of 0.2 inch and

Diameter of 0.3 inch. 11 Repeat the steps for Footprint RAD01-02.

Appendix A - 8

RAD01-02

12 Create the rest of the two components for SPDT_SW_G and CK05. SPDT_SW_G

Appendix A - 9

CK05

VeriBest Mouse Control Quick Reference

PAN VIEW

Press and hold + move mouse

ZOOM IN

Single click

Appendix A - 10

ZOOM OUT

Hold SHIFT + single click

SELECT ITEM

Single click on item

SELECT MULTIPLE ITEM

Press and hold + move mouse diagonally

SELECT MULTIPLE ITEM INDIVIDUALLY

Hold SHIFT + Single click on items

Appendix A - 11

TOGGLE SELECTION

Hold CTRL + Single click on items

MOVE SELECTED ITEM

Press and hold + move mouse

UNSELECT ITEM

Single click elsewhere

DISPLAY PROPERTY DIALOG

Appendix A - 12

Double click on item

DISPLAY ACTION MENU

Single click

LAB 1 CREATING SYMBOLS Objectives: Create Library Partitions in the Library Manager. Create Symbols for a Project and store them in their respective Libraries Use Cut and Paste command for creating similar symbols. Creating Symbols with multiple parts in a package. Library Manager 1 Invoke the Library Manager by clicking on

Start > Program > VeriBest VB99 > VeriBest Library Manager > Library Manager.

Appendix A - 13

2 The Library Manager Panel will appear as follow.

3 Click on File – New … . 4 Select your working drive and create a New Folder and rename it Melody.

Appendix A - 14

5 Double-click the Melody folder and click OK. 6 You will see that in the Melody folder, there is a file Melody.lmc that is automatically created for you. 7 The Melody.lmc file is the Library Manager file that will contain all the necessary information

between the Padstacks, Symbols, Cells and the Pin Mapping Information. 8 Click File – Open, you will see that a series of folders that are used to store these data created

automatically in the Melody folder.

9 Click Cancel to close. 10 Click Edit – Partition Editor … to create a new Library Partition. 11 This Library Partition stores all your Symbol and Cell Library data in the Melody.lmc file. Partition Editor 12 In this section of the exercise, we will Partition the libraries in accordance to Part Types.

Appendix A - 15

13 Click on the New Partition, and create the symbols for Transistors, Resistors, Capacitors, ICs, and

MISC.

14 You should have all the libraries as follows, use the button if you need to delete a

partition.

15 All Entries should be 0, as they are still empty. 16 Click on the Cells tab and create a Melody partition. 17 Click OK to exit. 18 Click on the Symbols button from the Library Manager Panel to launch the VBDC Symbol Editor.

Appendix A - 16

19 Go to File – Open, and click the button to select the Resistors Partition and OK.

20 The Resistor Symbol Library, Resistors.slb is automatically created. 21 Select and enter RES for Symbol name and Discrete Passive for Symbol type. 22 The Place tool box contains the basic tools that are needed to create your symbols.

Select Pin Text Arc Circle Rectangle Line

23 Use the Line tool to draw the symbol of the resistor with one end attached to the Symbol Origin.

Symbol Origin 24 You can double-click on anywhere in the workspace to get the Properties menu.

25 You can change the Grid spacing to fine tune the Symbol, but always maintain the end points of the

Symbol Pins on the Grid of 0.10.

Appendix A - 17

26 After you have created the Resistor Symbol, set the Grid spacing back to 0.10. 27 Click the Pin tool to extract a Symbol Pin. 28 Use the right mouse button to get to the Properties Menu. 29 Change the Pin Type to Any, in the General tab. 30 Under the Text tab, add in Type column, Pin Name and name it 1.

31 Do the same thing for pin 2. 32 Double-click on the workspace to get the Properties menu. 33 Under the Text tab, enter the Properties as below.

34 Adjust the Pin Name and Part Name positions. 35 You should see the components that you have created as follows.

Appendix A - 18

Pin Name Part Name

Pin 36 Double-click the Pin Name and Part Name and remove the tick on Visible. 37 Save your file, but do not close the RES window yet. Copy Symbol 38 For the next symbol, we are going to use the existing RES Symbol and modify it to a TRIMMER

Symbol. 39 Click on again to create a new component in the Resistor.slb. 40 Enter in the Symbol name: TRIMMER. 41 Use Ctrl – A keys, to select all the items that you have previously created in the RES window. 42 The Resistor Symbol you have created turns white in the selected mode. 43 Hit Ctrl – C to Copy the Symbol. 44 Move to the TRIMMER Symbol window and hit Ctrl – V to Paste the Symbol. 45 Move to the Symbol Origin and place the end with Pin 1 on the Origin. 46 Draw an arrow on to the Resistor, add a new Pin on the Symbol. 47 Double click the Pins and change the Pin Names as below.

48 Double click the Part Name: RES to enter the Properties Menu.

Appendix A - 19

49 Change the Part Name as follows.

50 Save and Close the Resistor.slb 51 Continue creating the rest of the components in their respective libraries as below. Capacitors.slb

ICs.slb

MISC.slb

Transistors.slb

Source.slb

Note that the Symbols VCC and GND have only one pin each, and each pin has the extra property of Net Name VCC and GND

52 Once finish, check all the Symbols for Ref Designator, Part Number and Part Name to be present. 53 Save your files.

Appendix A - 20

Multiple Parts in a Package 54 For the continuing exercise, you will be creating the AND Gate which is usually packaged with 4 parts

in a single DIP14 Cell. 55 Go to File – Open, and click the button to select the ICs Partition and OK. 56 Use the Place tools to draw the AND Gate Symbol. 57 The Pin Names are A and B for Input, and Y for Output.

58 A Pin Sequence property is added to each pin as follows, 1 for A, 2 for B and 3 for Y to ensure correct

Gate Mapping.

59 Enter the Part Name as AND. 60 Save the file and Exit.

Appendix A - 21

LAB 2 CREATING PCB TEMPLATE Objectives: To understand the structure of multiple layered PCB. Defining the layers used for design. Layer Structure of a Printed Circuit Board

The picture above displays a cross-section of a typical 6 layer PCB. The PCB material used is Fiberglass (FR4), which is coated with copper on both sides. The two Inner Layers PCBs are processed and etched first. A layer of resin material (Pre-preg) is used to separate the conductive layers. The Top and Bottom sides are coated with pre-preg and thin copper foils are placed on both the outer layers. The final assembly of the layers is ‘hot-pressed’ with a machine. The pre-preg melts and glues all the layers together. The 6 layer board is drilled and the holes are plated. Finally, the Top and Bottom layers are imaged and etched. In a 6 layer PCB, you will see the Top and Bottom layers on the outside. Typically both sides are etched

Appendix A - 22

with copper print which is used to interconnect the components. You will also see the outer layers coated with the green Solder Resist. It used to prevent the copper from oxidizing when it is exposed to air for a long period of time. The Solder Mask Openings expose only the Pads for component soldering, thus preventing the solder from flooding the copper prints other than the soldering pads. Mid Layers 1 and 2 are extra layers used for connections should there be a lack of space to Route the traces on the Top and Bottom Layers. To change layer when routing, a Via is introduced to connect the traces to another layer. The Via has plating on the wall of the hole to maintain conductivity between layers.

The two internal planes 1 and 2 are usually used for Power and Ground connections, which mainly consist of a whole copper plane with relief pattern and plane clearance etched away. Blind Via resides on the Top or Bottom Layers connecting to the immediate adjacent layer. They do not go through all the layers like Through Hole Via. Similarly Buried Via are vias that are sandwiched in between the external PCBs. Layout Template 1 Invoke the Layout Template.

Appendix A - 23

2 Select the 4 Layer Template and click Copy Template. 3 A copy of 4 Layer Template_1 appears. 4 Change the Name to 2 Layer Template. 5 Click on Edit Template. 6 This will launch the VeriBest PCB. 7 Once you are in the PCB environment, go to Setup – Setup Parameter.

8 Change the Number of physical layers to 2. 9 Hit the Remap Layers.. button, this will change the layers from 4 to 2.

10 Click OK to apply the changes.

Appendix A - 24

11 Click Edit > Place > Board Outline and draw the 3000 X 2200 (3 X 2.2 inches) outline of your PCB board with the Add Rectangle button at the bottom.

12 Click Edit > Place > Route Border, draw the outline 50 mils offset from the Board Outline and 400

mils off the corners.

13 Click on File – Save and Exit.

Appendix A - 25

LAB 3 CREATING PADSTACKS Objectives: To understand the structure of padstacks in a multiple layer PCB. Defining the layers used for defining a pad and a hole. Create Padstacks for use in Cell creation in the Library Manager. Layer Structure of a Padstack The layer structure of a Padstack, as you have learn in Lab 2 consist of the Top and Bottom Layers, Mid (Internal) Layers, Planes, Clearances and Reliefs, and Top and Bottom Masks.

The figure above shows the structure of a Padstack and the layers involved. Solder Mask - A green layer of Solder Resist is coated on the external layers of a PCB to prevent

the copper from oxidizing when exposed to air for a long period of time. The Solder Mask is the opening that exposes the Pad for Soldering, preventing the solder from flooding the adjoining copper.

Pad - Through Hole Pad has large hole and is used for mounting and soldering Leaded

Components to the board. Via pad is usually smaller as it is only used for inter-layer connection. Surface Mount Devices, the pad does not have a hole in it.

Solder Paste Mask - Solder Paste are used only on Surface Mount Devices, the paste is made up of tin

and silver alloy which is printed on Component Pads by pressing it over the Solder Paste Mask. It melts into liquid form when passing through a Reflow Machine and

solidifies as it cools attaching the pins of the component on to the pads.

Appendix A - 26

Plated Through - The Plated Through Hole is used for inter-layer connections, linking the electrical Hole signals from one layer to another by plating the walls of the hole with metallic alloy.

The Through Hole Pads and Vias in multiple layer designs have plated through holes. The plating also serves to improve mounting strength for Leaded Component.

Relief Connection - To prevent the heat from leaking too fast from the pad to the plane, creating Cold

Joints, Air Gaps are introduced. The resulting Relief Connections are used for connecting the copper plane to the pad or via having the same Net.

Plane Clearance - As a Plane is almost all copper, any Via or Through Hole Pad introduced that

belongs to a different Net will certainly be shorted to it. To prevent this, an Anti-Pad or a cut out must be made to allow clearance for the hole to go through without touching any part of the Plane.

Padstack Editor 19 Invoke the Padstack Editor.

20 You will see the four main Tabs, they are Padstacks, Pads, Holes and Custom Pads & Drill Symbols. 21 The Padstacks are the assembly of the Pads and Holes, therefore you need to define all the geometry

you need before creating the Padstacks. 22 For Example, click on the 026VIA.

Appendix A - 27

23 You will see the on the Preview screen, a hole size of 19 mils with a positive tolerance of 0 and a negative tolerance of 3 indicated as Rnd 19 +Tol 0 - Tol 3.

24 Hold on to the Ctrl Key and click on the Pads on the Mount side and the Mount side solder mask. 25 You can preview your Padstack as something like this.

26 In this case, the Mount side is the Top Layer where the components are mounted on. 27 In this exercise, you will learn to create the padstack for a double layer design, and we will dispense the

other layers that are not involved in this design. 28 Click on the Pads Tab, select the type as the Round Donut first and enter as follows.

29 Notice that the name of the Pad Donut Rnd 75 WebClear 23 has been entered automatically for you.

Appendix A - 28

30 Click on the New button, and create a few more pads with the following specification:

Donut Rnd 100 WebClear 34 Donut Rnd 125 WebClear 45

31 The unit used now is in English (Inches) and the th (mil) unit is a thousandth (1/1000) of an inch. 32 To change unit you can select Metric (Millimeter), VeriBest will be able to keep track of both units. 33 You can use the Filter to sort the pads and holes by types, and by units too. 34 Click on the Holes Tab, select the type as Drilled and enter as follows.

35 Create another hole for Rnd 32 +/-Tol 3. 36 The Drill symbol assignment allows you to visually define the location of the hole and the size of the

drill bit used during output of Gerber Files (Artwork Data). 37 The default will generate a letter for each hole size, in this case, A for 40 mils and B for 32 mils. 38 You can also attach a Drill symbol to your hole by selecting Use drill symbol from list. 39 However, do not use the same symbol for a different hole size.

Appendix A - 29

40 Return to Padstack Tab. 41 Click on the New button, and enter the name of the Padstack as R100 X H40. 42 Select from Hole Rnd 40 +/- Tol 3 and Pad Donut Rnd 100 WebClear 34. 43 Then select from the Available pads: column Mount side, Internal and Opposite side by holding on

to the Shift key. 44 Hit to assign the pads to these layers.

45 Continue to create the following Padstacks:

Name Pads Hole R75 X H40 Donut Rnd 75 WebClear 23 Rnd 40 +/-Tol 3 R125 X H40 Donut Rnd 125 WebClear 45 Rnd 40 +/-Tol 3 R75 X H32 Donut Rnd 75 WebClear 23 Rnd 32 +/-Tol 3 R100 X H32 Donut Rnd 100 WebClear 34 Rnd 32 +/-Tol 3

46 You should have five new Padstacks by now. 47 Save your file and Exit. 48 Refer to Appendix A for creation of SMD and Multi-Layered Pad.

Appendix A - 30

LAB 4 CREATING CELL Objectives: To create the Cells (Footprint Data) in the Library Manager for PCB Layout. Use of Component Wizard for cell creation. Manual cell creation. Defining the Silkscreen and Placement outline of a component. Cell Creation 61 In this Exercise, you will be guided step by step to create the Cell (Footprint) Data for the Melody

Generator Project. 62 Invoke the Cell Editor. 63 Select the Partition: Melody. 64 Click the New Button.

Appendix A - 31

65 As the dialog appears, enter as follows.

66 Click Next >> and you will enter the Graphical Cell Editor environment.

67 The Place Pins dialog appears as above.

Appendix A - 32

68 Select all the pins by clicking on Pin 1, hold the Shift Key and click Pin 16.

69 Click on the Padstack Name column at Pin 16.

70 While holding down the Shift Key, select R75 X H32 as the Padstack to be used in this component. 71 All the Padstack Name in this column will be changed to R75 X H32. 72 Go to Pattern Place Tab and select the Pattern Type: as DIP.

Appendix A - 33

73 Click Place and Close. 74 If you have place any part of the circuit wrongly, you can undo it by hitting the Undo

Button. 75 Double-click the Silkscreen Outline and change the line width to 10. Silkscreen Outline 76 Located at the Lower Left Hand Side of the screen use the tool bar to change the Snap Grid to 25 th.

77 Now all you need to do now is to place the Placement Outline and you are done. 78 Click the button that is shown up as below.

79 Next click on the Rectangle button which is located at the bottom tool bar of the editor.

80 Draw a rectangular box around the component.

81 The Placement Outline serves as a guide to keep components from overlapping each other during

placement in PCB Layout. 82 Save and Exit from the Graphical Cell Editor. 83 You will see the DIP16 component that you have just created in the Cell Editor.

Appendix A - 34

84 Following the creation of the DIP16 package, we will create the Variable Resistor Footprint. 85 Since this package cannot be created with the Wizard, you will have to create it manually. 86 Same as before click on the New Cell Button. 87 Enter the Cell name: as RV.

88 Always use 2 layers to create Component Footprint. 89 Select Package group: as Discrete – Others, and Mount Type: as Through. 90 At the Place Pins dialog, select the Padstack Name as R100 X H40. 91 Do a Right Click and select Editor Control…, change the Route and ViaGrid to 50.

Appendix A - 35

92 Click the Display Control Button, select Place & Route Tab. 93 Check the Route Box, to display the Grids.

94 Select the First Pin and click the Place Button. 95 Place it at the Component Origin.

96 Since the Route Grid is 50, every snap point is 50 mils. 97 Select Pin 3, move it 4 snap points to the right of the Pin 1and place it there. 98 Next select Pin 2, move it 1 snap point to the right of the Pin 1and 8 snap point up.

99 Change to Draw Mode, to draw your Silkscreen Outline.

100 Set the Snap Grid: to 25.

Appendix A - 36

101 Click the Place Silkscreen Outline.

102 Change the Vertex Type to Round, and the Radius to 175.

103 Draw the Silkscreen and the Placement Outline as the component given below. Placement Outline

Silkscreen 104 Move the cursor to coordinate (100, 325), check the coordinates from windows Top Blue Bar.

Appendix A - 37

105 After reaching the 3rd Vertex, Change the Vertex Type to Corner. 106 Adjust the Vertex Type to back to Round at the last stretch of the arc.

107 Next draw the Placement Outline over it.

Appendix A - 38

108 Save the Cell and Exit.

109 Refer to Appendix B and create the rest of the component Footprints.

LAB 5 PIN MAPPING Objectives: Create a Part Database Partition in the Library Manager. Create a Mapping file that links the Symbol data to their respective Footprints. Create variable Mapping file for Discrete Component. Pin Mapping Pin Mapping is a process that defines the link between the Schematic Symbols and PCB Physical Footprint data. Some software does not require this definition, most do. This is usually used for physically

Appendix A - 39

mapping the pins from a symbol, for example an AND Gate, which has Pin Names like A, B and Y, to be mapped to the DIP14 footprint with Pins 1, 2 and 3.

A Pin 1 As the example above shows, Pin A of the AND Gates will be mapped to Pins 1, 4, 10 and 13 of the DIP14 Footprint. The supply VCC and ground GND of the IC can be automatically connected without physically drawing a wire to join the symbol. This way of definition allows the designer to readily access the packaging information from the Part Database. Definition of the type of component to be mapped is also very important. For example, the AND Gate above comes commonly in 2 packages, Dual In-line Package (DIP) and Small Outline (SO). Therefore you need to define the availability of both packages. By mapping the packages to the symbol, you can select the correct package used for the design. Part Database 110 In the Library Manager, return to the Partition Editor, Edit > Partition Editor... .

Appendix A - 40

111 Create a New Partition: MELODYPDB in the PDBs Tab.

112 OK to exit. 113 Invoke the Part Database Editor and select the MELODYPDB Partition.

114 Click the New Button. 115 A new Part Listing: NEW appears.

Appendix A - 41

116 Change the Part Number and Part Name to BC548. 117 The Part Number indicates the package the Symbol is going to use, the Part Name substitutes the

Symbol Name in the definition. 118 Change the Type under the Component Properties: to BJT, however you will not be using this portion

of the data for this design as it is for Simulation only. 119 Next, change the Reference des prefix: to Q.

120 Click Pin Mapping… , to enter the Mapping environment. 121 Select Import from the Symbol and symbol property list: .

122 You are going to import and link the Symbol and Cell data for the Transistor BC548. 123 Select Transistors Partition under the Symbols Tab and choose BC548. 124 Enter 1 for Number of slots in component:, this is to indicate that there is only 1 part in the package.

Appendix A - 42

125 The AND Gate example discussed earlier has a 4 parts in a package, therefore 4 slots will be allocated. 126 Select the Melody Partition under the Cells Tab and choose TR09.

127 Select OK to exit. 128 You will find under the Logical Tab, the Symbol Pins B, C and E in Slot #1 are not yet assigned to the

Cell.

Appendix A - 43

129 Select the Physical Tab and Map 2 for B, 1 for C and 3 for E.

130 Change the Property to Pin Type and Value to BiDir. 131 This is used for Design Verification in your Schematic. 132 Select OK to exit. Copy Database 133 Next, we will use the Copy Button to create the Part Database for BC558 from BC548.

134 Modify the Part Number and Part Name on the Part Listing from BC548_1 to BC558. 135 Click the Pin Mapping Button. 136 Since Mapping is the same, you will only need to change the Symbol Name to BC558. 137 Click OK to exit, and do a File > Save.

Appendix A - 44

Variable Footprint Database 29 There are many components that use different Footprints for various purposes, like smaller packages

for more compact designs. 30 Simply, a Capacitor has Surface Mount packaging used for small signal application, however if a

higher voltage rating is required Leaded package is still used. 31 Create a New Part with Part Number as RAD02-03 and Part Name as E-CAP. 32 The Part Name E-CAP here will be the general term used for Electrolytic Capacitor Symbol. 33 The Part Number RAD02-03 describes the specific Footprint to be used. 34 Change the Reference Des Prefix to C.

35 Go to Pin Mapping and import the Symbol of E-CAP and the Cell of RAD02-03. 36 Map the Pins from the Symbol to the Cell.

Appendix A - 45

37 Next, we are going to create the other package for the Electrolytic Capacitor, with the Footprint RAD01-02.

38 Same as before, make a copy of the E-CAP by clicking the Copy Button. 39 Change the Part Number this time to RAD01-02. 40 Click the Pin Mapping Button and change the Cell Name: to RAD01-02.

41 Click OK to exit, Save your File. Components with Swappable Pins 42 Components with Swappable Pins are typically Input Pins of Gates, general Capacitors and

Resistors that has no special Polarity. 43 Refer to the Pin Mapping Guide, and create the Resistor Part Database. 44 Select both pins using the Shift Key, and click the Swap Button. Select Pins 45 With reference to the Pin Mapping Guide, create the rest of the component database.

Appendix A - 46

Pin Mapping Guide Symbol Footprint Pin Mapping Footprint

Pin Swap Symbol Footprint

C 1 None B 2 E 3 C 1 None B 2 E 3 1 2 None 2 1 3 3 1 1 1 and 3 2 2 3 3 1 1 None 2 2 1 1 None 2 2

Appendix A - 47

1 1 1 and 2 2 2 1 1 1 and 2 2 2 1 3 None 2 1 3 4 4 2 1 1 1 and 2 2 2 1 1 1 and 2 2 2 1 1 None 2 2 3 3 . . . . . . 16 16

Appendix A - 48

LAB 6 SCHEMATIC ENTRY Objectives: To draw the Schematic of the Melody Generator. To compile the circuit and generate the netlist for PCB Layout Design Schematics Schematics are an important source of information as it serves as a way to convey the function of the circuit diagram between engineers. The circuitry is useless if the person who reads it does not know how it functions and how it is applied. For example, the circuitry below is given in Layout form. Do you know how does the circuit function ?

Usually it will take hours to figure out the function of the circuit. However, if this is given to you, you can readily say that it is an amplifier. Even without the component name given to you.

Maintaining a correct set of information with both Schematic and PCB Layout data is a good practice for future references and changes.

Appendix A - 49

Schematic Entry 138 Invoke the VeriBest Design Capture by clicking on

Start > Program > VeriBest VB99.0 > VeriBest Design Capture > Design Capture.

139 After launching VeriBest Design Capture, click Project – New from the menu. 140 A New Project Wizard appears to guide you through setting up your Project Folder.

141 Click on the button at the end of the Project Location: box and you will be prompted to select your

project directory to store all your project files.

142 Click on the right mouse button and create a new folder MyProject.

Appendix A - 50

143 Enter your Project Name: as Melody_Generator, and click Next >.

144 This screen allows you to enter other design files to be reused here, however, since this is your first

project click Next > to continue until Finish. 145 Similarly, VeriBest will create a Melody_Generator directory and subdirectories for proper file

storage.

Appendix A - 51

146 From the menu, click on File – New … and select Schematic.

147 Click OK. 148 You should see the Design Capture screen as below.

149 Next you will need to define the source of your Symbol library.

Appendix A - 52

150 Click Project – Settings … , select the button at the end of Central Library: box.

151 Locate the Melody folder for the libraries that you have created, and select the Melody.lmc file.

152 Click OK to apply and exit. 153 Click the Device Button on the Place Tool Bar.

Appendix A - 53

16 You can pick from the Device Menu the Components needed for the Schematic. 17 Use the Preview Screen to view the component Symbol that you pick.

18 Select the component CAP and place it on the screen. 19 Double click the component to change the Property. 20 Enter the Value of the Capacitor as 223 and Ref Designator as C3. 21 Set under the Visible column, Part Name and Part Number to None, click OK to apply.

Appendix A - 54

22 Select the Capacitor by clicking it once, as it turns white in color. 23 Rotate it by using the Rotate Left Button.

24 Use the buttons to adjust your Symbols to a Horizontal position. 25 Select the Reference Designator C3 and the Value 233, and use Rotate Right Button to turn it back to

a Vertical position.

26 Select the Capacitor again. 27 Use Ctrl C to copy and Ctrl V to paste. 28 Place it on the right hand side the first capacitor, with its Pin 1 touching the Pin 2 of C3.

29 Change the Reference Designator for C4. 30 Select the capacitor C4 and pull it to the Right. 31 The two capacitors is now connected by a Wire.

32 Place the symbol of BC548, and set the Reference Designator to Q1.

Appendix A - 55

33 Rotate the component Left and click the Mirror Button to set change the component to a horizontal position.

34 Click the Wire Button.

35 Point the cursor to the Base pin of Q1 (Pin B), and place the start point of the Wire by clicking the Left

Mouse Button once.

36 Move the cursor to Pin 1 of C3, use Double-click to join the wire.

37 Continue to join Pin C of Q1 to the wire connecting Pin 2 of C3 to Pin 1 of C4. Wire Junction 38 A Wire Junction is automatically placed at the intersection of the connection.

Appendix A - 56

39 Draw the schematic as below.

40 Once you have finished, run the Verification Tool, Tools – Verify. 41 There should be some warnings generated due to the difference in expressing component definition, but

no errors should be found. 42 If there is error, you can use the Error Search Button to review the errors.

43 If you are not sure, seek help from the instructor. 44 Go to Tools – Setup Parameter and click the General Tab.

Appendix A - 57

45 Change the Number of physical layers: to 2. 46 Click OK to Remap the layers, and OK to exit from the dialog.

47 Compile the Database with Tools – Compile CDB. 48 Check the Output Box to verify the status of the compilation.

49 Next, Package the circuit to attach the PCB Component Data to the circuit, Tools – Package Design. 50 Check the Output Box again to verify the status of packaging. 51 If there is error found, invoke the Windows Explorer and navigate yourself to the file PartPkg.log in

the directory of ..\MyProject\Melody_Generator\Integration\ .

52 Open the file and check the error at the end of the page. 53 If no error is found, you can Save your file and Exit the Design Capture.

Appendix A - 58

LAB 7 PCB DESIGN Objectives: To link the Compiled Database Netlist from the Melody Generator Project to the PCB. Placement of components based on Schematic Diagram. To setup the Design Rules for PCB Layout. AutoRouting PCB Design Designing a PCB is not as simple a task as it was in the early 1980s. Normal operating frequency during then for general household electronic products was in Kilohertz except for TVs and radios. Only during the end of the 80’s that we see a vast increase in speed like in Personal Computers, Mobile Phones, and many others used to be luxury items becoming a household necessity in everyday life. Computer is currently the major driving factor for speed today. Now most of our PCs are operating in the 300 - 500 Megahertz. High-speed equipment usually emits a lot of noise that cannot be heard by human ears, but dangerous enough to damage other equipment that is working along side them. Because of this, many products have to be compliant with the FCC, CE and other industrial standards for Electromagnetic Compatibility. In other words, the product has to be safe for use, does not suffer interference from and does not interfere with the performance of the equipment within the circuitry itself, and other equipment.

The example here shows the Radiation Effects of an antenna residing in the middle of a metallic box, with different sizes of holes on the wall of the box. The flower pattern is actually the Electromagnetic Field emitted by the antenna and leaking through the holes.

Appendix A - 59

In digital boards, a signal travelling from a source along a copper trace to the input of another gate will have a transmission delay of approximately 10 nanoseconds every 6 inches. Gate delay for every other IC is another 10ns, most of them have to synchronize. Failing to do so will sometime cause equipment malfunction when a gate fails to trigger or trigger at the wrong time.

In RF design, the frequency is so high that it changes the characteristics of the traces and the components. For example, a small film resistor of 10K Ohms at high frequency exhibits a capacitive characteristic due to the parasitic components that resides within it.

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PCB Design Rules To design a PCB there are a few things to take note of :

- Components should be placed on Top and/or Bottom Layers. - Basic Routing Layers goes to the Top and Bottom. - If there is not enough routing space, go into Internal Layers. - Always increase layer in pairs, 2, 4, 6. - Internal Layers can be changed to Power Planes to accommodate for supply connections. - Use Relief Connections for shorting to the planes. - Use Split Planes for multiple voltage circuits. - Placement of components should be in Cluster format for a good design. - Design for both Routability and Manufacturability. - Component Placement should also cater for the mechanical aspect of the product like

casing, component to component Clearances, and component Pick-and-Place clearance. - Avoid long traces unless it is absolutely necessary. - Avoid switching layers too frequently within a single trace. - High Frequency digital traces should cater for Timing, Delays and Synchronicity. - Use 45 Degrees angled routing and trace chamfer.

Expedition PCB 154 Invoke the VeriBest Expedition PCB by clicking on

Start > Program > VeriBest VB99.0 > Expedition PCB > Expedition PCB.

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155 Click File – New in the Expedition PCB. 156 Browse for the Source project filename:

C:\MyProject\Melody_Generator\Melody_Generator.prj

157 Click Next > and select the 2 Layer Template.

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158 Proceed to the last of the Wizard and click the Start or Continue Process.

159 Once Forward annotation is complete, you can view the Process Report to check for errors.

160 Click Finish to end. 161 Close the Job Management Wizard.

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162 Select File – Open, browse to the …MyProject\Melody_Generator\Pcb\ directory and select the

Melody_Generator.pcb file.

163 The Expedition PCB displays the PCB Board from the Template you have created in LAB 2.

164 Activate the VeriBest Design Capture.

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Component Placement Component Placement is very subjective to the kind of design that you are working on. There is no such thing as right or wrong placement, only good and bad. The idea is to achieve Maximum Routability without having to run a connection through a series of vias before it connects to the its destination.

Bad Placement Good Placement The Connections are joined by a series of rubber-band lines which is called Ratsnest. They are used as a guide for designers to forecast the routability of the board. For example, the having the ratsnest running in Parallel will ease the trace route with a direct connection without going through a single Via. Bad Trace Good Trace Ratsnest This concept holds true for all routing cases because the more Through Hole Via there is, the less space there is for you to route your trace. Apart from this, the more layers you change, the higher the distortion of the signal will get. Placements of component Types are very important too. For example, if you are designing a board with mixed technology and placements of components are on both sides, placing all the Surface Mount Components on one side of the board, and Through Hole Components on the other, you can save the production cost for this product. There are generally 2 types of Automatic Insertion Machine, SMD and Through Hole and they can only handle their specific function. If the Surface Mount Components placements are mixed with the Through Hole Components on both sides, the Machine will have to place all the Surface Mount Components on both sides first before the continuing with Through Hole Components thus increase the manufacturing process from 2 steps to 4.

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12 Resize the PCB and VBDC windows making them placed side by side to each other. 13 Temporarily remove the Workspace Panel for a better view by toggling View – Workspace.

14 Notice that the Schematic is now overlaid with pin mapped information corresponding to their

Footprints. 15 Click the Place Mode Button.

16 You can use the buttons to switch between Placement and Routing Mode, by clicking the Route Mode

Button beside it. 17 Under the Place Mode Button click the Place Parts and Cells Button.

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18 Change the placement Criterion: to Schematic Cross Probe. 19 Check the Attach selected parts to cursor.

20 Go to Setup – Editor Control and change the Primary Part Grid: to 10.

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21 You are now ready to place the Components on to the PCB. 22 Click on the Connector Symbol, J1. 23 Notice that the Footprint of J1 appears immediately on the PCB.

24 Rotate the component if you need to with these buttons.

25 The one at the end is the Push Part Button that allows you to toggle the Part Placement from Top to

Bottom, and vice versa. 26 Place all the components from the Schematic on to on to the PCB. 27 Design your own placements while bearing in mind the Design Rules specified in the beginning of this

Lab Session. 28 Save your file when you are done. Routing

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Routing is the process of connecting the copper traces for the components that you have placed on the board. Ratsnests are use as the guide for the computer to tell if the traces are going the right way. It also serves as a guide for the user to determine whether the board can be routed effectively. Component is a physical device, having Dimensions of Length, Width and Height. You need to estimate the Clearances between the devices in order to have space for the Insertion Machines to place the components. Same with Routing a trace, you need Clearances to prevent traces shorting to each other during manufacturing.

If you magnify a Printed Circuit Board 20 times, you will see that the traces are not as straight as you would have originally thought without the magnification. This due to manufacturing tolerances. If you do not have enough Clearance, the edges of the traces may just touch each other and cause a Short Circuit. The current minimum clearance in the PCB industry is 4 mils. However, it will be very costly to produce this kind of board. On the whole, you will need to know the Clearances to estimate routability. Therefore, as above, you will need to calculate the total space Clearance + Trace Width + Clearance between the two Pads if you need to route between them. If you have a 10 mils clearance and 12 mils trace. The minimum space in between the edge of the Pads is 32 mils. If you want 2 traces to go in between, you will need 54 mils of space. Over the years, PCB software has improved in algorithms to route the board automatically with as little human interventions as possible. However, the placements are still highly dependent on manual work. To a computer, it has not achieved the capability to think like human on good placement strategy. Autorouting (short for Automatic Routing) uses the computer to calculate the space in between Pads and automatically route a trace to connect the components. Years ago, many Autorouters are still Grid Based.

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Trace following the grid To route a board, the PCB is subdivided into 10 mil grids. All the traces are to run on the grid. However, if there are two pads that touch the grid and the Clearances from the edge of the pad is too close to the grid. The computer will not route the trace through because it does not have a grid to follow. Instead it will try a longer route to reach the destination, even if there is ample of space for the trace to go through. Currently Autorouting Technology has moved to Shape-Based Algorithm where the autorouter attaches the clearance on every pad and trace on the board. As it routes, it will calculate for the required space in between the obstacles before routing through. Higher end tool uses true 45 Degree algorithm for routing the PCB and allows Trace Expansions and calculates the Impedance of the trace during routing. A more advanced level incorporates Signal Integrity Simulation on top of the design. Design Rules 29 After you have placed all the Components, your board should look something like this.

30 You will now setup the Design Rules for routing. 31 First you will need to define your Via for routing, although it will be highly unlikely that you will need

them.

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32 Select Setup – Padstack Editor. 33 From the Padstack Tab, select the R75 X H32 Padstack, copy and rename it to 32VIA as below.

34 Save and Exit the Padstack Editor. 35 Click Setup – Setup Parameter. 36 Under the Via Tab change the Via Definition to 32VIA.

37 32VIA is now the default Via to be used for the routing. 38 Click OK to exit. 39 Next we will define the Routing Control setup.

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40 Invoke the Editor Control with Setup – Editor Control … , setup as below in the General Tab.

41 Proceed to the Routes Tab and add the following setting.

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42 Next, go to Setup – Net Classes and Clearances … , change the (Default) Class Trace Width as below.

43 This changes the Width of the traces to be used in this design. 44 Click to create a New class Power and set the Trace Width to 30 mils for all Layers.

45 You have just created a different Net Class named Power and any Net that has been assigned under this

class will follow the Rules defined for it.

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29 Proceed to the Clearance Tab and change the Default Clearance Rule to 20 mils.

30 You can use the New Button to create a New Rule, and set all the Clearances to 30 mils.

30 Select the above configuration and click New Class to Class Rule Button to configure the New Rule

setting. 31 However, we will NOT be using the New Rule therefore Delete it before you click OK.

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32 Lastly, enter the Net Properties Setup, with Setup – Net Properties … .

33 Change the Net Class for both VCC and GND to Power. 34 Click OK to exit. Autorouting 35 Turn on the Autorouter.

36 Delete the Fanout Pass, as it is used only for Surface Mount Devices.

37 Use the New Pass Button to create a Smooth Pass and use the Down

Arrow to move to it to the bottom of the list.

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38 Setup the Autorouter as follows.

39 Click the Route Button to start the Autoroute, Save the changes when prompted. 40 The Pass Check will clear off once the passes has been run. 41 The Route Status should read 100% when you are done. 42 The Routed board should look something like this.

43 Next, go to Setup – Padstack Editor... to create a Mounting Hole for your PCB.

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44 Create a Pad of Donut Rnd 50 WebClear 20 and a Hole of Rnd 50 +/- Tol 3.00. 45 Set the Type to Mounting Hole and Name the Padstack: MOUNT50.

46 Save and Exit the Padstack Editor. 47 Returning to your PCB, select from the menu, Edit – Place – Mounting Hole... .

48 Select the Padstack MOUNT50, and hit the Apply Button.

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49 Go to Setup – Editor Control... , change the Primary Part Grid to 100.0. 50 Place the Mounting Hole at all 4 corners of the PCB at an offset of 100 mils inwards.

51 Save your completed PCB file.

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LAB 8 CREATING GERBER FILES Objectives: Understanding the concept of Gerber Files and Aperture List. Generating Gerber Files for PCB fabrication Gerber Files A Gerber File is an Industrial Standard File Format that is used to describe all the information that appears in a particular Layer of the PCB. As you have learnt in the previous labs, a PCB is made of an assembly of copper layers connected together by Through Hole Pads and Vias. The components on the PCB have Padstacks that describes the pattern of connection, whether it is Thermal on a Plane or a Pad on a Routing Layer.

The Gerber File output from a PCB Design Tool will gather the information that is contained in each layer and store it in separate Layer Files. The idea is the same as printing a particular layer of the PCB on a piece of paper. This way all the information can accurately described layer by layer for the Photo-plotting Machine to print it on a film.

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Gerber File Format and Aperture List There are a few Standards for Gerber File Format, like RS274D, RS274X, FIRE9000 and EIE. The most commonly used Standards are RS274D and RS274X. The difference between these two is that RS274X has its Aperture File embedded into the Gerber File while RS274D uses a separate file to describe the Aperture. The Aperture File describes the Shape and Size of the Aperture and assigns a D-CODE to it. This forms a table of all the shapes and sizes of the Aperture to be used in the Gerber File. The assignment usually starts with D10 because D0 to D9 are preset Machine Command. Here is an example of an Aperture File.

D-CODE Shape Xsize Ysize Rotation

D10 Round 10 10 0

D11 Square 60 60 0

D12 Rectangle 100 60 90

…..

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The Gerber Data by itself contains the D-CODE, X and Y Coordinates of the Traces and Pads on the Design Layer. The Photo-plotting Machine deciphers the Size and Shape of the trace or pad by referring to the D-CODE table. Here is a sample of the Gerber RS274X format with Embedded Aperture. The file first describes the Unit used (Inch) and the Format of the Unit, (2 Integers, 3 Decimals). Next the Shape of the Custom Donut Aperture is described. The Size and Shape is Mapped to a D-CODE Table. In this case, %ADD10VB_DONUT,0.0750X0.0230X270.0000*% means :

D-CODE Shape Outer-size Inner-size Rotation

D10 VB_DONUT 0.075 0.023 270

%ADD10VB_DONUT, 0.0750X0.0230X270.

0000

%ADD12C,0.0100*%

%ADD11VB_DONUT, 0.1000X0.0340X0.0000*%

Generating RS274X Gerber File 165 In this exercise, you will be generating the Gerber Files that you have designed for the

Melody_Generator Project. 166 Go to Setup – Gerber Machine Format…, to setup the format of the Gerber Data to be generated.

G04 Layer : EtchLayer1Top.gdo* G04 Date : Thu Jul 29 09:47:10 1999* G04 VeriBest Example Gerber Output Definition* %ICAS*% %MOIN*% à (units in inch ) %FSLAX24Y24*% à (2 integers and 4 Decimals ) %OFA0.0000B0.0000*% G90* (Custom Aperture Definition ) %AMVB_DONUT* $2=$2X2* 1,1,$1,0,0* 1,0,$1-$2,0,0* (Aperture Size Definition ) % %ADD12C,0.0100*% %ADD10VB_DONUT,0.0750X0.0230X270.0000*% %ADD11VB_DONUT,0.1000X0.0340X0.0000*% (Draw Action ) G01* G54D10* X4284Y16470D03* X4319Y18652D03* 6319Y18652D03* Y15296D03* ….

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167 Enter the settings as below.

168 Save the setting by clicking on the Save Button and close it. 169 Click Setup – Setup Parameter... and select the Gerber Machine Format file:

GerberMachineFile1.gmf that you have just generated.

170 Go to Output – Gerber… , VeriBest Expedition PCB will request you to select the Gerber Plot Setup File from your Project Directory.

171 Select Yes, and pick the pltdes00.gpf file from the config directory.

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172 Select Yes, and pick the pltdes00.gpf file from the config directory. 173 You will see that all the Layers are checked in the Output Files Process list.

174 Each file name with the extension .gdo defines it as a Gerber File and the layer to be plotted. 175 Switch to the Contents Tab

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176 You can view the items present in the individual files by selecting them from the Output file: box and viewing them from the Items: box.

177 Go back to the Parameters Tab. 178 Uncheck all the files, leaving only the EtchLayer1Top.gdo and EtchLayer2.gdo. 179 These are the two Copper Layers that you will need to build your project. 180 Switch to the Contents Tab again.

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181 Add to the selections for the two layers, the Board Outline and the Mounting Holes.

182 Return to the Parameters Tab and click the Process Checked Output Files Button. 183 Expedition PCB will generate the two files and store it in your Output directory. 184 To check on the Gerber Files you will need to use a Gerber Viewer Tool to check on the accuracy of

the plot. 185 Invoke the integrated GerbTool Software by clicking on the Icon as below.

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186 Once you have entered the GerbTool Software you will see that the files are loaded in automatically for you.

187 However, you will not be able to see both of them until you have turn them on. 188 On the right panel, turn Layer 2 on by clicking on the 2 Button until a Red Box appears. 189 Change the Blue and Green colors of Layer 2 to another set of colors by clicking on the Blue Square

beside Layer 2.

190 Click on the Redraw Button. 191 You should see your Gerber Files as below.

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192 Save your Project Files and Exit.