sourcing and sinking inputs

SOURCING AND SINKING INPUTSDc input modules can either be sources or sinks for dc current. This depends on the transistor used in the input card and the polarity of the dc supply

NPNsinkscurrentto ground

Sinking

SourcingEquivalentcircuit

transistor sources current to load

Switch

sinks load

current

Switch sources

load current

PNP

SOURCING AND SINKING OUTPUTMODULES

Sourcing Connections Sinking Connections

Common

universal

positive

universal

RELATIONSHIP BETWEEN I/O HARDWARE AND MEMORY

Field I/O device is considered load. Must provide sources of potential for I/O

Output LoadOutput

Module

To voltage source

I/O points mapped to memory by PLC software. Users must specify address when programming. Determined by I/O hardware address

Memory

Map

StatusWord

PLC DATA FILE STRUCTURESTypical structure Allen-Bradley SLC500 Series

Memory structure

SystemMemory Application

memory

ROMholds PLC Operatingsystem

RAMHolds user programsand data filesI/O maps, programsbattery back-up

PLC DATA FILE STRUCTURES

Bit, timer, counter,integer data definedby user

0

1

2

3

4

5

6

7

8

9

10-255

Output Image

Input Image

Status

Bit

Timer

Counter

Control

Integer

Reserved

Network Comm.

User defined

FileIDnumber

AB SLC 500 Data File Identifiers

File Type File ID File Number

Output status O 0

Input status I 1

Processor Status

S 2

Bit file B 3

Timer T 4

Counter C 5

Control R 6

Integer N 7

Float Point F 8


addr.15 14 13 12 01211 10 9 8 7 6 5 4 3

Address depends on slot location of the Output cardand number of points

File 0 - Output image single memory words

O:1

O:2

O:5

00 10 1010

Slot addres

s

Point Map

Unused

OUTPUT IMAGE FILE

addr.15 14 13 12 01211 10 9 8 7 6 5 4 3

O:2

O:5

O:6

O:7

PLC has an 16 output card in slot 2An 8 output card in slot 5A 16 output card in slot 6 An 8 output card in slot 7

x

x

x

x

Invalid

Invalid

Each card assigned a word, unused bits are not addressable

INPUT IMAGE FILE

addr.15 14 13 12 01211 10 9 8 7 6 5 4 3

File 1 - Input image single memory words

I:0

I:3

I:4

Slot addres

s

Each card assigned a word, unused bits are not addressable

Address depends on slot location of the input card and number of points. Similar to Output map.

File 2 - Processor Status File

Contains information about how PLC and its operating system is functioning


Typical Information

monitoring and clearing hardware and software faultssetting of watchdog timer valueruntime errorsI/O errorsaverage scan times


File 3 - The Bit File Bit files used to represent control relays that were used in electromechanical systems.

Addressing bit data type

B3:n/bBit

identifier

Wordidentifier

Data Type(Bit)

File IDNumber

Example: For the following memory map

Determine the bit value associated with the addressesAddresses Bit value

B3:0/5 B3:1/7B3:2/12B3:3/3

1100

5712 3


addr.15 14 13 12 01211 10 9 8 7 6 5 4 3

B3:0

B3:1

B3:2

B3:3

1

0

Identifying individual bits

B3:2/8B3:1/9


File 4 - Timers. Each timer requires 3 words of data file

Word 0 - control word I/O bits and Internal controlWord 1 - preset valueWord 2 - accumulated value

15 14 13 0

0

1

2

EN TT DN INTERNAL USE ONLY

Preset Value (PRE)

Accumulated Value (ACC)

Timer file structure and addressing

Addressable BitsEN - timer enabled bitTT - timer timing bitDN - timer done bit

Data Structure is the same for on-delay and off-delay timers

ADDRESSING TIMER FILE DATA15 14 13 0

0

1

2

EN TT DN INTERNAL USE ONLY

Preset Value (PRE)


Tf:e.s/bGeneral form

Bit

Sub-element

Sub-elements

Element(Timer #)

Timer file #

Default 4

T4:0/15 = T4:0/EN

Examples

Timer 0; Timer enabled bit

T20:2.PRE preset of a timer defined in a user defined file area

T4:1.ACC or T4:1.2

Accumulated value of timer 1

T4:5/DN

Timer 5 done bit

T4:5.ACC/1

Bit one of accumulated value of Timer 5

More Examples

T4:2/TT

Timer timing bit: Timer 2

COUNTER FILE STRUCTURE

File 5 - CountersEach counter defined by three words in data file

15 14 13 0

0

1

2

CU CD DN INTERNAL USE ONLY

Preset Value (PRE)


OV UN UA

Word 0 - control word I/O bits and Internal controlWord 1 - preset valueWord 2 - accumulated value

Addressable Bits

CU - counter up enabled bitCD - counter down enabled bitDN - counter done bitOV - counter overflow bitUN - counter underflow bitUA - update accumulated value (only certain models)PRE - preset valueACC -accumulated value

COUNTER FILE STRUCTURE15 14 13 0

0

1

2

CU CD DN INTERNAL USE ONLY

Preset Value (PRE)


OV UN UA

Cf:e.s/bGeneral form

Bit

Sub-element

Element(Counter

#)

Counter file #

Default 5

Examples

C5:0/15 = C5:0/CU

Counter 0 count up bit

Preset of a counter defined in a userdefined file area

C5:1.ACC or C5:1.2

Accumulated value of counter

C5:5/DN

Counter 5 done bit

C5:5.ACC/1

Bit 1 of accumulated value of counter 5

C5:2/CD

Count down enable bit for counter 2

C20:2.PRE

More Examples

CONTROL AND INTEGER FILESFile 6 -Control File

Used to store status information for bit operations and stack control operations

File 7 – Integer Data Integer Data typesSigned integer (16 bit): range 0 -

+- 32767Unsigned integer (16 bit) range 0 -

65535

Addressing Integer valuesEach integer requires 1 word N7:n

Integer data Type

File ID Number

Word identifier

PLC LADDER LOGIC PROGRAMMING

Basic Concepts of PLC Ladder Logic Programming

Instructions look like schematic symbols

PLC ladder logic program based on logical “continuity”

Symbols attached to bit addresses in data maps

All input symbols must test true for the output symbol to be true

PLC LADDER LOGIC PROGRAMMING

Boolean Equation

Could program PLC in verbose language or use ladder logic symbols.Ladder logic used to reduce training of maintenance personnel

Example system

)CR2PB1( )LS3)CR2PB1(( SOLACR5CR4

BASIC PLC PROGRAMMING INSTRUCTIONS

Bit or relay Instructions - test memory location bits

Examine if closed: XICexamines an input bitfor closed condition

Examine if open: XIOexamines an input bit foran open condition

Logic of XIC

Input bit

Evaluation

Rung Effect

1 TRUE Pass logical continuity

0 FALSE Block logical continuity

Logic of XIC

Input bit

Evaluation

Rung Effect

1 FALSE Block logical continuity

0 TRUE Pass logical continuity

Bit address Bit address


Output Instructions – Toggle output map bits when rung evaluates true

Output Energize (OTE)

Instruction becomes true when all instructions to rung become true

Output latch and Output unlatch

Output latch become TRUE when input rung instructions become TRUE. Remains TRUE after rung becomes FALSE

Output unlatch is used to reset the output latch instruction

Bit address

Bit address

Bit address


One Shot Instruction

Input that allows an event to occur only once during a program scan.

OSR

Responds to only FALSE to TRUE transitions

More Output Instructions

Instruction only responds to rising hardware input signal

PROGRAMMING EXAMPLES

Rung Examples: What is the condition of the output instruction (T/F)?

I:0

01746-IA8

O:2

11746-OB16

OTE Instructi

on

XIC Instructi

onaddr.15 14 13 12 01211 10 9 8 7 6 5 4 3

I:0

I:3

I:4

0

Input image table shows a 0 bit, so XIC evaluates to a FALSE

PROGRAMMING EXAMPLESRung example continued:What is the condition of the output instruction (T/F)?

I:0

01746-IA8

O:2

11746-OB16

False

addr.15 14 13 12 01211 10 9 8 7 6 5 4 3

O:0

O:2

O:4

0

Rung is FALSE. so OTE is FALSE.

This gives 0 in output image

False

sourcing and sinking inputs

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